1 /* 2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 /* 8 * MPC8610HPCD board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 /* High Level Configuration Options */ 17 #define CONFIG_MPC8610 1 /* MPC8610 specific */ 18 #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ 19 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 20 21 #define CONFIG_SYS_TEXT_BASE 0xfff00000 22 23 /* video */ 24 #define CONFIG_FSL_DIU_FB 25 26 #ifdef CONFIG_FSL_DIU_FB 27 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) 28 #define CONFIG_VIDEO 29 #define CONFIG_CMD_BMP 30 #define CONFIG_CFB_CONSOLE 31 #define CONFIG_VIDEO_SW_CURSOR 32 #define CONFIG_VGA_AS_SINGLE_DEVICE 33 #define CONFIG_VIDEO_LOGO 34 #define CONFIG_VIDEO_BMP_LOGO 35 #endif 36 37 #ifdef RUN_DIAG 38 #define CONFIG_SYS_DIAG_ADDR 0xff800000 39 #endif 40 41 /* 42 * virtual address to be used for temporary mappings. There 43 * should be 128k free at this VA. 44 */ 45 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 46 47 #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ 48 #define CONFIG_PCI1 1 /* PCI controller 1 */ 49 #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ 50 #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ 51 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 52 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 53 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 54 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 55 56 #define CONFIG_ENV_OVERWRITE 57 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ 58 59 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ 60 #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ 61 #define CONFIG_ALTIVEC 1 62 63 /* 64 * L2CR setup -- make sure this is right for your board! 65 */ 66 #define CONFIG_SYS_L2 67 #define L2_INIT 0 68 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 69 70 #ifndef CONFIG_SYS_CLK_FREQ 71 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 72 #endif 73 74 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 75 #define CONFIG_MISC_INIT_R 1 76 77 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 78 #define CONFIG_SYS_MEMTEST_END 0x00400000 79 80 /* 81 * Base addresses -- Note these are effective addresses where the 82 * actual resources get mapped (not physical addresses) 83 */ 84 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 85 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 86 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 87 88 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 89 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 90 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW 91 92 /* DDR Setup */ 93 #define CONFIG_SYS_FSL_DDR2 94 #undef CONFIG_FSL_DDR_INTERACTIVE 95 #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ 96 #define CONFIG_DDR_SPD 97 98 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 99 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 100 101 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 102 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 103 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ 104 #define CONFIG_VERY_BIG_RAM 105 106 #define CONFIG_NUM_DDR_CONTROLLERS 1 107 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 108 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 109 110 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 111 112 /* These are used when DDR doesn't use SPD. */ 113 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 114 115 #if 0 /* TODO */ 116 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F 117 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 118 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 119 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 120 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 121 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 122 #define CONFIG_SYS_DDR_MODE_1 0x00480432 123 #define CONFIG_SYS_DDR_MODE_2 0x00000000 124 #define CONFIG_SYS_DDR_INTERVAL 0x06180100 125 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 126 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 127 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 128 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 129 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ 130 #define CONFIG_SYS_DDR_CONTROL2 0x04400010 131 132 #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 133 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 134 #define CONFIG_SYS_DDR_SBE 0x000f0000 135 136 #endif 137 138 #define CONFIG_ID_EEPROM 139 #define CONFIG_SYS_I2C_EEPROM_NXID 140 #define CONFIG_ID_EEPROM 141 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 142 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 143 144 #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ 145 #define CONFIG_SYS_FLASH_BASE2 0xf8000000 146 147 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} 148 149 #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ 150 #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ 151 152 #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ 153 #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ 154 #if 0 /* TODO */ 155 #define CONFIG_SYS_BR2_PRELIM 0xf0000000 156 #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ 157 #endif 158 #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ 159 #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ 160 161 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 162 #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ 163 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 164 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 165 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 166 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 167 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ 168 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 169 #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ 170 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 171 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 172 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 173 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 174 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 175 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 176 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 177 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 178 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ 179 180 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 181 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 182 183 #undef CONFIG_SYS_FLASH_CHECKSUM 184 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 185 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 186 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 187 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ 188 189 #define CONFIG_FLASH_CFI_DRIVER 190 #define CONFIG_SYS_FLASH_CFI 191 #define CONFIG_SYS_FLASH_EMPTY_INFO 192 193 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 194 #define CONFIG_SYS_RAMBOOT 195 #else 196 #undef CONFIG_SYS_RAMBOOT 197 #endif 198 199 #if defined(CONFIG_SYS_RAMBOOT) 200 #undef CONFIG_SPD_EEPROM 201 #define CONFIG_SYS_SDRAM_SIZE 256 202 #endif 203 204 #undef CONFIG_CLOCKS_IN_MHZ 205 206 #define CONFIG_SYS_INIT_RAM_LOCK 1 207 #ifndef CONFIG_SYS_INIT_RAM_LOCK 208 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 209 #else 210 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ 211 #endif 212 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 213 214 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 215 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 216 217 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ 218 #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ 219 220 /* Serial Port */ 221 #define CONFIG_CONS_INDEX 1 222 #define CONFIG_SYS_NS16550_SERIAL 223 #define CONFIG_SYS_NS16550_REG_SIZE 1 224 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 225 226 #define CONFIG_SYS_BAUDRATE_TABLE \ 227 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 228 229 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 230 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 231 232 /* maximum size of the flat tree (8K) */ 233 #define OF_FLAT_TREE_MAX_SIZE 8192 234 235 /* 236 * I2C 237 */ 238 #define CONFIG_SYS_I2C 239 #define CONFIG_SYS_I2C_FSL 240 #define CONFIG_SYS_FSL_I2C_SPEED 400000 241 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 242 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 243 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 244 245 /* 246 * General PCI 247 * Addresses are mapped 1-1. 248 */ 249 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 250 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS 251 #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS 252 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 253 #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 254 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 255 #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 256 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 257 258 /* controller 1, Base address 0xa000 */ 259 #define CONFIG_SYS_PCIE1_NAME "ULI" 260 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 261 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS 262 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 263 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 264 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 265 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ 266 267 /* controller 2, Base Address 0x9000 */ 268 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 269 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 270 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS 271 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 272 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ 273 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 274 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ 275 276 #if defined(CONFIG_PCI) 277 278 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 279 280 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 281 #define CONFIG_CMD_REGINFO 282 283 #define CONFIG_ULI526X 284 #ifdef CONFIG_ULI526X 285 #endif 286 287 /************************************************************ 288 * USB support 289 ************************************************************/ 290 #define CONFIG_PCI_OHCI 1 291 #define CONFIG_USB_OHCI_NEW 1 292 #define CONFIG_USB_KEYBOARD 1 293 #define CONFIG_SYS_STDIO_DEREGISTER 294 #define CONFIG_SYS_USB_EVENT_POLL 1 295 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 296 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 297 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 298 299 #if !defined(CONFIG_PCI_PNP) 300 #define PCI_ENET0_IOADDR 0xe0000000 301 #define PCI_ENET0_MEMADDR 0xe0000000 302 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 303 #endif 304 305 #define CONFIG_DOS_PARTITION 306 #define CONFIG_SCSI_AHCI 307 308 #ifdef CONFIG_SCSI_AHCI 309 #define CONFIG_LIBATA 310 #define CONFIG_SATA_ULI5288 311 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 312 #define CONFIG_SYS_SCSI_MAX_LUN 1 313 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 314 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 315 #endif 316 317 #endif /* CONFIG_PCI */ 318 319 /* 320 * BAT0 2G Cacheable, non-guarded 321 * 0x0000_0000 2G DDR 322 */ 323 #define CONFIG_SYS_DBAT0L (BATL_PP_RW) 324 #define CONFIG_SYS_IBAT0L (BATL_PP_RW) 325 326 /* 327 * BAT1 1G Cache-inhibited, guarded 328 * 0x8000_0000 256M PCI-1 Memory 329 * 0xa000_0000 256M PCI-Express 1 Memory 330 * 0x9000_0000 256M PCI-Express 2 Memory 331 */ 332 333 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 334 | BATL_GUARDEDSTORAGE) 335 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) 336 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 337 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 338 339 /* 340 * BAT2 16M Cache-inhibited, guarded 341 * 0xe100_0000 1M PCI-1 I/O 342 */ 343 344 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 345 | BATL_GUARDEDSTORAGE) 346 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) 347 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 348 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 349 350 /* 351 * BAT3 4M Cache-inhibited, guarded 352 * 0xe000_0000 4M CCSR 353 */ 354 355 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ 356 | BATL_GUARDEDSTORAGE) 357 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) 358 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) 359 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 360 361 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) 362 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 363 | BATL_PP_RW | BATL_CACHEINHIBIT \ 364 | BATL_GUARDEDSTORAGE) 365 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ 366 | BATU_BL_1M | BATU_VS | BATU_VP) 367 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ 368 | BATL_PP_RW | BATL_CACHEINHIBIT) 369 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU 370 #endif 371 372 /* 373 * BAT4 32M Cache-inhibited, guarded 374 * 0xe200_0000 1M PCI-Express 2 I/O 375 * 0xe300_0000 1M PCI-Express 1 I/O 376 */ 377 378 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ 379 | BATL_GUARDEDSTORAGE) 380 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) 381 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) 382 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U 383 384 /* 385 * BAT5 128K Cacheable, non-guarded 386 * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) 387 */ 388 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 389 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 390 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L 391 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U 392 393 /* 394 * BAT6 256M Cache-inhibited, guarded 395 * 0xf000_0000 256M FLASH 396 */ 397 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 398 | BATL_GUARDEDSTORAGE) 399 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 400 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) 401 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U 402 403 /* Map the last 1M of flash where we're running from reset */ 404 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 405 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 406 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 407 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ 408 | BATL_MEMCOHERENCE) 409 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY 410 411 /* 412 * BAT7 4M Cache-inhibited, guarded 413 * 0xe800_0000 4M PIXIS 414 */ 415 #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ 416 | BATL_GUARDEDSTORAGE) 417 #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) 418 #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 419 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U 420 421 /* 422 * Environment 423 */ 424 #ifndef CONFIG_SYS_RAMBOOT 425 #define CONFIG_ENV_IS_IN_FLASH 1 426 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 427 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ 428 #define CONFIG_ENV_SIZE 0x2000 429 #else 430 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 431 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 432 #define CONFIG_ENV_SIZE 0x2000 433 #endif 434 435 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 436 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 437 438 /* 439 * BOOTP options 440 */ 441 #define CONFIG_BOOTP_BOOTFILESIZE 442 #define CONFIG_BOOTP_BOOTPATH 443 #define CONFIG_BOOTP_GATEWAY 444 #define CONFIG_BOOTP_HOSTNAME 445 446 /* 447 * Command line configuration. 448 */ 449 450 #if defined(CONFIG_PCI) 451 #define CONFIG_CMD_PCI 452 #define CONFIG_SCSI 453 #endif 454 455 #define CONFIG_WATCHDOG /* watchdog enabled */ 456 #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ 457 458 /* 459 * Miscellaneous configurable options 460 */ 461 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 462 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 463 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 464 465 #if defined(CONFIG_CMD_KGDB) 466 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 467 #else 468 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 469 #endif 470 471 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 472 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 473 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 474 475 /* 476 * For booting Linux, the board info and command line data 477 * have to be in the first 8 MB of memory, since this is 478 * the maximum mapped by the Linux kernel during initialization. 479 */ 480 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 481 482 #if defined(CONFIG_CMD_KGDB) 483 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 484 #endif 485 486 /* 487 * Environment Configuration 488 */ 489 #define CONFIG_IPADDR 192.168.1.100 490 491 #define CONFIG_HOSTNAME unknown 492 #define CONFIG_ROOTPATH "/opt/nfsroot" 493 #define CONFIG_BOOTFILE "uImage" 494 #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin 495 496 #define CONFIG_SERVERIP 192.168.1.1 497 #define CONFIG_GATEWAYIP 192.168.1.1 498 #define CONFIG_NETMASK 255.255.255.0 499 500 /* default location for tftp and bootm */ 501 #define CONFIG_LOADADDR 1000000 502 503 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 504 505 #define CONFIG_BAUDRATE 115200 506 507 #if defined(CONFIG_PCI1) 508 #define PCI_ENV \ 509 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ 510 "echo e;md ${a}e00 9\0" \ 511 "pci1regs=setenv a e0008; run pcireg\0" \ 512 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ 513 "pci d.w $b.0 56 1\0" \ 514 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ 515 "pci w.w $b.0 56 ffff\0" \ 516 "pci1err=setenv a e0008; run pcierr\0" \ 517 "pci1errc=setenv a e0008; run pcierrc\0" 518 #else 519 #define PCI_ENV "" 520 #endif 521 522 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) 523 #define PCIE_ENV \ 524 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ 525 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ 526 "pcie1regs=setenv a e000a; run pciereg\0" \ 527 "pcie2regs=setenv a e0009; run pciereg\0" \ 528 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ 529 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ 530 "pci d $b.0 130 1\0" \ 531 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ 532 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ 533 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ 534 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ 535 "pcie1err=setenv a e000a; run pcieerr\0" \ 536 "pcie2err=setenv a e0009; run pcieerr\0" \ 537 "pcie1errc=setenv a e000a; run pcieerrc\0" \ 538 "pcie2errc=setenv a e0009; run pcieerrc\0" 539 #else 540 #define PCIE_ENV "" 541 #endif 542 543 #define DMA_ENV \ 544 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ 545 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ 546 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ 547 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ 548 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ 549 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ 550 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ 551 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" 552 553 #ifdef ENV_DEBUG 554 #define CONFIG_EXTRA_ENV_SETTINGS \ 555 "netdev=eth0\0" \ 556 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 557 "tftpflash=tftpboot $loadaddr $uboot; " \ 558 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 559 " +$filesize; " \ 560 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 561 " +$filesize; " \ 562 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 563 " $filesize; " \ 564 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 565 " +$filesize; " \ 566 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 567 " $filesize\0" \ 568 "consoledev=ttyS0\0" \ 569 "ramdiskaddr=2000000\0" \ 570 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 571 "fdtaddr=c00000\0" \ 572 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 573 "bdev=sda3\0" \ 574 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ 575 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ 576 "maxcpus=1" \ 577 "eoi=mw e00400b0 0\0" \ 578 "iack=md e00400a0 1\0" \ 579 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ 580 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ 581 "md ${a}f00 5\0" \ 582 "ddr1regs=setenv a e0002; run ddrreg\0" \ 583 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ 584 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ 585 "md ${a}e60 1; md ${a}ef0 1d\0" \ 586 "guregs=setenv a e00e0; run gureg\0" \ 587 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ 588 "mcmregs=setenv a e0001; run mcmreg\0" \ 589 "diuregs=md e002c000 1d\0" \ 590 "dium=mw e002c01c\0" \ 591 "diuerr=md e002c014 1\0" \ 592 "pmregs=md e00e1000 2b\0" \ 593 "lawregs=md e0000c08 4b\0" \ 594 "lbcregs=md e0005000 36\0" \ 595 "dma0regs=md e0021100 12\0" \ 596 "dma1regs=md e0021180 12\0" \ 597 "dma2regs=md e0021200 12\0" \ 598 "dma3regs=md e0021280 12\0" \ 599 PCI_ENV \ 600 PCIE_ENV \ 601 DMA_ENV 602 #else 603 #define CONFIG_EXTRA_ENV_SETTINGS \ 604 "netdev=eth0\0" \ 605 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 606 "consoledev=ttyS0\0" \ 607 "ramdiskaddr=2000000\0" \ 608 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ 609 "fdtaddr=c00000\0" \ 610 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ 611 "bdev=sda3\0" 612 #endif 613 614 #define CONFIG_NFSBOOTCOMMAND \ 615 "setenv bootargs root=/dev/nfs rw " \ 616 "nfsroot=$serverip:$rootpath " \ 617 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 618 "console=$consoledev,$baudrate $othbootargs;" \ 619 "tftp $loadaddr $bootfile;" \ 620 "tftp $fdtaddr $fdtfile;" \ 621 "bootm $loadaddr - $fdtaddr" 622 623 #define CONFIG_RAMBOOTCOMMAND \ 624 "setenv bootargs root=/dev/ram rw " \ 625 "console=$consoledev,$baudrate $othbootargs;" \ 626 "tftp $ramdiskaddr $ramdiskfile;" \ 627 "tftp $loadaddr $bootfile;" \ 628 "tftp $fdtaddr $fdtfile;" \ 629 "bootm $loadaddr $ramdiskaddr $fdtaddr" 630 631 #define CONFIG_BOOTCOMMAND \ 632 "setenv bootargs root=/dev/$bdev rw " \ 633 "console=$consoledev,$baudrate $othbootargs;" \ 634 "tftp $loadaddr $bootfile;" \ 635 "tftp $fdtaddr $fdtfile;" \ 636 "bootm $loadaddr - $fdtaddr" 637 638 #endif /* __CONFIG_H */ 639