1 /*
2  * Copyright 2007-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0
5  */
6 
7 /*
8  * MPC8610HPCD board configuration file
9  */
10 
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13 
14 /* High Level Configuration Options */
15 #define CONFIG_LINUX_RESET_VEC	0x100	/* Reset vector used by Linux */
16 
17 #define	CONFIG_SYS_TEXT_BASE	0xfff00000
18 
19 /* video */
20 #define CONFIG_FSL_DIU_FB
21 
22 #ifdef CONFIG_FSL_DIU_FB
23 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x2c000)
24 #define CONFIG_CMD_BMP
25 #define CONFIG_VIDEO_LOGO
26 #define CONFIG_VIDEO_BMP_LOGO
27 #endif
28 
29 #ifdef RUN_DIAG
30 #define CONFIG_SYS_DIAG_ADDR		0xff800000
31 #endif
32 
33 /*
34  * virtual address to be used for temporary mappings.  There
35  * should be 128k free at this VA.
36  */
37 #define CONFIG_SYS_SCRATCH_VA	0xc0000000
38 
39 #define CONFIG_PCI1		1	/* PCI controller 1 */
40 #define CONFIG_PCIE1		1	/* PCIe 1 connected to ULI bridge */
41 #define CONFIG_PCIE2		1	/* PCIe 2 connected to slot */
42 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
43 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
44 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
45 
46 #define CONFIG_ENV_OVERWRITE
47 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
48 
49 #define CONFIG_BAT_RW		1	/* Use common BAT rw code */
50 #define CONFIG_HIGH_BATS	1	/* High BATs supported & enabled */
51 #define CONFIG_ALTIVEC		1
52 
53 /*
54  * L2CR setup -- make sure this is right for your board!
55  */
56 #define CONFIG_SYS_L2
57 #define L2_INIT		0
58 #define L2_ENABLE	(L2CR_L2E |0x00100000 )
59 
60 #ifndef CONFIG_SYS_CLK_FREQ
61 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
62 #endif
63 
64 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
65 #define CONFIG_MISC_INIT_R		1
66 
67 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
68 #define CONFIG_SYS_MEMTEST_END		0x00400000
69 
70 /*
71  * Base addresses -- Note these are effective addresses where the
72  * actual resources get mapped (not physical addresses)
73  */
74 #define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
75 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
76 
77 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
78 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0x0
79 #define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR_PHYS_LOW
80 
81 /* DDR Setup */
82 #define CONFIG_SYS_FSL_DDR2
83 #undef CONFIG_FSL_DDR_INTERACTIVE
84 #define CONFIG_SPD_EEPROM		/* Use SPD for DDR */
85 #define CONFIG_DDR_SPD
86 
87 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
88 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
89 
90 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
91 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
92 #define CONFIG_SYS_MAX_DDR_BAT_SIZE	0x80000000	/* BAT mapping size */
93 #define CONFIG_VERY_BIG_RAM
94 
95 #define CONFIG_NUM_DDR_CONTROLLERS	1
96 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
97 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
98 
99 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
100 
101 /* These are used when DDR doesn't use SPD.  */
102 #define CONFIG_SYS_SDRAM_SIZE	256		/* DDR is 256MB */
103 
104 #if 0 /* TODO */
105 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000000F
106 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
107 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
108 #define CONFIG_SYS_DDR_TIMING_0	0x00260802
109 #define CONFIG_SYS_DDR_TIMING_1	0x3935d322
110 #define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
111 #define CONFIG_SYS_DDR_MODE_1		0x00480432
112 #define CONFIG_SYS_DDR_MODE_2		0x00000000
113 #define CONFIG_SYS_DDR_INTERVAL	0x06180100
114 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
115 #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
116 #define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
117 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
118 #define CONFIG_SYS_DDR_CONTROL		0xe3008000	/* Type = DDR2 */
119 #define CONFIG_SYS_DDR_CONTROL2	0x04400010
120 
121 #define CONFIG_SYS_DDR_ERR_INT_EN	0x00000000
122 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000
123 #define CONFIG_SYS_DDR_SBE		0x000f0000
124 
125 #endif
126 
127 #define CONFIG_ID_EEPROM
128 #define CONFIG_SYS_I2C_EEPROM_NXID
129 #define CONFIG_ID_EEPROM
130 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
131 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
132 
133 #define CONFIG_SYS_FLASH_BASE		0xf0000000 /* start of FLASH 128M */
134 #define CONFIG_SYS_FLASH_BASE2		0xf8000000
135 
136 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
137 
138 #define CONFIG_SYS_BR0_PRELIM		0xf8001001 /* port size 16bit */
139 #define CONFIG_SYS_OR0_PRELIM		0xf8006e65 /* 128MB NOR Flash*/
140 
141 #define CONFIG_SYS_BR1_PRELIM		0xf0001001 /* port size 16bit */
142 #define CONFIG_SYS_OR1_PRELIM		0xf8006e65 /* 128MB Promjet */
143 #if 0 /* TODO */
144 #define CONFIG_SYS_BR2_PRELIM		0xf0000000
145 #define CONFIG_SYS_OR2_PRELIM		0xf0000000 /* 256MB NAND Flash - bank 1 */
146 #endif
147 #define CONFIG_SYS_BR3_PRELIM		0xe8000801 /* port size 8bit */
148 #define CONFIG_SYS_OR3_PRELIM		0xfff06ff7 /* 1MB PIXIS area*/
149 
150 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
151 #define PIXIS_BASE	0xe8000000	/* PIXIS registers */
152 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
153 #define PIXIS_VER		0x1	/* Board version at offset 1 */
154 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
155 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
156 #define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch */
157 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
158 #define PIXIS_BRDCFG0		0x8	/* PIXIS Board Configuration Register0*/
159 #define PIXIS_VCTL		0x10	/* VELA Control Register */
160 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
161 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
162 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
163 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
164 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
165 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
166 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
167 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0xC0    /* Reset altbank mask */
168 
169 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
170 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
171 
172 #undef	CONFIG_SYS_FLASH_CHECKSUM
173 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
174 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
175 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
176 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000	/* early monitor loc */
177 
178 #define CONFIG_FLASH_CFI_DRIVER
179 #define CONFIG_SYS_FLASH_CFI
180 #define CONFIG_SYS_FLASH_EMPTY_INFO
181 
182 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
183 #define CONFIG_SYS_RAMBOOT
184 #else
185 #undef	CONFIG_SYS_RAMBOOT
186 #endif
187 
188 #if defined(CONFIG_SYS_RAMBOOT)
189 #undef CONFIG_SPD_EEPROM
190 #define CONFIG_SYS_SDRAM_SIZE	256
191 #endif
192 
193 #undef CONFIG_CLOCKS_IN_MHZ
194 
195 #define CONFIG_SYS_INIT_RAM_LOCK	1
196 #ifndef CONFIG_SYS_INIT_RAM_LOCK
197 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
198 #else
199 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4000000	/* Initial RAM address */
200 #endif
201 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
202 
203 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
204 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
205 
206 #define CONFIG_SYS_MONITOR_LEN		(512 * 1024)	/* Reserve 512 KB for Mon */
207 #define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
208 
209 /* Serial Port */
210 #define CONFIG_CONS_INDEX	1
211 #define CONFIG_SYS_NS16550_SERIAL
212 #define CONFIG_SYS_NS16550_REG_SIZE	1
213 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
214 
215 #define CONFIG_SYS_BAUDRATE_TABLE \
216 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
217 
218 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
219 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
220 
221 /* maximum size of the flat tree (8K) */
222 #define OF_FLAT_TREE_MAX_SIZE	8192
223 
224 /*
225  * I2C
226  */
227 #define CONFIG_SYS_I2C
228 #define CONFIG_SYS_I2C_FSL
229 #define CONFIG_SYS_FSL_I2C_SPEED	400000
230 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
231 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
232 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
233 
234 /*
235  * General PCI
236  * Addresses are mapped 1-1.
237  */
238 #define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
239 #define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
240 #define CONFIG_SYS_PCI1_MEM_VIRT	CONFIG_SYS_PCI1_MEM_BUS
241 #define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
242 #define CONFIG_SYS_PCI1_IO_BUS	0x0000000
243 #define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
244 #define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
245 #define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
246 
247 /* controller 1, Base address 0xa000 */
248 #define CONFIG_SYS_PCIE1_NAME		"ULI"
249 #define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
250 #define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
251 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
252 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
253 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
254 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/* 1M */
255 
256 /* controller 2, Base Address 0x9000 */
257 #define CONFIG_SYS_PCIE2_NAME		"Slot 1"
258 #define CONFIG_SYS_PCIE2_MEM_BUS	0x90000000
259 #define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BUS
260 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
261 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000	/* reuse mem LAW */
262 #define CONFIG_SYS_PCIE2_IO_PHYS	0xe2000000
263 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00100000	/* 1M */
264 
265 #if defined(CONFIG_PCI)
266 
267 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
268 
269 #define CONFIG_CMD_REGINFO
270 
271 #define CONFIG_ULI526X
272 #ifdef CONFIG_ULI526X
273 #endif
274 
275 /************************************************************
276  * USB support
277  ************************************************************/
278 #define CONFIG_PCI_OHCI		1
279 #define CONFIG_USB_OHCI_NEW		1
280 #define CONFIG_SYS_USB_EVENT_POLL	1
281 #define CONFIG_SYS_USB_OHCI_SLOT_NAME	"ohci_pci"
282 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
283 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS	1
284 
285 #if !defined(CONFIG_PCI_PNP)
286 #define PCI_ENET0_IOADDR	0xe0000000
287 #define PCI_ENET0_MEMADDR	0xe0000000
288 #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
289 #endif
290 
291 #define CONFIG_DOS_PARTITION
292 #define CONFIG_SCSI_AHCI
293 
294 #ifdef CONFIG_SCSI_AHCI
295 #define CONFIG_LIBATA
296 #define CONFIG_SATA_ULI5288
297 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
298 #define CONFIG_SYS_SCSI_MAX_LUN	1
299 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
300 #define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
301 #endif
302 
303 #endif	/* CONFIG_PCI */
304 
305 /*
306  * BAT0		2G	Cacheable, non-guarded
307  * 0x0000_0000	2G	DDR
308  */
309 #define CONFIG_SYS_DBAT0L	(BATL_PP_RW)
310 #define CONFIG_SYS_IBAT0L	(BATL_PP_RW)
311 
312 /*
313  * BAT1		1G	Cache-inhibited, guarded
314  * 0x8000_0000	256M	PCI-1 Memory
315  * 0xa000_0000	256M	PCI-Express 1 Memory
316  * 0x9000_0000	256M	PCI-Express 2 Memory
317  */
318 
319 #define CONFIG_SYS_DBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
320 			| BATL_GUARDEDSTORAGE)
321 #define CONFIG_SYS_DBAT1U	(CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
322 #define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
323 #define CONFIG_SYS_IBAT1U	CONFIG_SYS_DBAT1U
324 
325 /*
326  * BAT2		16M	Cache-inhibited, guarded
327  * 0xe100_0000	1M	PCI-1 I/O
328  */
329 
330 #define CONFIG_SYS_DBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
331 			| BATL_GUARDEDSTORAGE)
332 #define CONFIG_SYS_DBAT2U	(CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
333 #define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
334 #define CONFIG_SYS_IBAT2U	CONFIG_SYS_DBAT2U
335 
336 /*
337  * BAT3		4M	Cache-inhibited, guarded
338  * 0xe000_0000	4M	CCSR
339  */
340 
341 #define CONFIG_SYS_DBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
342 			| BATL_GUARDEDSTORAGE)
343 #define CONFIG_SYS_DBAT3U	(CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
344 #define CONFIG_SYS_IBAT3L	(CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
345 #define CONFIG_SYS_IBAT3U	CONFIG_SYS_DBAT3U
346 
347 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
348 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
349 				       | BATL_PP_RW | BATL_CACHEINHIBIT \
350 				       | BATL_GUARDEDSTORAGE)
351 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
352 				       | BATU_BL_1M | BATU_VS | BATU_VP)
353 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
354 				       | BATL_PP_RW | BATL_CACHEINHIBIT)
355 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
356 #endif
357 
358 /*
359  * BAT4		32M	Cache-inhibited, guarded
360  * 0xe200_0000	1M	PCI-Express 2 I/O
361  * 0xe300_0000	1M	PCI-Express 1 I/O
362  */
363 
364 #define CONFIG_SYS_DBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
365 			| BATL_GUARDEDSTORAGE)
366 #define CONFIG_SYS_DBAT4U	(CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
367 #define CONFIG_SYS_IBAT4L	(CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
368 #define CONFIG_SYS_IBAT4U	CONFIG_SYS_DBAT4U
369 
370 /*
371  * BAT5		128K	Cacheable, non-guarded
372  * 0xe400_0000	128K	Init RAM for stack in the CPU DCache (no backing memory)
373  */
374 #define CONFIG_SYS_DBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
375 #define CONFIG_SYS_DBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
376 #define CONFIG_SYS_IBAT5L	CONFIG_SYS_DBAT5L
377 #define CONFIG_SYS_IBAT5U	CONFIG_SYS_DBAT5U
378 
379 /*
380  * BAT6		256M	Cache-inhibited, guarded
381  * 0xf000_0000	256M	FLASH
382  */
383 #define CONFIG_SYS_DBAT6L	(CONFIG_SYS_FLASH_BASE	 | BATL_PP_RW | BATL_CACHEINHIBIT \
384 			| BATL_GUARDEDSTORAGE)
385 #define CONFIG_SYS_DBAT6U	(CONFIG_SYS_FLASH_BASE	 | BATU_BL_256M | BATU_VS | BATU_VP)
386 #define CONFIG_SYS_IBAT6L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
387 #define CONFIG_SYS_IBAT6U	CONFIG_SYS_DBAT6U
388 
389 /* Map the last 1M of flash where we're running from reset */
390 #define CONFIG_SYS_DBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
391 				 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
392 #define CONFIG_SYS_DBAT6U_EARLY	(CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
393 #define CONFIG_SYS_IBAT6L_EARLY	(CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
394 				 | BATL_MEMCOHERENCE)
395 #define CONFIG_SYS_IBAT6U_EARLY	CONFIG_SYS_DBAT6U_EARLY
396 
397 /*
398  * BAT7		4M	Cache-inhibited, guarded
399  * 0xe800_0000	4M	PIXIS
400  */
401 #define CONFIG_SYS_DBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
402 			| BATL_GUARDEDSTORAGE)
403 #define CONFIG_SYS_DBAT7U	(PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
404 #define CONFIG_SYS_IBAT7L	(PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
405 #define CONFIG_SYS_IBAT7U	CONFIG_SYS_DBAT7U
406 
407 /*
408  * Environment
409  */
410 #ifndef CONFIG_SYS_RAMBOOT
411 #define CONFIG_ENV_IS_IN_FLASH	1
412 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
413 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 126k (one sector) for env */
414 #define CONFIG_ENV_SIZE		0x2000
415 #else
416 #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
417 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
418 #define CONFIG_ENV_SIZE		0x2000
419 #endif
420 
421 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
422 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
423 
424 /*
425  * BOOTP options
426  */
427 #define CONFIG_BOOTP_BOOTFILESIZE
428 #define CONFIG_BOOTP_BOOTPATH
429 #define CONFIG_BOOTP_GATEWAY
430 #define CONFIG_BOOTP_HOSTNAME
431 
432 /*
433  * Command line configuration.
434  */
435 
436 #if defined(CONFIG_PCI)
437 #define CONFIG_CMD_PCI
438 #define CONFIG_SCSI
439 #endif
440 
441 #define CONFIG_WATCHDOG			/* watchdog enabled */
442 #define CONFIG_SYS_WATCHDOG_FREQ	5000	/* Feed interval, 5s */
443 
444 /*
445  * Miscellaneous configurable options
446  */
447 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
448 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
449 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
450 
451 #if defined(CONFIG_CMD_KGDB)
452 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
453 #else
454 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
455 #endif
456 
457 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
458 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
459 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
460 
461 /*
462  * For booting Linux, the board info and command line data
463  * have to be in the first 8 MB of memory, since this is
464  * the maximum mapped by the Linux kernel during initialization.
465  */
466 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20)	/* Initial Memory map for Linux*/
467 #define CONFIG_SYS_BOOTM_LEN	(256 << 20)	/* Increase max gunzip size */
468 
469 #if defined(CONFIG_CMD_KGDB)
470 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
471 #endif
472 
473 /*
474  * Environment Configuration
475  */
476 #define CONFIG_IPADDR		192.168.1.100
477 
478 #define CONFIG_HOSTNAME		unknown
479 #define CONFIG_ROOTPATH		"/opt/nfsroot"
480 #define CONFIG_BOOTFILE		"uImage"
481 #define CONFIG_UBOOTPATH	8610hpcd/u-boot.bin
482 
483 #define CONFIG_SERVERIP		192.168.1.1
484 #define CONFIG_GATEWAYIP	192.168.1.1
485 #define CONFIG_NETMASK		255.255.255.0
486 
487 /* default location for tftp and bootm */
488 #define CONFIG_LOADADDR		0x10000000
489 
490 #undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
491 
492 #define CONFIG_BAUDRATE	115200
493 
494 #if defined(CONFIG_PCI1)
495 #define PCI_ENV \
496  "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
497 	"echo e;md ${a}e00 9\0" \
498  "pci1regs=setenv a e0008; run pcireg\0" \
499  "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
500 	"pci d.w $b.0 56 1\0" \
501  "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
502 	"pci w.w $b.0 56 ffff\0"	\
503  "pci1err=setenv a e0008; run pcierr\0"	\
504  "pci1errc=setenv a e0008; run pcierrc\0"
505 #else
506 #define	PCI_ENV ""
507 #endif
508 
509 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
510 #define PCIE_ENV \
511  "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
512 	"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
513  "pcie1regs=setenv a e000a; run pciereg\0"	\
514  "pcie2regs=setenv a e0009; run pciereg\0"	\
515  "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
516 	"pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;"	\
517 	"pci d $b.0 130 1\0" \
518  "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
519 	"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
520 	"pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0"		\
521  "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0"	\
522  "pcie1err=setenv a e000a; run pcieerr\0"	\
523  "pcie2err=setenv a e0009; run pcieerr\0"	\
524  "pcie1errc=setenv a e000a; run pcieerrc\0"	\
525  "pcie2errc=setenv a e0009; run pcieerrc\0"
526 #else
527 #define	PCIE_ENV ""
528 #endif
529 
530 #define DMA_ENV \
531  "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
532 	"mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
533  "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
534 	"mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
535  "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
536 	"mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
537  "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
538 	"mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
539 
540 #ifdef ENV_DEBUG
541 #define	CONFIG_EXTRA_ENV_SETTINGS				\
542 "netdev=eth0\0"							\
543 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
544 "tftpflash=tftpboot $loadaddr $uboot; "				\
545 	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
546 		" +$filesize; "	\
547 	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
548 		" +$filesize; "	\
549 	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
550 		" $filesize; "	\
551 	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
552 		" +$filesize; "	\
553 	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
554 		" $filesize\0"	\
555 "consoledev=ttyS0\0"						\
556 "ramdiskaddr=0x18000000\0"					\
557 "ramdiskfile=8610hpcd/ramdisk.uboot\0"				\
558 "fdtaddr=0x17c00000\0"						\
559 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"				\
560 "bdev=sda3\0"					\
561 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
562 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
563 "maxcpus=1"	\
564 "eoi=mw e00400b0 0\0"						\
565 "iack=md e00400a0 1\0"						\
566 "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
567 	"md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
568 	"md ${a}f00 5\0" \
569 "ddr1regs=setenv a e0002; run ddrreg\0" \
570 "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
571 	"md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
572 	"md ${a}e60 1; md ${a}ef0 1d\0" \
573 "guregs=setenv a e00e0; run gureg\0" \
574 "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
575 "mcmregs=setenv a e0001; run mcmreg\0" \
576 "diuregs=md e002c000 1d\0" \
577 "dium=mw e002c01c\0" \
578 "diuerr=md e002c014 1\0" \
579 "pmregs=md e00e1000 2b\0" \
580 "lawregs=md e0000c08 4b\0" \
581 "lbcregs=md e0005000 36\0" \
582 "dma0regs=md e0021100 12\0" \
583 "dma1regs=md e0021180 12\0" \
584 "dma2regs=md e0021200 12\0" \
585 "dma3regs=md e0021280 12\0" \
586  PCI_ENV \
587  PCIE_ENV \
588  DMA_ENV
589 #else
590 #define CONFIG_EXTRA_ENV_SETTINGS				\
591 	"netdev=eth0\0"						\
592 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
593 	"consoledev=ttyS0\0"					\
594 	"ramdiskaddr=0x18000000\0"				\
595 	"ramdiskfile=8610hpcd/ramdisk.uboot\0"			\
596 	"fdtaddr=0x17c00000\0"					\
597 	"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0"			\
598 	"bdev=sda3\0"
599 #endif
600 
601 #define CONFIG_NFSBOOTCOMMAND					\
602  "setenv bootargs root=/dev/nfs rw "				\
603 	"nfsroot=$serverip:$rootpath "				\
604 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
605 	"console=$consoledev,$baudrate $othbootargs;"		\
606  "tftp $loadaddr $bootfile;"					\
607  "tftp $fdtaddr $fdtfile;"					\
608  "bootm $loadaddr - $fdtaddr"
609 
610 #define CONFIG_RAMBOOTCOMMAND \
611  "setenv bootargs root=/dev/ram rw "				\
612 	"console=$consoledev,$baudrate $othbootargs;"		\
613  "tftp $ramdiskaddr $ramdiskfile;"				\
614  "tftp $loadaddr $bootfile;"					\
615  "tftp $fdtaddr $fdtfile;"					\
616  "bootm $loadaddr $ramdiskaddr $fdtaddr"
617 
618 #define CONFIG_BOOTCOMMAND		\
619  "setenv bootargs root=/dev/$bdev rw "	\
620 	"console=$consoledev,$baudrate $othbootargs;"	\
621  "tftp $loadaddr $bootfile;"		\
622  "tftp $fdtaddr $fdtfile;"		\
623  "bootm $loadaddr - $fdtaddr"
624 
625 #endif	/* __CONFIG_H */
626