1 /* 2 * Copyright 2007-2008,2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8572ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #include "../board/freescale/common/ics307_clk.h" 31 32 #ifdef CONFIG_MK_36BIT 33 #define CONFIG_PHYS_64BIT 34 #endif 35 36 /* High Level Configuration Options */ 37 #define CONFIG_BOOKE 1 /* BOOKE */ 38 #define CONFIG_E500 1 /* BOOKE e500 family */ 39 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 40 #define CONFIG_MPC8572 1 41 #define CONFIG_MPC8572DS 1 42 #define CONFIG_MP 1 /* support multiple processors */ 43 44 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 45 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 46 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 47 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 48 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 49 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 50 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 51 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 52 53 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 54 55 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 56 #define CONFIG_ENV_OVERWRITE 57 58 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 59 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 60 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 61 62 /* 63 * These can be toggled for performance analysis, otherwise use default. 64 */ 65 #define CONFIG_L2_CACHE /* toggle L2 cache */ 66 #define CONFIG_BTB /* toggle branch predition */ 67 68 #define CONFIG_ENABLE_36BIT_PHYS 1 69 70 #ifdef CONFIG_PHYS_64BIT 71 #define CONFIG_ADDR_MAP 1 72 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 73 #endif 74 75 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 76 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 77 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 78 79 /* 80 * Base addresses -- Note these are effective addresses where the 81 * actual resources get mapped (not physical addresses) 82 */ 83 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 84 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 85 #ifdef CONFIG_PHYS_64BIT 86 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 87 #else 88 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 89 #endif 90 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 91 92 /* DDR Setup */ 93 #define CONFIG_VERY_BIG_RAM 94 #define CONFIG_FSL_DDR2 95 #undef CONFIG_FSL_DDR_INTERACTIVE 96 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 97 #define CONFIG_DDR_SPD 98 #undef CONFIG_DDR_DLL 99 100 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 101 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 102 103 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 104 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 105 106 #define CONFIG_NUM_DDR_CONTROLLERS 2 107 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 108 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 109 110 /* I2C addresses of SPD EEPROMs */ 111 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 112 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 113 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 114 115 /* These are used when DDR doesn't use SPD. */ 116 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 118 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 119 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 120 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 121 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 122 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 123 #define CONFIG_SYS_DDR_MODE_1 0x00440462 124 #define CONFIG_SYS_DDR_MODE_2 0x00000000 125 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 126 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 127 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 128 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 129 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 130 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 131 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 132 133 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 134 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 135 #define CONFIG_SYS_DDR_SBE 0x00010000 136 137 /* 138 * Make sure required options are set 139 */ 140 #ifndef CONFIG_SPD_EEPROM 141 #error ("CONFIG_SPD_EEPROM is required") 142 #endif 143 144 #undef CONFIG_CLOCKS_IN_MHZ 145 146 /* 147 * Memory map 148 * 149 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 150 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 151 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 152 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 153 * 154 * Localbus cacheable (TBD) 155 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 156 * 157 * Localbus non-cacheable 158 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 159 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 160 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 161 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 162 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 163 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 164 */ 165 166 /* 167 * Local Bus Definitions 168 */ 169 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 170 #ifdef CONFIG_PHYS_64BIT 171 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 172 #else 173 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 174 #endif 175 176 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 177 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 178 179 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 180 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 181 182 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 183 #define CONFIG_SYS_FLASH_QUIET_TEST 184 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 185 186 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 187 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 188 #undef CONFIG_SYS_FLASH_CHECKSUM 189 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 190 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 191 192 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 193 194 #define CONFIG_FLASH_CFI_DRIVER 195 #define CONFIG_SYS_FLASH_CFI 196 #define CONFIG_SYS_FLASH_EMPTY_INFO 197 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 198 199 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 200 201 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 202 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 203 #ifdef CONFIG_PHYS_64BIT 204 #define PIXIS_BASE_PHYS 0xfffdf0000ull 205 #else 206 #define PIXIS_BASE_PHYS PIXIS_BASE 207 #endif 208 209 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 210 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 211 212 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 213 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 214 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 215 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 216 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 217 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 218 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 219 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 220 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 221 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 222 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 223 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 224 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 225 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 226 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 227 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 228 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 229 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 230 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 231 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 232 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 233 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 234 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 235 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 236 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 237 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 238 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 239 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 240 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 241 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 242 #define PIXIS_LED 0x25 /* LED Register */ 243 244 /* old pixis referenced names */ 245 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 246 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 247 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 248 #define PIXIS_VSPEED2_TSEC1SER 0x8 249 #define PIXIS_VSPEED2_TSEC2SER 0x4 250 #define PIXIS_VSPEED2_TSEC3SER 0x2 251 #define PIXIS_VSPEED2_TSEC4SER 0x1 252 #define PIXIS_VCFGEN1_TSEC1SER 0x20 253 #define PIXIS_VCFGEN1_TSEC2SER 0x20 254 #define PIXIS_VCFGEN1_TSEC3SER 0x20 255 #define PIXIS_VCFGEN1_TSEC4SER 0x20 256 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 257 | PIXIS_VSPEED2_TSEC2SER \ 258 | PIXIS_VSPEED2_TSEC3SER \ 259 | PIXIS_VSPEED2_TSEC4SER) 260 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 261 | PIXIS_VCFGEN1_TSEC2SER \ 262 | PIXIS_VCFGEN1_TSEC3SER \ 263 | PIXIS_VCFGEN1_TSEC4SER) 264 265 #define CONFIG_SYS_INIT_RAM_LOCK 1 266 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 267 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 268 269 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 270 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 271 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 272 273 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 274 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 275 276 #define CONFIG_SYS_NAND_BASE 0xffa00000 277 #ifdef CONFIG_PHYS_64BIT 278 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 279 #else 280 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 281 #endif 282 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 283 CONFIG_SYS_NAND_BASE + 0x40000, \ 284 CONFIG_SYS_NAND_BASE + 0x80000,\ 285 CONFIG_SYS_NAND_BASE + 0xC0000} 286 #define CONFIG_SYS_MAX_NAND_DEVICE 4 287 #define CONFIG_MTD_NAND_VERIFY_WRITE 288 #define CONFIG_CMD_NAND 1 289 #define CONFIG_NAND_FSL_ELBC 1 290 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 291 292 /* NAND flash config */ 293 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 294 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 295 | BR_PS_8 /* Port Size = 8 bit */ \ 296 | BR_MS_FCM /* MSEL = FCM */ \ 297 | BR_V) /* valid */ 298 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 299 | OR_FCM_PGS /* Large Page*/ \ 300 | OR_FCM_CSCT \ 301 | OR_FCM_CST \ 302 | OR_FCM_CHT \ 303 | OR_FCM_SCY_1 \ 304 | OR_FCM_TRLX \ 305 | OR_FCM_EHTR) 306 307 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 308 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 309 310 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 311 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 312 | BR_PS_8 /* Port Size = 8 bit */ \ 313 | BR_MS_FCM /* MSEL = FCM */ \ 314 | BR_V) /* valid */ 315 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 316 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 317 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 318 | BR_PS_8 /* Port Size = 8 bit */ \ 319 | BR_MS_FCM /* MSEL = FCM */ \ 320 | BR_V) /* valid */ 321 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 322 323 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 324 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 325 | BR_PS_8 /* Port Size = 8 bit */ \ 326 | BR_MS_FCM /* MSEL = FCM */ \ 327 | BR_V) /* valid */ 328 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 329 330 331 /* Serial Port - controlled on board with jumper J8 332 * open - index 2 333 * shorted - index 1 334 */ 335 #define CONFIG_CONS_INDEX 1 336 #undef CONFIG_SERIAL_SOFTWARE_FIFO 337 #define CONFIG_SYS_NS16550 338 #define CONFIG_SYS_NS16550_SERIAL 339 #define CONFIG_SYS_NS16550_REG_SIZE 1 340 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 341 342 #define CONFIG_SYS_BAUDRATE_TABLE \ 343 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 344 345 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 346 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 347 348 /* Use the HUSH parser */ 349 #define CONFIG_SYS_HUSH_PARSER 350 #ifdef CONFIG_SYS_HUSH_PARSER 351 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 352 #endif 353 354 /* 355 * Pass open firmware flat tree 356 */ 357 #define CONFIG_OF_LIBFDT 1 358 #define CONFIG_OF_BOARD_SETUP 1 359 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 360 361 /* new uImage format support */ 362 #define CONFIG_FIT 1 363 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 364 365 /* I2C */ 366 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 367 #define CONFIG_HARD_I2C /* I2C with hardware support */ 368 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 369 #define CONFIG_I2C_MULTI_BUS 370 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 371 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 372 #define CONFIG_SYS_I2C_SLAVE 0x7F 373 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 374 #define CONFIG_SYS_I2C_OFFSET 0x3000 375 #define CONFIG_SYS_I2C2_OFFSET 0x3100 376 377 /* 378 * I2C2 EEPROM 379 */ 380 #define CONFIG_ID_EEPROM 381 #ifdef CONFIG_ID_EEPROM 382 #define CONFIG_SYS_I2C_EEPROM_NXID 383 #endif 384 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 385 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 386 #define CONFIG_SYS_EEPROM_BUS_NUM 1 387 388 /* 389 * General PCI 390 * Memory space is mapped 1-1, but I/O space must start from 0. 391 */ 392 393 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 394 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 395 #ifdef CONFIG_PHYS_64BIT 396 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 397 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 398 #else 399 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 400 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 401 #endif 402 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 403 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 404 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 405 #ifdef CONFIG_PHYS_64BIT 406 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 407 #else 408 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 409 #endif 410 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 411 412 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 413 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 414 #ifdef CONFIG_PHYS_64BIT 415 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 416 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 417 #else 418 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 419 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 420 #endif 421 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 422 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 423 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 426 #else 427 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 428 #endif 429 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 430 431 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 432 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 433 #ifdef CONFIG_PHYS_64BIT 434 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 435 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 436 #else 437 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 438 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 439 #endif 440 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 441 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 442 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 443 #ifdef CONFIG_PHYS_64BIT 444 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 445 #else 446 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 447 #endif 448 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 449 450 #if defined(CONFIG_PCI) 451 452 /*PCIE video card used*/ 453 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 454 455 /* video */ 456 #define CONFIG_VIDEO 457 458 #if defined(CONFIG_VIDEO) 459 #define CONFIG_BIOSEMU 460 #define CONFIG_CFB_CONSOLE 461 #define CONFIG_VIDEO_SW_CURSOR 462 #define CONFIG_VGA_AS_SINGLE_DEVICE 463 #define CONFIG_ATI_RADEON_FB 464 #define CONFIG_VIDEO_LOGO 465 /*#define CONFIG_CONSOLE_CURSOR*/ 466 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 467 #endif 468 469 #define CONFIG_NET_MULTI 470 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 471 472 #undef CONFIG_EEPRO100 473 #undef CONFIG_TULIP 474 #undef CONFIG_RTL8139 475 476 #ifndef CONFIG_PCI_PNP 477 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 478 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 479 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 480 #endif 481 482 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 483 #define CONFIG_DOS_PARTITION 484 #define CONFIG_SCSI_AHCI 485 486 #ifdef CONFIG_SCSI_AHCI 487 #define CONFIG_SATA_ULI5288 488 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 489 #define CONFIG_SYS_SCSI_MAX_LUN 1 490 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 491 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 492 #endif /* SCSI */ 493 494 #endif /* CONFIG_PCI */ 495 496 497 #if defined(CONFIG_TSEC_ENET) 498 499 #ifndef CONFIG_NET_MULTI 500 #define CONFIG_NET_MULTI 1 501 #endif 502 503 #define CONFIG_MII 1 /* MII PHY management */ 504 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 505 #define CONFIG_TSEC1 1 506 #define CONFIG_TSEC1_NAME "eTSEC1" 507 #define CONFIG_TSEC2 1 508 #define CONFIG_TSEC2_NAME "eTSEC2" 509 #define CONFIG_TSEC3 1 510 #define CONFIG_TSEC3_NAME "eTSEC3" 511 #define CONFIG_TSEC4 1 512 #define CONFIG_TSEC4_NAME "eTSEC4" 513 514 #define CONFIG_PIXIS_SGMII_CMD 515 #define CONFIG_FSL_SGMII_RISER 1 516 #define SGMII_RISER_PHY_OFFSET 0x1c 517 518 #ifdef CONFIG_FSL_SGMII_RISER 519 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 520 #endif 521 522 #define TSEC1_PHY_ADDR 0 523 #define TSEC2_PHY_ADDR 1 524 #define TSEC3_PHY_ADDR 2 525 #define TSEC4_PHY_ADDR 3 526 527 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 528 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 529 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 530 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 531 532 #define TSEC1_PHYIDX 0 533 #define TSEC2_PHYIDX 0 534 #define TSEC3_PHYIDX 0 535 #define TSEC4_PHYIDX 0 536 537 #define CONFIG_ETHPRIME "eTSEC1" 538 539 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 540 #endif /* CONFIG_TSEC_ENET */ 541 542 /* 543 * Environment 544 */ 545 #define CONFIG_ENV_IS_IN_FLASH 1 546 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 547 #define CONFIG_ENV_ADDR 0xfff80000 548 #else 549 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 550 #endif 551 #define CONFIG_ENV_SIZE 0x2000 552 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 553 554 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 555 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 556 557 /* 558 * Command line configuration. 559 */ 560 #include <config_cmd_default.h> 561 562 #define CONFIG_CMD_IRQ 563 #define CONFIG_CMD_PING 564 #define CONFIG_CMD_I2C 565 #define CONFIG_CMD_MII 566 #define CONFIG_CMD_ELF 567 #define CONFIG_CMD_IRQ 568 #define CONFIG_CMD_SETEXPR 569 #define CONFIG_CMD_REGINFO 570 571 #if defined(CONFIG_PCI) 572 #define CONFIG_CMD_PCI 573 #define CONFIG_CMD_NET 574 #define CONFIG_CMD_SCSI 575 #define CONFIG_CMD_EXT2 576 #endif 577 578 #undef CONFIG_WATCHDOG /* watchdog disabled */ 579 580 /* 581 * Miscellaneous configurable options 582 */ 583 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 584 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 585 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 586 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 587 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 588 #if defined(CONFIG_CMD_KGDB) 589 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 590 #else 591 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 592 #endif 593 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 594 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 595 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 596 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 597 598 /* 599 * For booting Linux, the board info and command line data 600 * have to be in the first 16 MB of memory, since this is 601 * the maximum mapped by the Linux kernel during initialization. 602 */ 603 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 604 605 /* 606 * Internal Definitions 607 * 608 * Boot Flags 609 */ 610 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 611 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 612 613 #if defined(CONFIG_CMD_KGDB) 614 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 615 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 616 #endif 617 618 /* 619 * Environment Configuration 620 */ 621 622 /* The mac addresses for all ethernet interface */ 623 #if defined(CONFIG_TSEC_ENET) 624 #define CONFIG_HAS_ETH0 625 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 626 #define CONFIG_HAS_ETH1 627 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 628 #define CONFIG_HAS_ETH2 629 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 630 #define CONFIG_HAS_ETH3 631 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 632 #endif 633 634 #define CONFIG_IPADDR 192.168.1.254 635 636 #define CONFIG_HOSTNAME unknown 637 #define CONFIG_ROOTPATH /opt/nfsroot 638 #define CONFIG_BOOTFILE uImage 639 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 640 641 #define CONFIG_SERVERIP 192.168.1.1 642 #define CONFIG_GATEWAYIP 192.168.1.1 643 #define CONFIG_NETMASK 255.255.255.0 644 645 /* default location for tftp and bootm */ 646 #define CONFIG_LOADADDR 1000000 647 648 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 649 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 650 651 #define CONFIG_BAUDRATE 115200 652 653 #define CONFIG_EXTRA_ENV_SETTINGS \ 654 "memctl_intlv_ctl=2\0" \ 655 "netdev=eth0\0" \ 656 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 657 "tftpflash=tftpboot $loadaddr $uboot; " \ 658 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 659 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 660 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 661 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 662 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 663 "consoledev=ttyS0\0" \ 664 "ramdiskaddr=2000000\0" \ 665 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 666 "fdtaddr=c00000\0" \ 667 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 668 "bdev=sda3\0" 669 670 #define CONFIG_HDBOOT \ 671 "setenv bootargs root=/dev/$bdev rw " \ 672 "console=$consoledev,$baudrate $othbootargs;" \ 673 "tftp $loadaddr $bootfile;" \ 674 "tftp $fdtaddr $fdtfile;" \ 675 "bootm $loadaddr - $fdtaddr" 676 677 #define CONFIG_NFSBOOTCOMMAND \ 678 "setenv bootargs root=/dev/nfs rw " \ 679 "nfsroot=$serverip:$rootpath " \ 680 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 681 "console=$consoledev,$baudrate $othbootargs;" \ 682 "tftp $loadaddr $bootfile;" \ 683 "tftp $fdtaddr $fdtfile;" \ 684 "bootm $loadaddr - $fdtaddr" 685 686 #define CONFIG_RAMBOOTCOMMAND \ 687 "setenv bootargs root=/dev/ram rw " \ 688 "console=$consoledev,$baudrate $othbootargs;" \ 689 "tftp $ramdiskaddr $ramdiskfile;" \ 690 "tftp $loadaddr $bootfile;" \ 691 "tftp $fdtaddr $fdtfile;" \ 692 "bootm $loadaddr $ramdiskaddr $fdtaddr" 693 694 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 695 696 #endif /* __CONFIG_H */ 697