1 /* 2 * Copyright 2007-2008 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8572ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34 #define CONFIG_MPC8572 1 35 #define CONFIG_MPC8572DS 1 36 #define CONFIG_MP 1 /* support multiple processors */ 37 38 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 39 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 40 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 41 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 42 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 43 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 44 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 45 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 46 47 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 48 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 52 /* 53 * When initializing flash, if we cannot find the manufacturer ID, 54 * assume this is the AMD flash associated with the CDS board. 55 * This allows booting from a promjet. 56 */ 57 #define CONFIG_ASSUME_AMD_FLASH 58 59 #ifndef __ASSEMBLY__ 60 extern unsigned long get_board_sys_clk(unsigned long dummy); 61 extern unsigned long get_board_ddr_clk(unsigned long dummy); 62 #endif 63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 64 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 65 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 66 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 67 from ICS307 instead of switches */ 68 69 /* 70 * These can be toggled for performance analysis, otherwise use default. 71 */ 72 #define CONFIG_L2_CACHE /* toggle L2 cache */ 73 #define CONFIG_BTB /* toggle branch predition */ 74 75 #define CONFIG_ENABLE_36BIT_PHYS 1 76 77 #ifdef CONFIG_PHYS_64BIT 78 #define CONFIG_ADDR_MAP 1 79 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 80 #endif 81 82 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 83 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 84 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 85 86 /* 87 * Base addresses -- Note these are effective addresses where the 88 * actual resources get mapped (not physical addresses) 89 */ 90 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 91 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 92 #ifdef CONFIG_PHYS_64BIT 93 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 94 #else 95 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 96 #endif 97 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 98 99 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 100 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 101 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 102 103 /* DDR Setup */ 104 #define CONFIG_SYS_DDR_TLB_START 9 105 #define CONFIG_VERY_BIG_RAM 106 #define CONFIG_FSL_DDR2 107 #undef CONFIG_FSL_DDR_INTERACTIVE 108 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 109 #define CONFIG_DDR_SPD 110 #undef CONFIG_DDR_DLL 111 112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 113 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 114 115 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 116 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 117 118 #define CONFIG_NUM_DDR_CONTROLLERS 2 119 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 120 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 121 122 /* I2C addresses of SPD EEPROMs */ 123 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 124 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 125 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 126 127 /* These are used when DDR doesn't use SPD. */ 128 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 129 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 130 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 131 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 132 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 133 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 134 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 135 #define CONFIG_SYS_DDR_MODE_1 0x00440462 136 #define CONFIG_SYS_DDR_MODE_2 0x00000000 137 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 138 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 139 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 140 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 141 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 142 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 143 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 144 145 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 146 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 147 #define CONFIG_SYS_DDR_SBE 0x00010000 148 149 /* 150 * Make sure required options are set 151 */ 152 #ifndef CONFIG_SPD_EEPROM 153 #error ("CONFIG_SPD_EEPROM is required") 154 #endif 155 156 #undef CONFIG_CLOCKS_IN_MHZ 157 158 /* 159 * Memory map 160 * 161 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 162 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 163 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 164 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 165 * 166 * Localbus cacheable (TBD) 167 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 168 * 169 * Localbus non-cacheable 170 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 171 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 172 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 173 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 174 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 175 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 176 */ 177 178 /* 179 * Local Bus Definitions 180 */ 181 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 182 #ifdef CONFIG_PHYS_64BIT 183 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 184 #else 185 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 186 #endif 187 188 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 189 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 190 191 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 192 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 193 194 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 195 #define CONFIG_SYS_FLASH_QUIET_TEST 196 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 197 198 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 199 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 200 #undef CONFIG_SYS_FLASH_CHECKSUM 201 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 202 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 203 204 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 205 206 #define CONFIG_FLASH_CFI_DRIVER 207 #define CONFIG_SYS_FLASH_CFI 208 #define CONFIG_SYS_FLASH_EMPTY_INFO 209 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 210 211 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 212 213 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 214 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 215 #ifdef CONFIG_PHYS_64BIT 216 #define PIXIS_BASE_PHYS 0xfffdf0000ull 217 #else 218 #define PIXIS_BASE_PHYS PIXIS_BASE 219 #endif 220 221 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 222 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 223 224 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 225 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 226 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 227 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 228 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 229 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 230 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 231 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 232 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 233 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 234 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 235 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 236 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 237 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 238 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 239 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 240 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 241 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 242 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 243 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 244 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 245 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 246 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 247 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 248 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 249 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 250 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 251 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 252 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 253 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 254 #define PIXIS_LED 0x25 /* LED Register */ 255 256 /* old pixis referenced names */ 257 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 258 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 259 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 260 #define PIXIS_VSPEED2_TSEC1SER 0x8 261 #define PIXIS_VSPEED2_TSEC2SER 0x4 262 #define PIXIS_VSPEED2_TSEC3SER 0x2 263 #define PIXIS_VSPEED2_TSEC4SER 0x1 264 #define PIXIS_VCFGEN1_TSEC1SER 0x20 265 #define PIXIS_VCFGEN1_TSEC2SER 0x20 266 #define PIXIS_VCFGEN1_TSEC3SER 0x20 267 #define PIXIS_VCFGEN1_TSEC4SER 0x20 268 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 269 | PIXIS_VSPEED2_TSEC2SER \ 270 | PIXIS_VSPEED2_TSEC3SER \ 271 | PIXIS_VSPEED2_TSEC4SER) 272 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 273 | PIXIS_VCFGEN1_TSEC2SER \ 274 | PIXIS_VCFGEN1_TSEC3SER \ 275 | PIXIS_VCFGEN1_TSEC4SER) 276 277 #define CONFIG_SYS_INIT_RAM_LOCK 1 278 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 279 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 280 281 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 282 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 283 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 284 285 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 286 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 287 288 #define CONFIG_SYS_NAND_BASE 0xffa00000 289 #ifdef CONFIG_PHYS_64BIT 290 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 291 #else 292 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 293 #endif 294 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 295 CONFIG_SYS_NAND_BASE + 0x40000, \ 296 CONFIG_SYS_NAND_BASE + 0x80000,\ 297 CONFIG_SYS_NAND_BASE + 0xC0000} 298 #define CONFIG_SYS_MAX_NAND_DEVICE 4 299 #define CONFIG_MTD_NAND_VERIFY_WRITE 300 #define CONFIG_CMD_NAND 1 301 #define CONFIG_NAND_FSL_ELBC 1 302 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 303 304 /* NAND flash config */ 305 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 306 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 307 | BR_PS_8 /* Port Size = 8 bit */ \ 308 | BR_MS_FCM /* MSEL = FCM */ \ 309 | BR_V) /* valid */ 310 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 311 | OR_FCM_PGS /* Large Page*/ \ 312 | OR_FCM_CSCT \ 313 | OR_FCM_CST \ 314 | OR_FCM_CHT \ 315 | OR_FCM_SCY_1 \ 316 | OR_FCM_TRLX \ 317 | OR_FCM_EHTR) 318 319 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 320 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 321 322 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 323 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 324 | BR_PS_8 /* Port Size = 8 bit */ \ 325 | BR_MS_FCM /* MSEL = FCM */ \ 326 | BR_V) /* valid */ 327 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 328 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 329 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 330 | BR_PS_8 /* Port Size = 8 bit */ \ 331 | BR_MS_FCM /* MSEL = FCM */ \ 332 | BR_V) /* valid */ 333 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 334 335 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 336 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 337 | BR_PS_8 /* Port Size = 8 bit */ \ 338 | BR_MS_FCM /* MSEL = FCM */ \ 339 | BR_V) /* valid */ 340 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 341 342 343 /* Serial Port - controlled on board with jumper J8 344 * open - index 2 345 * shorted - index 1 346 */ 347 #define CONFIG_CONS_INDEX 1 348 #undef CONFIG_SERIAL_SOFTWARE_FIFO 349 #define CONFIG_SYS_NS16550 350 #define CONFIG_SYS_NS16550_SERIAL 351 #define CONFIG_SYS_NS16550_REG_SIZE 1 352 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 353 354 #define CONFIG_SYS_BAUDRATE_TABLE \ 355 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 356 357 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 358 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 359 360 /* Use the HUSH parser */ 361 #define CONFIG_SYS_HUSH_PARSER 362 #ifdef CONFIG_SYS_HUSH_PARSER 363 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 364 #endif 365 366 /* 367 * Pass open firmware flat tree 368 */ 369 #define CONFIG_OF_LIBFDT 1 370 #define CONFIG_OF_BOARD_SETUP 1 371 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 372 373 #define CONFIG_SYS_64BIT_VSPRINTF 1 374 #define CONFIG_SYS_64BIT_STRTOUL 1 375 376 /* new uImage format support */ 377 #define CONFIG_FIT 1 378 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 379 380 /* I2C */ 381 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 382 #define CONFIG_HARD_I2C /* I2C with hardware support */ 383 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 384 #define CONFIG_I2C_MULTI_BUS 385 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 386 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 387 #define CONFIG_SYS_I2C_SLAVE 0x7F 388 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 389 #define CONFIG_SYS_I2C_OFFSET 0x3000 390 #define CONFIG_SYS_I2C2_OFFSET 0x3100 391 392 /* 393 * I2C2 EEPROM 394 */ 395 #define CONFIG_ID_EEPROM 396 #ifdef CONFIG_ID_EEPROM 397 #define CONFIG_SYS_I2C_EEPROM_NXID 398 #endif 399 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 400 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 401 #define CONFIG_SYS_EEPROM_BUS_NUM 1 402 403 /* 404 * General PCI 405 * Memory space is mapped 1-1, but I/O space must start from 0. 406 */ 407 408 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 409 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 410 #ifdef CONFIG_PHYS_64BIT 411 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 412 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 413 #else 414 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 415 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 416 #endif 417 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 418 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 419 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 420 #ifdef CONFIG_PHYS_64BIT 421 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 422 #else 423 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 424 #endif 425 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 426 427 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 428 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 429 #ifdef CONFIG_PHYS_64BIT 430 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 431 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 432 #else 433 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 434 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 435 #endif 436 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 437 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 438 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 439 #ifdef CONFIG_PHYS_64BIT 440 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 441 #else 442 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 443 #endif 444 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 445 446 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 447 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 448 #ifdef CONFIG_PHYS_64BIT 449 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 450 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 451 #else 452 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 453 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 454 #endif 455 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 456 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 457 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 458 #ifdef CONFIG_PHYS_64BIT 459 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 460 #else 461 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 462 #endif 463 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 464 465 #if defined(CONFIG_PCI) 466 467 /*PCIE video card used*/ 468 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 469 470 /* video */ 471 #define CONFIG_VIDEO 472 473 #if defined(CONFIG_VIDEO) 474 #define CONFIG_BIOSEMU 475 #define CONFIG_CFB_CONSOLE 476 #define CONFIG_VIDEO_SW_CURSOR 477 #define CONFIG_VGA_AS_SINGLE_DEVICE 478 #define CONFIG_ATI_RADEON_FB 479 #define CONFIG_VIDEO_LOGO 480 /*#define CONFIG_CONSOLE_CURSOR*/ 481 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 482 #endif 483 484 #define CONFIG_NET_MULTI 485 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 486 487 #undef CONFIG_EEPRO100 488 #undef CONFIG_TULIP 489 #undef CONFIG_RTL8139 490 491 #ifndef CONFIG_PCI_PNP 492 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 493 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 494 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 495 #endif 496 497 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 498 #define CONFIG_DOS_PARTITION 499 #define CONFIG_SCSI_AHCI 500 501 #ifdef CONFIG_SCSI_AHCI 502 #define CONFIG_SATA_ULI5288 503 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 504 #define CONFIG_SYS_SCSI_MAX_LUN 1 505 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 506 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 507 #endif /* SCSI */ 508 509 #endif /* CONFIG_PCI */ 510 511 512 #if defined(CONFIG_TSEC_ENET) 513 514 #ifndef CONFIG_NET_MULTI 515 #define CONFIG_NET_MULTI 1 516 #endif 517 518 #define CONFIG_MII 1 /* MII PHY management */ 519 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 520 #define CONFIG_TSEC1 1 521 #define CONFIG_TSEC1_NAME "eTSEC1" 522 #define CONFIG_TSEC2 1 523 #define CONFIG_TSEC2_NAME "eTSEC2" 524 #define CONFIG_TSEC3 1 525 #define CONFIG_TSEC3_NAME "eTSEC3" 526 #define CONFIG_TSEC4 1 527 #define CONFIG_TSEC4_NAME "eTSEC4" 528 529 #define CONFIG_PIXIS_SGMII_CMD 530 #define CONFIG_FSL_SGMII_RISER 1 531 #define SGMII_RISER_PHY_OFFSET 0x1c 532 533 #ifdef CONFIG_FSL_SGMII_RISER 534 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 535 #endif 536 537 #define TSEC1_PHY_ADDR 0 538 #define TSEC2_PHY_ADDR 1 539 #define TSEC3_PHY_ADDR 2 540 #define TSEC4_PHY_ADDR 3 541 542 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 543 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 544 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 545 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 546 547 #define TSEC1_PHYIDX 0 548 #define TSEC2_PHYIDX 0 549 #define TSEC3_PHYIDX 0 550 #define TSEC4_PHYIDX 0 551 552 #define CONFIG_ETHPRIME "eTSEC1" 553 554 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 555 #endif /* CONFIG_TSEC_ENET */ 556 557 /* 558 * Environment 559 */ 560 #define CONFIG_ENV_IS_IN_FLASH 1 561 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 562 #define CONFIG_ENV_ADDR 0xfff80000 563 #else 564 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 565 #endif 566 #define CONFIG_ENV_SIZE 0x2000 567 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 568 569 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 570 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 571 572 /* 573 * Command line configuration. 574 */ 575 #include <config_cmd_default.h> 576 577 #define CONFIG_CMD_IRQ 578 #define CONFIG_CMD_PING 579 #define CONFIG_CMD_I2C 580 #define CONFIG_CMD_MII 581 #define CONFIG_CMD_ELF 582 #define CONFIG_CMD_IRQ 583 #define CONFIG_CMD_SETEXPR 584 585 #if defined(CONFIG_PCI) 586 #define CONFIG_CMD_PCI 587 #define CONFIG_CMD_NET 588 #define CONFIG_CMD_SCSI 589 #define CONFIG_CMD_EXT2 590 #endif 591 592 #undef CONFIG_WATCHDOG /* watchdog disabled */ 593 594 /* 595 * Miscellaneous configurable options 596 */ 597 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 598 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 599 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 600 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 601 #if defined(CONFIG_CMD_KGDB) 602 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 603 #else 604 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 605 #endif 606 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 607 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 608 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 609 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 610 611 /* 612 * For booting Linux, the board info and command line data 613 * have to be in the first 16 MB of memory, since this is 614 * the maximum mapped by the Linux kernel during initialization. 615 */ 616 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 617 618 /* 619 * Internal Definitions 620 * 621 * Boot Flags 622 */ 623 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 624 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 625 626 #if defined(CONFIG_CMD_KGDB) 627 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 628 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 629 #endif 630 631 /* 632 * Environment Configuration 633 */ 634 635 /* The mac addresses for all ethernet interface */ 636 #if defined(CONFIG_TSEC_ENET) 637 #define CONFIG_HAS_ETH0 638 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 639 #define CONFIG_HAS_ETH1 640 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 641 #define CONFIG_HAS_ETH2 642 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 643 #define CONFIG_HAS_ETH3 644 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 645 #endif 646 647 #define CONFIG_IPADDR 192.168.1.254 648 649 #define CONFIG_HOSTNAME unknown 650 #define CONFIG_ROOTPATH /opt/nfsroot 651 #define CONFIG_BOOTFILE uImage 652 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 653 654 #define CONFIG_SERVERIP 192.168.1.1 655 #define CONFIG_GATEWAYIP 192.168.1.1 656 #define CONFIG_NETMASK 255.255.255.0 657 658 /* default location for tftp and bootm */ 659 #define CONFIG_LOADADDR 1000000 660 661 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 662 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 663 664 #define CONFIG_BAUDRATE 115200 665 666 #define CONFIG_EXTRA_ENV_SETTINGS \ 667 "memctl_intlv_ctl=2\0" \ 668 "netdev=eth0\0" \ 669 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 670 "tftpflash=tftpboot $loadaddr $uboot; " \ 671 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 672 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 673 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 674 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 675 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 676 "consoledev=ttyS0\0" \ 677 "ramdiskaddr=2000000\0" \ 678 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 679 "fdtaddr=c00000\0" \ 680 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 681 "bdev=sda3\0" 682 683 #define CONFIG_HDBOOT \ 684 "setenv bootargs root=/dev/$bdev rw " \ 685 "console=$consoledev,$baudrate $othbootargs;" \ 686 "tftp $loadaddr $bootfile;" \ 687 "tftp $fdtaddr $fdtfile;" \ 688 "bootm $loadaddr - $fdtaddr" 689 690 #define CONFIG_NFSBOOTCOMMAND \ 691 "setenv bootargs root=/dev/nfs rw " \ 692 "nfsroot=$serverip:$rootpath " \ 693 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 694 "console=$consoledev,$baudrate $othbootargs;" \ 695 "tftp $loadaddr $bootfile;" \ 696 "tftp $fdtaddr $fdtfile;" \ 697 "bootm $loadaddr - $fdtaddr" 698 699 #define CONFIG_RAMBOOTCOMMAND \ 700 "setenv bootargs root=/dev/ram rw " \ 701 "console=$consoledev,$baudrate $othbootargs;" \ 702 "tftp $ramdiskaddr $ramdiskfile;" \ 703 "tftp $loadaddr $bootfile;" \ 704 "tftp $fdtaddr $fdtfile;" \ 705 "bootm $loadaddr $ramdiskaddr $fdtaddr" 706 707 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 708 709 #endif /* __CONFIG_H */ 710