1 /* 2 * Copyright 2007-2008 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8572ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34 #define CONFIG_MPC8572 1 35 #define CONFIG_MPC8572DS 1 36 #define CONFIG_MP 1 /* support multiple processors */ 37 #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 38 39 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 40 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 41 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 42 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 43 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 44 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 45 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 46 47 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 48 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 52 /* 53 * When initializing flash, if we cannot find the manufacturer ID, 54 * assume this is the AMD flash associated with the CDS board. 55 * This allows booting from a promjet. 56 */ 57 #define CONFIG_ASSUME_AMD_FLASH 58 59 #ifndef __ASSEMBLY__ 60 extern unsigned long get_board_sys_clk(unsigned long dummy); 61 extern unsigned long get_board_ddr_clk(unsigned long dummy); 62 #endif 63 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 64 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 65 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 66 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 67 from ICS307 instead of switches */ 68 69 /* 70 * These can be toggled for performance analysis, otherwise use default. 71 */ 72 #define CONFIG_L2_CACHE /* toggle L2 cache */ 73 #define CONFIG_BTB /* toggle branch predition */ 74 75 #define CONFIG_ENABLE_36BIT_PHYS 1 76 77 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 78 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 79 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 80 81 /* 82 * Base addresses -- Note these are effective addresses where the 83 * actual resources get mapped (not physical addresses) 84 */ 85 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 86 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 87 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 88 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 89 90 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 91 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 92 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 93 94 /* DDR Setup */ 95 #define CONFIG_SYS_DDR_TLB_START 9 96 #define CONFIG_FSL_DDR2 97 #undef CONFIG_FSL_DDR_INTERACTIVE 98 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 99 #define CONFIG_DDR_SPD 100 #undef CONFIG_DDR_DLL 101 102 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 103 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 104 105 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 106 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 107 108 #define CONFIG_NUM_DDR_CONTROLLERS 2 109 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 110 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 111 112 /* I2C addresses of SPD EEPROMs */ 113 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 114 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 115 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 116 117 /* These are used when DDR doesn't use SPD. */ 118 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 119 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 120 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 121 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 122 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 123 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 124 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 125 #define CONFIG_SYS_DDR_MODE_1 0x00440462 126 #define CONFIG_SYS_DDR_MODE_2 0x00000000 127 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 128 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 129 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 130 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 131 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 132 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 133 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 134 135 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 136 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 137 #define CONFIG_SYS_DDR_SBE 0x00010000 138 139 /* 140 * Make sure required options are set 141 */ 142 #ifndef CONFIG_SPD_EEPROM 143 #error ("CONFIG_SPD_EEPROM is required") 144 #endif 145 146 #undef CONFIG_CLOCKS_IN_MHZ 147 148 /* 149 * Memory map 150 * 151 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 152 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 153 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 154 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 155 * 156 * Localbus cacheable (TBD) 157 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 158 * 159 * Localbus non-cacheable 160 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 161 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 162 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 163 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 164 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 165 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 166 */ 167 168 /* 169 * Local Bus Definitions 170 */ 171 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 172 173 #define CONFIG_SYS_BR0_PRELIM 0xe8001001 174 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 175 176 #define CONFIG_SYS_BR1_PRELIM 0xe0001001 177 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 178 179 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} 180 #define CONFIG_SYS_FLASH_QUIET_TEST 181 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 182 183 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 184 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 185 #undef CONFIG_SYS_FLASH_CHECKSUM 186 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 187 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 188 189 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 190 191 #define CONFIG_FLASH_CFI_DRIVER 192 #define CONFIG_SYS_FLASH_CFI 193 #define CONFIG_SYS_FLASH_EMPTY_INFO 194 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 195 196 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 197 198 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 199 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 200 201 #define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ 202 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 203 204 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 205 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 206 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 207 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 208 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 209 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 210 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 211 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 212 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 213 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 214 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 215 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 216 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 217 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 218 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 219 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 220 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 221 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 222 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 223 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 224 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 225 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 226 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 227 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 228 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 229 #define PIXIS_LED 0x25 /* LED Register */ 230 231 /* old pixis referenced names */ 232 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 233 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 234 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 235 #define PIXIS_VSPEED2_TSEC1SER 0x8 236 #define PIXIS_VSPEED2_TSEC2SER 0x4 237 #define PIXIS_VSPEED2_TSEC3SER 0x2 238 #define PIXIS_VSPEED2_TSEC4SER 0x1 239 #define PIXIS_VCFGEN1_TSEC1SER 0x20 240 #define PIXIS_VCFGEN1_TSEC2SER 0x20 241 #define PIXIS_VCFGEN1_TSEC3SER 0x20 242 #define PIXIS_VCFGEN1_TSEC4SER 0x20 243 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 244 | PIXIS_VSPEED2_TSEC2SER \ 245 | PIXIS_VSPEED2_TSEC3SER \ 246 | PIXIS_VSPEED2_TSEC4SER) 247 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 248 | PIXIS_VCFGEN1_TSEC2SER \ 249 | PIXIS_VCFGEN1_TSEC3SER \ 250 | PIXIS_VCFGEN1_TSEC4SER) 251 252 #define CONFIG_SYS_INIT_RAM_LOCK 1 253 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 254 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 255 256 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 257 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 258 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 259 260 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 261 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 262 263 #define CONFIG_SYS_NAND_BASE 0xffa00000 264 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 265 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 266 CONFIG_SYS_NAND_BASE + 0x40000, \ 267 CONFIG_SYS_NAND_BASE + 0x80000,\ 268 CONFIG_SYS_NAND_BASE + 0xC0000} 269 #define CONFIG_SYS_MAX_NAND_DEVICE 4 270 #define NAND_MAX_CHIPS 1 271 #define CONFIG_MTD_NAND_VERIFY_WRITE 272 #define CONFIG_CMD_NAND 1 273 #define CONFIG_NAND_FSL_ELBC 1 274 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 275 276 /* NAND flash config */ 277 #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 278 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 279 | BR_PS_8 /* Port Size = 8 bit */ \ 280 | BR_MS_FCM /* MSEL = FCM */ \ 281 | BR_V) /* valid */ 282 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 283 | OR_FCM_PGS /* Large Page*/ \ 284 | OR_FCM_CSCT \ 285 | OR_FCM_CST \ 286 | OR_FCM_CHT \ 287 | OR_FCM_SCY_1 \ 288 | OR_FCM_TRLX \ 289 | OR_FCM_EHTR) 290 291 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 292 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 293 294 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ 295 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 296 | BR_PS_8 /* Port Size = 8 bit */ \ 297 | BR_MS_FCM /* MSEL = FCM */ \ 298 | BR_V) /* valid */ 299 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 300 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 301 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 302 | BR_PS_8 /* Port Size = 8 bit */ \ 303 | BR_MS_FCM /* MSEL = FCM */ \ 304 | BR_V) /* valid */ 305 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 306 307 #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ 308 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 309 | BR_PS_8 /* Port Size = 8 bit */ \ 310 | BR_MS_FCM /* MSEL = FCM */ \ 311 | BR_V) /* valid */ 312 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 313 314 315 /* Serial Port - controlled on board with jumper J8 316 * open - index 2 317 * shorted - index 1 318 */ 319 #define CONFIG_CONS_INDEX 1 320 #undef CONFIG_SERIAL_SOFTWARE_FIFO 321 #define CONFIG_SYS_NS16550 322 #define CONFIG_SYS_NS16550_SERIAL 323 #define CONFIG_SYS_NS16550_REG_SIZE 1 324 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 325 326 #define CONFIG_SYS_BAUDRATE_TABLE \ 327 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 328 329 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 330 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 331 332 /* Use the HUSH parser */ 333 #define CONFIG_SYS_HUSH_PARSER 334 #ifdef CONFIG_SYS_HUSH_PARSER 335 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 336 #endif 337 338 /* 339 * Pass open firmware flat tree 340 */ 341 #define CONFIG_OF_LIBFDT 1 342 #define CONFIG_OF_BOARD_SETUP 1 343 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 344 345 #define CONFIG_SYS_64BIT_VSPRINTF 1 346 #define CONFIG_SYS_64BIT_STRTOUL 1 347 348 /* new uImage format support */ 349 #define CONFIG_FIT 1 350 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 351 352 /* I2C */ 353 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 354 #define CONFIG_HARD_I2C /* I2C with hardware support */ 355 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 356 #define CONFIG_I2C_MULTI_BUS 357 #define CONFIG_I2C_CMD_TREE 358 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 359 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 360 #define CONFIG_SYS_I2C_SLAVE 0x7F 361 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 362 #define CONFIG_SYS_I2C_OFFSET 0x3000 363 #define CONFIG_SYS_I2C2_OFFSET 0x3100 364 365 /* 366 * I2C2 EEPROM 367 */ 368 #define CONFIG_ID_EEPROM 369 #ifdef CONFIG_ID_EEPROM 370 #define CONFIG_SYS_I2C_EEPROM_NXID 371 #endif 372 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 373 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 374 #define CONFIG_SYS_EEPROM_BUS_NUM 1 375 376 /* 377 * General PCI 378 * Memory space is mapped 1-1, but I/O space must start from 0. 379 */ 380 381 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 382 #define CONFIG_SYS_PCIE3_MEM_BASE 0x80000000 383 #define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE 384 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 385 #define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 386 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 387 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 388 389 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 390 #define CONFIG_SYS_PCIE2_MEM_BASE 0xa0000000 391 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE 392 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 393 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 394 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 395 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 396 397 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 398 #define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000 399 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE 400 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 401 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 402 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 403 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 404 405 #if defined(CONFIG_PCI) 406 407 /*PCIE video card used*/ 408 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_PHYS 409 410 /* video */ 411 #define CONFIG_VIDEO 412 413 #if defined(CONFIG_VIDEO) 414 #define CONFIG_BIOSEMU 415 #define CONFIG_CFB_CONSOLE 416 #define CONFIG_VIDEO_SW_CURSOR 417 #define CONFIG_VGA_AS_SINGLE_DEVICE 418 #define CONFIG_ATI_RADEON_FB 419 #define CONFIG_VIDEO_LOGO 420 /*#define CONFIG_CONSOLE_CURSOR*/ 421 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 422 #endif 423 424 #define CONFIG_NET_MULTI 425 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 426 427 #undef CONFIG_EEPRO100 428 #undef CONFIG_TULIP 429 #undef CONFIG_RTL8139 430 431 #ifdef CONFIG_RTL8139 432 /* This macro is used by RTL8139 but not defined in PPC architecture */ 433 #define KSEG1ADDR(x) (x) 434 #define _IO_BASE 0x00000000 435 #endif 436 437 #ifndef CONFIG_PCI_PNP 438 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BASE 439 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BASE 440 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 441 #endif 442 443 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 444 #define CONFIG_DOS_PARTITION 445 #define CONFIG_SCSI_AHCI 446 447 #ifdef CONFIG_SCSI_AHCI 448 #define CONFIG_SATA_ULI5288 449 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 450 #define CONFIG_SYS_SCSI_MAX_LUN 1 451 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 452 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 453 #endif /* SCSI */ 454 455 #endif /* CONFIG_PCI */ 456 457 458 #if defined(CONFIG_TSEC_ENET) 459 460 #ifndef CONFIG_NET_MULTI 461 #define CONFIG_NET_MULTI 1 462 #endif 463 464 #define CONFIG_MII 1 /* MII PHY management */ 465 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 466 #define CONFIG_TSEC1 1 467 #define CONFIG_TSEC1_NAME "eTSEC1" 468 #define CONFIG_TSEC2 1 469 #define CONFIG_TSEC2_NAME "eTSEC2" 470 #define CONFIG_TSEC3 1 471 #define CONFIG_TSEC3_NAME "eTSEC3" 472 #define CONFIG_TSEC4 1 473 #define CONFIG_TSEC4_NAME "eTSEC4" 474 475 #define CONFIG_PIXIS_SGMII_CMD 476 #define CONFIG_FSL_SGMII_RISER 1 477 #define SGMII_RISER_PHY_OFFSET 0x1c 478 479 #ifdef CONFIG_FSL_SGMII_RISER 480 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 481 #endif 482 483 #define TSEC1_PHY_ADDR 0 484 #define TSEC2_PHY_ADDR 1 485 #define TSEC3_PHY_ADDR 2 486 #define TSEC4_PHY_ADDR 3 487 488 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 489 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 490 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 491 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 492 493 #define TSEC1_PHYIDX 0 494 #define TSEC2_PHYIDX 0 495 #define TSEC3_PHYIDX 0 496 #define TSEC4_PHYIDX 0 497 498 #define CONFIG_ETHPRIME "eTSEC1" 499 500 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 501 #endif /* CONFIG_TSEC_ENET */ 502 503 /* 504 * Environment 505 */ 506 #define CONFIG_ENV_IS_IN_FLASH 1 507 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 508 #define CONFIG_ENV_ADDR 0xfff80000 509 #else 510 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 511 #endif 512 #define CONFIG_ENV_SIZE 0x2000 513 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 514 515 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 516 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 517 518 /* 519 * Command line configuration. 520 */ 521 #include <config_cmd_default.h> 522 523 #define CONFIG_CMD_IRQ 524 #define CONFIG_CMD_PING 525 #define CONFIG_CMD_I2C 526 #define CONFIG_CMD_MII 527 #define CONFIG_CMD_ELF 528 #define CONFIG_CMD_IRQ 529 #define CONFIG_CMD_SETEXPR 530 531 #if defined(CONFIG_PCI) 532 #define CONFIG_CMD_PCI 533 #define CONFIG_CMD_BEDBUG 534 #define CONFIG_CMD_NET 535 #define CONFIG_CMD_SCSI 536 #define CONFIG_CMD_EXT2 537 #endif 538 539 #undef CONFIG_WATCHDOG /* watchdog disabled */ 540 541 /* 542 * Miscellaneous configurable options 543 */ 544 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 545 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 546 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 547 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 548 #if defined(CONFIG_CMD_KGDB) 549 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 550 #else 551 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 552 #endif 553 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 554 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 555 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 556 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 557 558 /* 559 * For booting Linux, the board info and command line data 560 * have to be in the first 8 MB of memory, since this is 561 * the maximum mapped by the Linux kernel during initialization. 562 */ 563 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 564 565 /* 566 * Internal Definitions 567 * 568 * Boot Flags 569 */ 570 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 571 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 572 573 #if defined(CONFIG_CMD_KGDB) 574 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 575 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 576 #endif 577 578 /* 579 * Environment Configuration 580 */ 581 582 /* The mac addresses for all ethernet interface */ 583 #if defined(CONFIG_TSEC_ENET) 584 #define CONFIG_HAS_ETH0 585 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 586 #define CONFIG_HAS_ETH1 587 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 588 #define CONFIG_HAS_ETH2 589 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 590 #define CONFIG_HAS_ETH3 591 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 592 #endif 593 594 #define CONFIG_IPADDR 192.168.1.254 595 596 #define CONFIG_HOSTNAME unknown 597 #define CONFIG_ROOTPATH /opt/nfsroot 598 #define CONFIG_BOOTFILE uImage 599 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 600 601 #define CONFIG_SERVERIP 192.168.1.1 602 #define CONFIG_GATEWAYIP 192.168.1.1 603 #define CONFIG_NETMASK 255.255.255.0 604 605 /* default location for tftp and bootm */ 606 #define CONFIG_LOADADDR 1000000 607 608 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 609 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 610 611 #define CONFIG_BAUDRATE 115200 612 613 #define CONFIG_EXTRA_ENV_SETTINGS \ 614 "memctl_intlv_ctl=2\0" \ 615 "netdev=eth0\0" \ 616 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 617 "tftpflash=tftpboot $loadaddr $uboot; " \ 618 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 619 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 620 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 621 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 622 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 623 "consoledev=ttyS0\0" \ 624 "ramdiskaddr=2000000\0" \ 625 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 626 "fdtaddr=c00000\0" \ 627 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 628 "bdev=sda3\0" 629 630 #define CONFIG_HDBOOT \ 631 "setenv bootargs root=/dev/$bdev rw " \ 632 "console=$consoledev,$baudrate $othbootargs;" \ 633 "tftp $loadaddr $bootfile;" \ 634 "tftp $fdtaddr $fdtfile;" \ 635 "bootm $loadaddr - $fdtaddr" 636 637 #define CONFIG_NFSBOOTCOMMAND \ 638 "setenv bootargs root=/dev/nfs rw " \ 639 "nfsroot=$serverip:$rootpath " \ 640 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 641 "console=$consoledev,$baudrate $othbootargs;" \ 642 "tftp $loadaddr $bootfile;" \ 643 "tftp $fdtaddr $fdtfile;" \ 644 "bootm $loadaddr - $fdtaddr" 645 646 #define CONFIG_RAMBOOTCOMMAND \ 647 "setenv bootargs root=/dev/ram rw " \ 648 "console=$consoledev,$baudrate $othbootargs;" \ 649 "tftp $ramdiskaddr $ramdiskfile;" \ 650 "tftp $loadaddr $bootfile;" \ 651 "tftp $fdtaddr $fdtfile;" \ 652 "bootm $loadaddr $ramdiskaddr $fdtaddr" 653 654 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 655 656 #endif /* __CONFIG_H */ 657