1 /* 2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8572ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifdef CONFIG_36BIT 17 #define CONFIG_PHYS_64BIT 18 #endif 19 20 #ifdef CONFIG_NAND 21 #define CONFIG_NAND_U_BOOT 22 #define CONFIG_RAMBOOT_NAND 23 #ifdef CONFIG_NAND_SPL 24 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 25 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 26 #else 27 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds 28 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 29 #endif /* CONFIG_NAND_SPL */ 30 #endif 31 32 #ifndef CONFIG_SYS_TEXT_BASE 33 #define CONFIG_SYS_TEXT_BASE 0xeff80000 34 #endif 35 36 #ifndef CONFIG_RESET_VECTOR_ADDRESS 37 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 38 #endif 39 40 #ifndef CONFIG_SYS_MONITOR_BASE 41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 42 #endif 43 44 /* High Level Configuration Options */ 45 #define CONFIG_BOOKE 1 /* BOOKE */ 46 #define CONFIG_E500 1 /* BOOKE e500 family */ 47 #define CONFIG_MPC8572 1 48 #define CONFIG_MPC8572DS 1 49 #define CONFIG_MP 1 /* support multiple processors */ 50 51 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 52 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 53 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 54 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 55 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 56 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 57 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 58 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 59 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 60 61 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 62 63 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 64 #define CONFIG_ENV_OVERWRITE 65 66 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 67 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 68 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 69 70 /* 71 * These can be toggled for performance analysis, otherwise use default. 72 */ 73 #define CONFIG_L2_CACHE /* toggle L2 cache */ 74 #define CONFIG_BTB /* toggle branch predition */ 75 76 #define CONFIG_ENABLE_36BIT_PHYS 1 77 78 #ifdef CONFIG_PHYS_64BIT 79 #define CONFIG_ADDR_MAP 1 80 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 81 #endif 82 83 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 84 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 85 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 86 87 /* 88 * Config the L2 Cache as L2 SRAM 89 */ 90 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 91 #ifdef CONFIG_PHYS_64BIT 92 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 93 #else 94 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 95 #endif 96 #define CONFIG_SYS_L2_SIZE (512 << 10) 97 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 98 99 #define CONFIG_SYS_CCSRBAR 0xffe00000 100 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 101 102 #if defined(CONFIG_NAND_SPL) 103 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 104 #endif 105 106 /* DDR Setup */ 107 #define CONFIG_VERY_BIG_RAM 108 #define CONFIG_SYS_FSL_DDR2 109 #undef CONFIG_FSL_DDR_INTERACTIVE 110 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 111 #define CONFIG_DDR_SPD 112 113 #define CONFIG_DDR_ECC 114 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 115 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 116 117 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 118 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 119 120 #define CONFIG_NUM_DDR_CONTROLLERS 2 121 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 122 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 123 124 /* I2C addresses of SPD EEPROMs */ 125 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 126 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 127 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 128 129 /* These are used when DDR doesn't use SPD. */ 130 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 131 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 132 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 133 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 134 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 135 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 136 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 137 #define CONFIG_SYS_DDR_MODE_1 0x00440462 138 #define CONFIG_SYS_DDR_MODE_2 0x00000000 139 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 140 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 141 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 142 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 143 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 144 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 145 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 146 147 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 148 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 149 #define CONFIG_SYS_DDR_SBE 0x00010000 150 151 /* 152 * Make sure required options are set 153 */ 154 #ifndef CONFIG_SPD_EEPROM 155 #error ("CONFIG_SPD_EEPROM is required") 156 #endif 157 158 #undef CONFIG_CLOCKS_IN_MHZ 159 160 /* 161 * Memory map 162 * 163 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 164 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 165 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 166 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 167 * 168 * Localbus cacheable (TBD) 169 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 170 * 171 * Localbus non-cacheable 172 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 173 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 174 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 175 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 176 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 177 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 178 */ 179 180 /* 181 * Local Bus Definitions 182 */ 183 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 184 #ifdef CONFIG_PHYS_64BIT 185 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 186 #else 187 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 188 #endif 189 190 191 #define CONFIG_FLASH_BR_PRELIM \ 192 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 193 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 194 195 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 196 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 197 198 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 199 #define CONFIG_SYS_FLASH_QUIET_TEST 200 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 201 202 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 203 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 204 #undef CONFIG_SYS_FLASH_CHECKSUM 205 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 206 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 207 208 #if defined(CONFIG_RAMBOOT_NAND) 209 #define CONFIG_SYS_RAMBOOT 210 #define CONFIG_SYS_EXTRA_ENV_RELOC 211 #else 212 #undef CONFIG_SYS_RAMBOOT 213 #endif 214 215 #define CONFIG_FLASH_CFI_DRIVER 216 #define CONFIG_SYS_FLASH_CFI 217 #define CONFIG_SYS_FLASH_EMPTY_INFO 218 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 219 220 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 221 222 #define CONFIG_HWCONFIG /* enable hwconfig */ 223 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 224 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 225 #ifdef CONFIG_PHYS_64BIT 226 #define PIXIS_BASE_PHYS 0xfffdf0000ull 227 #else 228 #define PIXIS_BASE_PHYS PIXIS_BASE 229 #endif 230 231 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 232 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 233 234 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 235 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 236 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 237 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 238 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 239 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 240 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 241 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 242 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 243 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 244 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 245 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 246 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 247 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 248 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 249 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 250 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 251 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 252 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 253 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 254 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 255 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 256 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 257 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 258 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 259 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 260 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 261 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 262 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 263 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 264 #define PIXIS_LED 0x25 /* LED Register */ 265 266 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 267 268 /* old pixis referenced names */ 269 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 270 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 271 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 272 #define PIXIS_VSPEED2_TSEC1SER 0x8 273 #define PIXIS_VSPEED2_TSEC2SER 0x4 274 #define PIXIS_VSPEED2_TSEC3SER 0x2 275 #define PIXIS_VSPEED2_TSEC4SER 0x1 276 #define PIXIS_VCFGEN1_TSEC1SER 0x20 277 #define PIXIS_VCFGEN1_TSEC2SER 0x20 278 #define PIXIS_VCFGEN1_TSEC3SER 0x20 279 #define PIXIS_VCFGEN1_TSEC4SER 0x20 280 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 281 | PIXIS_VSPEED2_TSEC2SER \ 282 | PIXIS_VSPEED2_TSEC3SER \ 283 | PIXIS_VSPEED2_TSEC4SER) 284 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 285 | PIXIS_VCFGEN1_TSEC2SER \ 286 | PIXIS_VCFGEN1_TSEC3SER \ 287 | PIXIS_VCFGEN1_TSEC4SER) 288 289 #define CONFIG_SYS_INIT_RAM_LOCK 1 290 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 291 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 292 293 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 294 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 295 296 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 297 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 298 299 #ifndef CONFIG_NAND_SPL 300 #define CONFIG_SYS_NAND_BASE 0xffa00000 301 #ifdef CONFIG_PHYS_64BIT 302 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 303 #else 304 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 305 #endif 306 #else 307 #define CONFIG_SYS_NAND_BASE 0xfff00000 308 #ifdef CONFIG_PHYS_64BIT 309 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 310 #else 311 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 312 #endif 313 #endif 314 315 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 316 CONFIG_SYS_NAND_BASE + 0x40000, \ 317 CONFIG_SYS_NAND_BASE + 0x80000,\ 318 CONFIG_SYS_NAND_BASE + 0xC0000} 319 #define CONFIG_SYS_MAX_NAND_DEVICE 4 320 #define CONFIG_MTD_NAND_VERIFY_WRITE 321 #define CONFIG_CMD_NAND 1 322 #define CONFIG_NAND_FSL_ELBC 1 323 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 324 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 325 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 326 327 /* NAND boot: 4K NAND loader config */ 328 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 329 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 330 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 331 #define CONFIG_SYS_NAND_U_BOOT_START \ 332 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 333 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 334 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 335 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 336 337 338 /* NAND flash config */ 339 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 340 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 341 | BR_PS_8 /* Port Size = 8 bit */ \ 342 | BR_MS_FCM /* MSEL = FCM */ \ 343 | BR_V) /* valid */ 344 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 345 | OR_FCM_PGS /* Large Page*/ \ 346 | OR_FCM_CSCT \ 347 | OR_FCM_CST \ 348 | OR_FCM_CHT \ 349 | OR_FCM_SCY_1 \ 350 | OR_FCM_TRLX \ 351 | OR_FCM_EHTR) 352 353 #ifdef CONFIG_RAMBOOT_NAND 354 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 355 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 356 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 357 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 358 #else 359 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 360 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 361 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 362 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 363 #endif 364 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 365 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 366 | BR_PS_8 /* Port Size = 8 bit */ \ 367 | BR_MS_FCM /* MSEL = FCM */ \ 368 | BR_V) /* valid */ 369 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 370 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 371 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 372 | BR_PS_8 /* Port Size = 8 bit */ \ 373 | BR_MS_FCM /* MSEL = FCM */ \ 374 | BR_V) /* valid */ 375 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 376 377 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 378 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 379 | BR_PS_8 /* Port Size = 8 bit */ \ 380 | BR_MS_FCM /* MSEL = FCM */ \ 381 | BR_V) /* valid */ 382 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 383 384 385 /* Serial Port - controlled on board with jumper J8 386 * open - index 2 387 * shorted - index 1 388 */ 389 #define CONFIG_CONS_INDEX 1 390 #define CONFIG_SYS_NS16550 391 #define CONFIG_SYS_NS16550_SERIAL 392 #define CONFIG_SYS_NS16550_REG_SIZE 1 393 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 394 #ifdef CONFIG_NAND_SPL 395 #define CONFIG_NS16550_MIN_FUNCTIONS 396 #endif 397 398 #define CONFIG_SYS_BAUDRATE_TABLE \ 399 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 400 401 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 402 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 403 404 /* Use the HUSH parser */ 405 #define CONFIG_SYS_HUSH_PARSER 406 407 /* 408 * Pass open firmware flat tree 409 */ 410 #define CONFIG_OF_LIBFDT 1 411 #define CONFIG_OF_BOARD_SETUP 1 412 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 413 414 /* new uImage format support */ 415 #define CONFIG_FIT 1 416 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 417 418 /* I2C */ 419 #define CONFIG_SYS_I2C 420 #define CONFIG_SYS_I2C_FSL 421 #define CONFIG_SYS_FSL_I2C_SPEED 400000 422 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 423 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 424 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 425 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 426 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 427 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 428 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 429 430 /* 431 * I2C2 EEPROM 432 */ 433 #define CONFIG_ID_EEPROM 434 #ifdef CONFIG_ID_EEPROM 435 #define CONFIG_SYS_I2C_EEPROM_NXID 436 #endif 437 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 438 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 439 #define CONFIG_SYS_EEPROM_BUS_NUM 1 440 441 /* 442 * General PCI 443 * Memory space is mapped 1-1, but I/O space must start from 0. 444 */ 445 446 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 447 #define CONFIG_SYS_PCIE3_NAME "ULI" 448 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 449 #ifdef CONFIG_PHYS_64BIT 450 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 451 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 452 #else 453 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 454 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 455 #endif 456 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 457 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 458 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 459 #ifdef CONFIG_PHYS_64BIT 460 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 461 #else 462 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 463 #endif 464 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 465 466 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 467 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 468 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 469 #ifdef CONFIG_PHYS_64BIT 470 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 471 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 472 #else 473 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 474 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 475 #endif 476 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 477 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 478 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 479 #ifdef CONFIG_PHYS_64BIT 480 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 481 #else 482 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 483 #endif 484 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 485 486 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 487 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 488 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 489 #ifdef CONFIG_PHYS_64BIT 490 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 491 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 492 #else 493 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 494 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 495 #endif 496 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 497 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 498 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 499 #ifdef CONFIG_PHYS_64BIT 500 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 501 #else 502 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 503 #endif 504 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 505 506 #if defined(CONFIG_PCI) 507 508 /*PCIE video card used*/ 509 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 510 511 /* video */ 512 #define CONFIG_VIDEO 513 514 #if defined(CONFIG_VIDEO) 515 #define CONFIG_BIOSEMU 516 #define CONFIG_CFB_CONSOLE 517 #define CONFIG_VIDEO_SW_CURSOR 518 #define CONFIG_VGA_AS_SINGLE_DEVICE 519 #define CONFIG_ATI_RADEON_FB 520 #define CONFIG_VIDEO_LOGO 521 /*#define CONFIG_CONSOLE_CURSOR*/ 522 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 523 #endif 524 525 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 526 527 #undef CONFIG_EEPRO100 528 #undef CONFIG_TULIP 529 #undef CONFIG_RTL8139 530 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 531 532 #ifndef CONFIG_PCI_PNP 533 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 534 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 535 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 536 #endif 537 538 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 539 #define CONFIG_DOS_PARTITION 540 #define CONFIG_SCSI_AHCI 541 542 #ifdef CONFIG_SCSI_AHCI 543 #define CONFIG_LIBATA 544 #define CONFIG_SATA_ULI5288 545 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 546 #define CONFIG_SYS_SCSI_MAX_LUN 1 547 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 548 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 549 #endif /* SCSI */ 550 551 #endif /* CONFIG_PCI */ 552 553 554 #if defined(CONFIG_TSEC_ENET) 555 556 #define CONFIG_MII 1 /* MII PHY management */ 557 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 558 #define CONFIG_TSEC1 1 559 #define CONFIG_TSEC1_NAME "eTSEC1" 560 #define CONFIG_TSEC2 1 561 #define CONFIG_TSEC2_NAME "eTSEC2" 562 #define CONFIG_TSEC3 1 563 #define CONFIG_TSEC3_NAME "eTSEC3" 564 #define CONFIG_TSEC4 1 565 #define CONFIG_TSEC4_NAME "eTSEC4" 566 567 #define CONFIG_PIXIS_SGMII_CMD 568 #define CONFIG_FSL_SGMII_RISER 1 569 #define SGMII_RISER_PHY_OFFSET 0x1c 570 571 #ifdef CONFIG_FSL_SGMII_RISER 572 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 573 #endif 574 575 #define TSEC1_PHY_ADDR 0 576 #define TSEC2_PHY_ADDR 1 577 #define TSEC3_PHY_ADDR 2 578 #define TSEC4_PHY_ADDR 3 579 580 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 581 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 582 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 583 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 584 585 #define TSEC1_PHYIDX 0 586 #define TSEC2_PHYIDX 0 587 #define TSEC3_PHYIDX 0 588 #define TSEC4_PHYIDX 0 589 590 #define CONFIG_ETHPRIME "eTSEC1" 591 592 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 593 #endif /* CONFIG_TSEC_ENET */ 594 595 /* 596 * Environment 597 */ 598 599 #if defined(CONFIG_SYS_RAMBOOT) 600 #if defined(CONFIG_RAMBOOT_NAND) 601 #define CONFIG_ENV_IS_IN_NAND 1 602 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 603 #define CONFIG_ENV_OFFSET ((512 * 1024)\ 604 + CONFIG_SYS_NAND_BLOCK_SIZE) 605 #endif 606 607 #else 608 #define CONFIG_ENV_IS_IN_FLASH 1 609 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 610 #define CONFIG_ENV_ADDR 0xfff80000 611 #else 612 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 613 #endif 614 #define CONFIG_ENV_SIZE 0x2000 615 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 616 #endif 617 618 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 619 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 620 621 /* 622 * Command line configuration. 623 */ 624 #include <config_cmd_default.h> 625 626 #define CONFIG_CMD_ERRATA 627 #define CONFIG_CMD_IRQ 628 #define CONFIG_CMD_PING 629 #define CONFIG_CMD_I2C 630 #define CONFIG_CMD_MII 631 #define CONFIG_CMD_ELF 632 #define CONFIG_CMD_SETEXPR 633 #define CONFIG_CMD_REGINFO 634 635 #if defined(CONFIG_PCI) 636 #define CONFIG_CMD_PCI 637 #define CONFIG_CMD_NET 638 #define CONFIG_CMD_SCSI 639 #define CONFIG_CMD_EXT2 640 #endif 641 642 /* 643 * USB 644 */ 645 #define CONFIG_USB_EHCI 646 647 #ifdef CONFIG_USB_EHCI 648 #define CONFIG_CMD_USB 649 #define CONFIG_USB_EHCI_PCI 650 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 651 #define CONFIG_USB_STORAGE 652 #define CONFIG_PCI_EHCI_DEVICE 0 653 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 654 #endif 655 656 #undef CONFIG_WATCHDOG /* watchdog disabled */ 657 658 /* 659 * Miscellaneous configurable options 660 */ 661 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 662 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 663 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 664 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 665 #if defined(CONFIG_CMD_KGDB) 666 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 667 #else 668 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 669 #endif 670 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 671 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 672 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 673 674 /* 675 * For booting Linux, the board info and command line data 676 * have to be in the first 64 MB of memory, since this is 677 * the maximum mapped by the Linux kernel during initialization. 678 */ 679 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 680 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 681 682 #if defined(CONFIG_CMD_KGDB) 683 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 684 #endif 685 686 /* 687 * Environment Configuration 688 */ 689 690 /* The mac addresses for all ethernet interface */ 691 #if defined(CONFIG_TSEC_ENET) 692 #define CONFIG_HAS_ETH0 693 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 694 #define CONFIG_HAS_ETH1 695 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 696 #define CONFIG_HAS_ETH2 697 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 698 #define CONFIG_HAS_ETH3 699 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 700 #endif 701 702 #define CONFIG_IPADDR 192.168.1.254 703 704 #define CONFIG_HOSTNAME unknown 705 #define CONFIG_ROOTPATH "/opt/nfsroot" 706 #define CONFIG_BOOTFILE "uImage" 707 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 708 709 #define CONFIG_SERVERIP 192.168.1.1 710 #define CONFIG_GATEWAYIP 192.168.1.1 711 #define CONFIG_NETMASK 255.255.255.0 712 713 /* default location for tftp and bootm */ 714 #define CONFIG_LOADADDR 1000000 715 716 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 717 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 718 719 #define CONFIG_BAUDRATE 115200 720 721 #define CONFIG_EXTRA_ENV_SETTINGS \ 722 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 723 "netdev=eth0\0" \ 724 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 725 "tftpflash=tftpboot $loadaddr $uboot; " \ 726 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 727 " +$filesize; " \ 728 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 729 " +$filesize; " \ 730 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 731 " $filesize; " \ 732 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 733 " +$filesize; " \ 734 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 735 " $filesize\0" \ 736 "consoledev=ttyS0\0" \ 737 "ramdiskaddr=2000000\0" \ 738 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 739 "fdtaddr=c00000\0" \ 740 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 741 "bdev=sda3\0" 742 743 #define CONFIG_HDBOOT \ 744 "setenv bootargs root=/dev/$bdev rw " \ 745 "console=$consoledev,$baudrate $othbootargs;" \ 746 "tftp $loadaddr $bootfile;" \ 747 "tftp $fdtaddr $fdtfile;" \ 748 "bootm $loadaddr - $fdtaddr" 749 750 #define CONFIG_NFSBOOTCOMMAND \ 751 "setenv bootargs root=/dev/nfs rw " \ 752 "nfsroot=$serverip:$rootpath " \ 753 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 754 "console=$consoledev,$baudrate $othbootargs;" \ 755 "tftp $loadaddr $bootfile;" \ 756 "tftp $fdtaddr $fdtfile;" \ 757 "bootm $loadaddr - $fdtaddr" 758 759 #define CONFIG_RAMBOOTCOMMAND \ 760 "setenv bootargs root=/dev/ram rw " \ 761 "console=$consoledev,$baudrate $othbootargs;" \ 762 "tftp $ramdiskaddr $ramdiskfile;" \ 763 "tftp $loadaddr $bootfile;" \ 764 "tftp $fdtaddr $fdtfile;" \ 765 "bootm $loadaddr $ramdiskaddr $fdtaddr" 766 767 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 768 769 #endif /* __CONFIG_H */ 770