1 /* 2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8572ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifndef CONFIG_SYS_TEXT_BASE 17 #define CONFIG_SYS_TEXT_BASE 0xeff40000 18 #endif 19 20 #ifndef CONFIG_RESET_VECTOR_ADDRESS 21 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 22 #endif 23 24 #ifndef CONFIG_SYS_MONITOR_BASE 25 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_MP 1 /* support multiple processors */ 30 31 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 32 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 33 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 34 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 35 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 36 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 37 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 38 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 39 40 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 41 #define CONFIG_ENV_OVERWRITE 42 43 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 44 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 45 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 46 47 /* 48 * These can be toggled for performance analysis, otherwise use default. 49 */ 50 #define CONFIG_L2_CACHE /* toggle L2 cache */ 51 #define CONFIG_BTB /* toggle branch predition */ 52 53 #define CONFIG_ENABLE_36BIT_PHYS 1 54 55 #ifdef CONFIG_PHYS_64BIT 56 #define CONFIG_ADDR_MAP 1 57 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 58 #endif 59 60 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 61 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 62 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 63 64 /* 65 * Config the L2 Cache as L2 SRAM 66 */ 67 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 68 #ifdef CONFIG_PHYS_64BIT 69 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 70 #else 71 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 72 #endif 73 #define CONFIG_SYS_L2_SIZE (512 << 10) 74 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 75 76 #define CONFIG_SYS_CCSRBAR 0xffe00000 77 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 78 79 #if defined(CONFIG_NAND_SPL) 80 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 81 #endif 82 83 /* DDR Setup */ 84 #define CONFIG_VERY_BIG_RAM 85 #undef CONFIG_FSL_DDR_INTERACTIVE 86 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 87 #define CONFIG_DDR_SPD 88 89 #define CONFIG_DDR_ECC 90 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 91 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 92 93 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 95 96 #define CONFIG_NUM_DDR_CONTROLLERS 2 97 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 98 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 99 100 /* I2C addresses of SPD EEPROMs */ 101 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 102 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 103 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 104 105 /* These are used when DDR doesn't use SPD. */ 106 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 107 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 108 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 109 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 110 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 111 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 112 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 113 #define CONFIG_SYS_DDR_MODE_1 0x00440462 114 #define CONFIG_SYS_DDR_MODE_2 0x00000000 115 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 116 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 117 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 118 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 119 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 120 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 121 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 122 123 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 124 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 125 #define CONFIG_SYS_DDR_SBE 0x00010000 126 127 /* 128 * Make sure required options are set 129 */ 130 #ifndef CONFIG_SPD_EEPROM 131 #error ("CONFIG_SPD_EEPROM is required") 132 #endif 133 134 #undef CONFIG_CLOCKS_IN_MHZ 135 136 /* 137 * Memory map 138 * 139 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 140 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 141 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 142 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 143 * 144 * Localbus cacheable (TBD) 145 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 146 * 147 * Localbus non-cacheable 148 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 149 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 150 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 151 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 152 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 153 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 154 */ 155 156 /* 157 * Local Bus Definitions 158 */ 159 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 160 #ifdef CONFIG_PHYS_64BIT 161 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 162 #else 163 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 164 #endif 165 166 #define CONFIG_FLASH_BR_PRELIM \ 167 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 168 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 169 170 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 171 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 172 173 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 174 #define CONFIG_SYS_FLASH_QUIET_TEST 175 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 176 177 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 178 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 179 #undef CONFIG_SYS_FLASH_CHECKSUM 180 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 181 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 182 183 #undef CONFIG_SYS_RAMBOOT 184 185 #define CONFIG_FLASH_CFI_DRIVER 186 #define CONFIG_SYS_FLASH_CFI 187 #define CONFIG_SYS_FLASH_EMPTY_INFO 188 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 189 190 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 191 192 #define CONFIG_HWCONFIG /* enable hwconfig */ 193 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 194 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 195 #ifdef CONFIG_PHYS_64BIT 196 #define PIXIS_BASE_PHYS 0xfffdf0000ull 197 #else 198 #define PIXIS_BASE_PHYS PIXIS_BASE 199 #endif 200 201 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 202 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 203 204 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 205 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 206 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 207 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 208 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 209 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 210 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 211 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 212 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 213 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 214 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 215 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 216 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 217 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 218 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 219 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 220 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 221 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 222 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 223 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 224 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 225 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 226 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 227 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 228 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 229 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 230 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 231 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 232 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 233 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 234 #define PIXIS_LED 0x25 /* LED Register */ 235 236 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 237 238 /* old pixis referenced names */ 239 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 240 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 241 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 242 #define PIXIS_VSPEED2_TSEC1SER 0x8 243 #define PIXIS_VSPEED2_TSEC2SER 0x4 244 #define PIXIS_VSPEED2_TSEC3SER 0x2 245 #define PIXIS_VSPEED2_TSEC4SER 0x1 246 #define PIXIS_VCFGEN1_TSEC1SER 0x20 247 #define PIXIS_VCFGEN1_TSEC2SER 0x20 248 #define PIXIS_VCFGEN1_TSEC3SER 0x20 249 #define PIXIS_VCFGEN1_TSEC4SER 0x20 250 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 251 | PIXIS_VSPEED2_TSEC2SER \ 252 | PIXIS_VSPEED2_TSEC3SER \ 253 | PIXIS_VSPEED2_TSEC4SER) 254 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 255 | PIXIS_VCFGEN1_TSEC2SER \ 256 | PIXIS_VCFGEN1_TSEC3SER \ 257 | PIXIS_VCFGEN1_TSEC4SER) 258 259 #define CONFIG_SYS_INIT_RAM_LOCK 1 260 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 261 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 262 263 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 264 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 265 266 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 267 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 268 269 #ifndef CONFIG_NAND_SPL 270 #define CONFIG_SYS_NAND_BASE 0xffa00000 271 #ifdef CONFIG_PHYS_64BIT 272 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 273 #else 274 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 275 #endif 276 #else 277 #define CONFIG_SYS_NAND_BASE 0xfff00000 278 #ifdef CONFIG_PHYS_64BIT 279 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 280 #else 281 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 282 #endif 283 #endif 284 285 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 286 CONFIG_SYS_NAND_BASE + 0x40000, \ 287 CONFIG_SYS_NAND_BASE + 0x80000,\ 288 CONFIG_SYS_NAND_BASE + 0xC0000} 289 #define CONFIG_SYS_MAX_NAND_DEVICE 4 290 #define CONFIG_CMD_NAND 1 291 #define CONFIG_NAND_FSL_ELBC 1 292 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 293 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 294 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 295 296 /* NAND boot: 4K NAND loader config */ 297 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 298 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 299 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 300 #define CONFIG_SYS_NAND_U_BOOT_START \ 301 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 302 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 303 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 304 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 305 306 /* NAND flash config */ 307 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 308 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 309 | BR_PS_8 /* Port Size = 8 bit */ \ 310 | BR_MS_FCM /* MSEL = FCM */ \ 311 | BR_V) /* valid */ 312 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 313 | OR_FCM_PGS /* Large Page*/ \ 314 | OR_FCM_CSCT \ 315 | OR_FCM_CST \ 316 | OR_FCM_CHT \ 317 | OR_FCM_SCY_1 \ 318 | OR_FCM_TRLX \ 319 | OR_FCM_EHTR) 320 321 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 322 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 323 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 324 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 325 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 326 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 327 | BR_PS_8 /* Port Size = 8 bit */ \ 328 | BR_MS_FCM /* MSEL = FCM */ \ 329 | BR_V) /* valid */ 330 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 331 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 332 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 333 | BR_PS_8 /* Port Size = 8 bit */ \ 334 | BR_MS_FCM /* MSEL = FCM */ \ 335 | BR_V) /* valid */ 336 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 337 338 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 339 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 340 | BR_PS_8 /* Port Size = 8 bit */ \ 341 | BR_MS_FCM /* MSEL = FCM */ \ 342 | BR_V) /* valid */ 343 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 344 345 /* Serial Port - controlled on board with jumper J8 346 * open - index 2 347 * shorted - index 1 348 */ 349 #define CONFIG_CONS_INDEX 1 350 #define CONFIG_SYS_NS16550_SERIAL 351 #define CONFIG_SYS_NS16550_REG_SIZE 1 352 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 353 #ifdef CONFIG_NAND_SPL 354 #define CONFIG_NS16550_MIN_FUNCTIONS 355 #endif 356 357 #define CONFIG_SYS_BAUDRATE_TABLE \ 358 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 359 360 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 361 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 362 363 /* I2C */ 364 #define CONFIG_SYS_I2C 365 #define CONFIG_SYS_I2C_FSL 366 #define CONFIG_SYS_FSL_I2C_SPEED 400000 367 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 368 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 369 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 370 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 371 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 372 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 373 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 374 375 /* 376 * I2C2 EEPROM 377 */ 378 #define CONFIG_ID_EEPROM 379 #ifdef CONFIG_ID_EEPROM 380 #define CONFIG_SYS_I2C_EEPROM_NXID 381 #endif 382 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 383 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 384 #define CONFIG_SYS_EEPROM_BUS_NUM 1 385 386 /* 387 * General PCI 388 * Memory space is mapped 1-1, but I/O space must start from 0. 389 */ 390 391 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 392 #define CONFIG_SYS_PCIE3_NAME "ULI" 393 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 394 #ifdef CONFIG_PHYS_64BIT 395 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 396 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 397 #else 398 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 399 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 400 #endif 401 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 402 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 403 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 404 #ifdef CONFIG_PHYS_64BIT 405 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 406 #else 407 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 408 #endif 409 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 410 411 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 412 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 413 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 414 #ifdef CONFIG_PHYS_64BIT 415 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 416 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 417 #else 418 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 419 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 420 #endif 421 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 422 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 423 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 426 #else 427 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 428 #endif 429 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 430 431 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 432 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 433 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 434 #ifdef CONFIG_PHYS_64BIT 435 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 436 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 437 #else 438 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 439 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 440 #endif 441 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 442 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 443 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 444 #ifdef CONFIG_PHYS_64BIT 445 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 446 #else 447 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 448 #endif 449 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 450 451 #if defined(CONFIG_PCI) 452 453 /*PCIE video card used*/ 454 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 455 456 /* video */ 457 458 #if defined(CONFIG_VIDEO) 459 #define CONFIG_BIOSEMU 460 #define CONFIG_ATI_RADEON_FB 461 #define CONFIG_VIDEO_LOGO 462 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 463 #endif 464 465 #undef CONFIG_EEPRO100 466 #undef CONFIG_TULIP 467 468 #ifndef CONFIG_PCI_PNP 469 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 470 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 471 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 472 #endif 473 474 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 475 #define CONFIG_DOS_PARTITION 476 #define CONFIG_SCSI_AHCI 477 478 #ifdef CONFIG_SCSI_AHCI 479 #define CONFIG_LIBATA 480 #define CONFIG_SATA_ULI5288 481 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 482 #define CONFIG_SYS_SCSI_MAX_LUN 1 483 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 484 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 485 #endif /* SCSI */ 486 487 #endif /* CONFIG_PCI */ 488 489 #if defined(CONFIG_TSEC_ENET) 490 491 #define CONFIG_MII 1 /* MII PHY management */ 492 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 493 #define CONFIG_TSEC1 1 494 #define CONFIG_TSEC1_NAME "eTSEC1" 495 #define CONFIG_TSEC2 1 496 #define CONFIG_TSEC2_NAME "eTSEC2" 497 #define CONFIG_TSEC3 1 498 #define CONFIG_TSEC3_NAME "eTSEC3" 499 #define CONFIG_TSEC4 1 500 #define CONFIG_TSEC4_NAME "eTSEC4" 501 502 #define CONFIG_PIXIS_SGMII_CMD 503 #define CONFIG_FSL_SGMII_RISER 1 504 #define SGMII_RISER_PHY_OFFSET 0x1c 505 506 #ifdef CONFIG_FSL_SGMII_RISER 507 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 508 #endif 509 510 #define TSEC1_PHY_ADDR 0 511 #define TSEC2_PHY_ADDR 1 512 #define TSEC3_PHY_ADDR 2 513 #define TSEC4_PHY_ADDR 3 514 515 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 516 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 517 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 518 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 519 520 #define TSEC1_PHYIDX 0 521 #define TSEC2_PHYIDX 0 522 #define TSEC3_PHYIDX 0 523 #define TSEC4_PHYIDX 0 524 525 #define CONFIG_ETHPRIME "eTSEC1" 526 527 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 528 #endif /* CONFIG_TSEC_ENET */ 529 530 /* 531 * Environment 532 */ 533 534 #if defined(CONFIG_SYS_RAMBOOT) 535 536 #else 537 #define CONFIG_ENV_IS_IN_FLASH 1 538 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 539 #define CONFIG_ENV_ADDR 0xfff80000 540 #else 541 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 542 #endif 543 #define CONFIG_ENV_SIZE 0x2000 544 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 545 #endif 546 547 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 548 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 549 550 /* 551 * Command line configuration. 552 */ 553 #define CONFIG_CMD_ERRATA 554 #define CONFIG_CMD_IRQ 555 #define CONFIG_CMD_REGINFO 556 557 #if defined(CONFIG_PCI) 558 #define CONFIG_CMD_PCI 559 #define CONFIG_SCSI 560 #endif 561 562 /* 563 * USB 564 */ 565 #define CONFIG_USB_EHCI 566 567 #ifdef CONFIG_USB_EHCI 568 #define CONFIG_USB_EHCI_PCI 569 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 570 #define CONFIG_PCI_EHCI_DEVICE 0 571 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 572 #endif 573 574 #undef CONFIG_WATCHDOG /* watchdog disabled */ 575 576 /* 577 * Miscellaneous configurable options 578 */ 579 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 580 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 581 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 582 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 583 #if defined(CONFIG_CMD_KGDB) 584 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 585 #else 586 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 587 #endif 588 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 589 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 590 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 591 592 /* 593 * For booting Linux, the board info and command line data 594 * have to be in the first 64 MB of memory, since this is 595 * the maximum mapped by the Linux kernel during initialization. 596 */ 597 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 598 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 599 600 #if defined(CONFIG_CMD_KGDB) 601 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 602 #endif 603 604 /* 605 * Environment Configuration 606 */ 607 #if defined(CONFIG_TSEC_ENET) 608 #define CONFIG_HAS_ETH0 609 #define CONFIG_HAS_ETH1 610 #define CONFIG_HAS_ETH2 611 #define CONFIG_HAS_ETH3 612 #endif 613 614 #define CONFIG_IPADDR 192.168.1.254 615 616 #define CONFIG_HOSTNAME unknown 617 #define CONFIG_ROOTPATH "/opt/nfsroot" 618 #define CONFIG_BOOTFILE "uImage" 619 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 620 621 #define CONFIG_SERVERIP 192.168.1.1 622 #define CONFIG_GATEWAYIP 192.168.1.1 623 #define CONFIG_NETMASK 255.255.255.0 624 625 /* default location for tftp and bootm */ 626 #define CONFIG_LOADADDR 1000000 627 628 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 629 630 #define CONFIG_BAUDRATE 115200 631 632 #define CONFIG_EXTRA_ENV_SETTINGS \ 633 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 634 "netdev=eth0\0" \ 635 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 636 "tftpflash=tftpboot $loadaddr $uboot; " \ 637 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 638 " +$filesize; " \ 639 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 640 " +$filesize; " \ 641 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 642 " $filesize; " \ 643 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 644 " +$filesize; " \ 645 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 646 " $filesize\0" \ 647 "consoledev=ttyS0\0" \ 648 "ramdiskaddr=2000000\0" \ 649 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 650 "fdtaddr=1e00000\0" \ 651 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 652 "bdev=sda3\0" 653 654 #define CONFIG_HDBOOT \ 655 "setenv bootargs root=/dev/$bdev rw " \ 656 "console=$consoledev,$baudrate $othbootargs;" \ 657 "tftp $loadaddr $bootfile;" \ 658 "tftp $fdtaddr $fdtfile;" \ 659 "bootm $loadaddr - $fdtaddr" 660 661 #define CONFIG_NFSBOOTCOMMAND \ 662 "setenv bootargs root=/dev/nfs rw " \ 663 "nfsroot=$serverip:$rootpath " \ 664 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 665 "console=$consoledev,$baudrate $othbootargs;" \ 666 "tftp $loadaddr $bootfile;" \ 667 "tftp $fdtaddr $fdtfile;" \ 668 "bootm $loadaddr - $fdtaddr" 669 670 #define CONFIG_RAMBOOTCOMMAND \ 671 "setenv bootargs root=/dev/ram rw " \ 672 "console=$consoledev,$baudrate $othbootargs;" \ 673 "tftp $ramdiskaddr $ramdiskfile;" \ 674 "tftp $loadaddr $bootfile;" \ 675 "tftp $fdtaddr $fdtfile;" \ 676 "bootm $loadaddr $ramdiskaddr $fdtaddr" 677 678 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 679 680 #endif /* __CONFIG_H */ 681