1 /* 2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8572ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #include "../board/freescale/common/ics307_clk.h" 17 18 #ifdef CONFIG_36BIT 19 #define CONFIG_PHYS_64BIT 20 #endif 21 22 #ifndef CONFIG_SYS_TEXT_BASE 23 #define CONFIG_SYS_TEXT_BASE 0xeff40000 24 #endif 25 26 #ifndef CONFIG_RESET_VECTOR_ADDRESS 27 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 28 #endif 29 30 #ifndef CONFIG_SYS_MONITOR_BASE 31 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 32 #endif 33 34 /* High Level Configuration Options */ 35 #define CONFIG_BOOKE 1 /* BOOKE */ 36 #define CONFIG_E500 1 /* BOOKE e500 family */ 37 #define CONFIG_MPC8572 1 38 #define CONFIG_MPC8572DS 1 39 #define CONFIG_MP 1 /* support multiple processors */ 40 41 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 42 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 43 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 44 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 45 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 46 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 47 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 48 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 49 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 50 51 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 52 53 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 54 #define CONFIG_ENV_OVERWRITE 55 56 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 57 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 58 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 59 60 /* 61 * These can be toggled for performance analysis, otherwise use default. 62 */ 63 #define CONFIG_L2_CACHE /* toggle L2 cache */ 64 #define CONFIG_BTB /* toggle branch predition */ 65 66 #define CONFIG_ENABLE_36BIT_PHYS 1 67 68 #ifdef CONFIG_PHYS_64BIT 69 #define CONFIG_ADDR_MAP 1 70 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 71 #endif 72 73 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 74 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 75 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 76 77 /* 78 * Config the L2 Cache as L2 SRAM 79 */ 80 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 81 #ifdef CONFIG_PHYS_64BIT 82 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 83 #else 84 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 85 #endif 86 #define CONFIG_SYS_L2_SIZE (512 << 10) 87 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 88 89 #define CONFIG_SYS_CCSRBAR 0xffe00000 90 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 91 92 #if defined(CONFIG_NAND_SPL) 93 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 94 #endif 95 96 /* DDR Setup */ 97 #define CONFIG_VERY_BIG_RAM 98 #define CONFIG_SYS_FSL_DDR2 99 #undef CONFIG_FSL_DDR_INTERACTIVE 100 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 101 #define CONFIG_DDR_SPD 102 103 #define CONFIG_DDR_ECC 104 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 105 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 106 107 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 108 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 109 110 #define CONFIG_NUM_DDR_CONTROLLERS 2 111 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 112 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 113 114 /* I2C addresses of SPD EEPROMs */ 115 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 116 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 117 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 118 119 /* These are used when DDR doesn't use SPD. */ 120 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 121 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 122 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 123 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 124 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 125 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 126 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 127 #define CONFIG_SYS_DDR_MODE_1 0x00440462 128 #define CONFIG_SYS_DDR_MODE_2 0x00000000 129 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 130 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 131 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 132 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 133 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 134 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 135 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 136 137 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 138 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 139 #define CONFIG_SYS_DDR_SBE 0x00010000 140 141 /* 142 * Make sure required options are set 143 */ 144 #ifndef CONFIG_SPD_EEPROM 145 #error ("CONFIG_SPD_EEPROM is required") 146 #endif 147 148 #undef CONFIG_CLOCKS_IN_MHZ 149 150 /* 151 * Memory map 152 * 153 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 154 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 155 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 156 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 157 * 158 * Localbus cacheable (TBD) 159 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 160 * 161 * Localbus non-cacheable 162 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 163 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 164 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 165 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 166 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 167 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 168 */ 169 170 /* 171 * Local Bus Definitions 172 */ 173 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 174 #ifdef CONFIG_PHYS_64BIT 175 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 176 #else 177 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 178 #endif 179 180 181 #define CONFIG_FLASH_BR_PRELIM \ 182 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 183 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 184 185 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 186 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 187 188 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 189 #define CONFIG_SYS_FLASH_QUIET_TEST 190 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 191 192 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 193 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 194 #undef CONFIG_SYS_FLASH_CHECKSUM 195 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 196 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 197 198 #undef CONFIG_SYS_RAMBOOT 199 200 #define CONFIG_FLASH_CFI_DRIVER 201 #define CONFIG_SYS_FLASH_CFI 202 #define CONFIG_SYS_FLASH_EMPTY_INFO 203 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 204 205 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 206 207 #define CONFIG_HWCONFIG /* enable hwconfig */ 208 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 209 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 210 #ifdef CONFIG_PHYS_64BIT 211 #define PIXIS_BASE_PHYS 0xfffdf0000ull 212 #else 213 #define PIXIS_BASE_PHYS PIXIS_BASE 214 #endif 215 216 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 217 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 218 219 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 220 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 221 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 222 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 223 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 224 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 225 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 226 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 227 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 228 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 229 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 230 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 231 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 232 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 233 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 234 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 235 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 236 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 237 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 238 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 239 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 240 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 241 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 242 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 243 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 244 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 245 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 246 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 247 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 248 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 249 #define PIXIS_LED 0x25 /* LED Register */ 250 251 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 252 253 /* old pixis referenced names */ 254 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 255 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 256 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 257 #define PIXIS_VSPEED2_TSEC1SER 0x8 258 #define PIXIS_VSPEED2_TSEC2SER 0x4 259 #define PIXIS_VSPEED2_TSEC3SER 0x2 260 #define PIXIS_VSPEED2_TSEC4SER 0x1 261 #define PIXIS_VCFGEN1_TSEC1SER 0x20 262 #define PIXIS_VCFGEN1_TSEC2SER 0x20 263 #define PIXIS_VCFGEN1_TSEC3SER 0x20 264 #define PIXIS_VCFGEN1_TSEC4SER 0x20 265 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 266 | PIXIS_VSPEED2_TSEC2SER \ 267 | PIXIS_VSPEED2_TSEC3SER \ 268 | PIXIS_VSPEED2_TSEC4SER) 269 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 270 | PIXIS_VCFGEN1_TSEC2SER \ 271 | PIXIS_VCFGEN1_TSEC3SER \ 272 | PIXIS_VCFGEN1_TSEC4SER) 273 274 #define CONFIG_SYS_INIT_RAM_LOCK 1 275 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 276 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 277 278 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 279 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 280 281 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 282 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 283 284 #ifndef CONFIG_NAND_SPL 285 #define CONFIG_SYS_NAND_BASE 0xffa00000 286 #ifdef CONFIG_PHYS_64BIT 287 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 288 #else 289 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 290 #endif 291 #else 292 #define CONFIG_SYS_NAND_BASE 0xfff00000 293 #ifdef CONFIG_PHYS_64BIT 294 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 295 #else 296 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 297 #endif 298 #endif 299 300 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 301 CONFIG_SYS_NAND_BASE + 0x40000, \ 302 CONFIG_SYS_NAND_BASE + 0x80000,\ 303 CONFIG_SYS_NAND_BASE + 0xC0000} 304 #define CONFIG_SYS_MAX_NAND_DEVICE 4 305 #define CONFIG_CMD_NAND 1 306 #define CONFIG_NAND_FSL_ELBC 1 307 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 308 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 309 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 310 311 /* NAND boot: 4K NAND loader config */ 312 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 313 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 314 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 315 #define CONFIG_SYS_NAND_U_BOOT_START \ 316 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 317 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 318 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 319 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 320 321 322 /* NAND flash config */ 323 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 324 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 325 | BR_PS_8 /* Port Size = 8 bit */ \ 326 | BR_MS_FCM /* MSEL = FCM */ \ 327 | BR_V) /* valid */ 328 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 329 | OR_FCM_PGS /* Large Page*/ \ 330 | OR_FCM_CSCT \ 331 | OR_FCM_CST \ 332 | OR_FCM_CHT \ 333 | OR_FCM_SCY_1 \ 334 | OR_FCM_TRLX \ 335 | OR_FCM_EHTR) 336 337 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 338 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 339 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 340 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 341 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 342 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 343 | BR_PS_8 /* Port Size = 8 bit */ \ 344 | BR_MS_FCM /* MSEL = FCM */ \ 345 | BR_V) /* valid */ 346 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 347 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 348 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 349 | BR_PS_8 /* Port Size = 8 bit */ \ 350 | BR_MS_FCM /* MSEL = FCM */ \ 351 | BR_V) /* valid */ 352 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 353 354 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 355 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 356 | BR_PS_8 /* Port Size = 8 bit */ \ 357 | BR_MS_FCM /* MSEL = FCM */ \ 358 | BR_V) /* valid */ 359 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 360 361 362 /* Serial Port - controlled on board with jumper J8 363 * open - index 2 364 * shorted - index 1 365 */ 366 #define CONFIG_CONS_INDEX 1 367 #define CONFIG_SYS_NS16550 368 #define CONFIG_SYS_NS16550_SERIAL 369 #define CONFIG_SYS_NS16550_REG_SIZE 1 370 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 371 #ifdef CONFIG_NAND_SPL 372 #define CONFIG_NS16550_MIN_FUNCTIONS 373 #endif 374 375 #define CONFIG_SYS_BAUDRATE_TABLE \ 376 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 377 378 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 379 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 380 381 /* Use the HUSH parser */ 382 #define CONFIG_SYS_HUSH_PARSER 383 384 /* 385 * Pass open firmware flat tree 386 */ 387 #define CONFIG_OF_LIBFDT 1 388 #define CONFIG_OF_BOARD_SETUP 1 389 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 390 391 /* new uImage format support */ 392 #define CONFIG_FIT 1 393 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 394 395 /* I2C */ 396 #define CONFIG_SYS_I2C 397 #define CONFIG_SYS_I2C_FSL 398 #define CONFIG_SYS_FSL_I2C_SPEED 400000 399 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 400 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 401 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 402 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 403 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 404 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 405 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 406 407 /* 408 * I2C2 EEPROM 409 */ 410 #define CONFIG_ID_EEPROM 411 #ifdef CONFIG_ID_EEPROM 412 #define CONFIG_SYS_I2C_EEPROM_NXID 413 #endif 414 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 415 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 416 #define CONFIG_SYS_EEPROM_BUS_NUM 1 417 418 /* 419 * General PCI 420 * Memory space is mapped 1-1, but I/O space must start from 0. 421 */ 422 423 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 424 #define CONFIG_SYS_PCIE3_NAME "ULI" 425 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 426 #ifdef CONFIG_PHYS_64BIT 427 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 428 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 429 #else 430 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 431 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 432 #endif 433 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 434 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 435 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 436 #ifdef CONFIG_PHYS_64BIT 437 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 438 #else 439 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 440 #endif 441 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 442 443 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 444 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 445 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 446 #ifdef CONFIG_PHYS_64BIT 447 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 448 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 449 #else 450 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 451 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 452 #endif 453 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 454 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 455 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 456 #ifdef CONFIG_PHYS_64BIT 457 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 458 #else 459 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 460 #endif 461 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 462 463 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 464 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 465 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 466 #ifdef CONFIG_PHYS_64BIT 467 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 468 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 469 #else 470 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 471 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 472 #endif 473 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 474 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 475 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 476 #ifdef CONFIG_PHYS_64BIT 477 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 478 #else 479 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 480 #endif 481 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 482 483 #if defined(CONFIG_PCI) 484 485 /*PCIE video card used*/ 486 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 487 488 /* video */ 489 #define CONFIG_VIDEO 490 491 #if defined(CONFIG_VIDEO) 492 #define CONFIG_BIOSEMU 493 #define CONFIG_CFB_CONSOLE 494 #define CONFIG_VIDEO_SW_CURSOR 495 #define CONFIG_VGA_AS_SINGLE_DEVICE 496 #define CONFIG_ATI_RADEON_FB 497 #define CONFIG_VIDEO_LOGO 498 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 499 #endif 500 501 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 502 503 #undef CONFIG_EEPRO100 504 #undef CONFIG_TULIP 505 #undef CONFIG_RTL8139 506 507 #ifndef CONFIG_PCI_PNP 508 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 509 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 510 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 511 #endif 512 513 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 514 #define CONFIG_DOS_PARTITION 515 #define CONFIG_SCSI_AHCI 516 517 #ifdef CONFIG_SCSI_AHCI 518 #define CONFIG_LIBATA 519 #define CONFIG_SATA_ULI5288 520 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 521 #define CONFIG_SYS_SCSI_MAX_LUN 1 522 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 523 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 524 #endif /* SCSI */ 525 526 #endif /* CONFIG_PCI */ 527 528 529 #if defined(CONFIG_TSEC_ENET) 530 531 #define CONFIG_MII 1 /* MII PHY management */ 532 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 533 #define CONFIG_TSEC1 1 534 #define CONFIG_TSEC1_NAME "eTSEC1" 535 #define CONFIG_TSEC2 1 536 #define CONFIG_TSEC2_NAME "eTSEC2" 537 #define CONFIG_TSEC3 1 538 #define CONFIG_TSEC3_NAME "eTSEC3" 539 #define CONFIG_TSEC4 1 540 #define CONFIG_TSEC4_NAME "eTSEC4" 541 542 #define CONFIG_PIXIS_SGMII_CMD 543 #define CONFIG_FSL_SGMII_RISER 1 544 #define SGMII_RISER_PHY_OFFSET 0x1c 545 546 #ifdef CONFIG_FSL_SGMII_RISER 547 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 548 #endif 549 550 #define TSEC1_PHY_ADDR 0 551 #define TSEC2_PHY_ADDR 1 552 #define TSEC3_PHY_ADDR 2 553 #define TSEC4_PHY_ADDR 3 554 555 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 556 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 557 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 558 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 559 560 #define TSEC1_PHYIDX 0 561 #define TSEC2_PHYIDX 0 562 #define TSEC3_PHYIDX 0 563 #define TSEC4_PHYIDX 0 564 565 #define CONFIG_ETHPRIME "eTSEC1" 566 567 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 568 #endif /* CONFIG_TSEC_ENET */ 569 570 /* 571 * Environment 572 */ 573 574 #if defined(CONFIG_SYS_RAMBOOT) 575 576 #else 577 #define CONFIG_ENV_IS_IN_FLASH 1 578 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 579 #define CONFIG_ENV_ADDR 0xfff80000 580 #else 581 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 582 #endif 583 #define CONFIG_ENV_SIZE 0x2000 584 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 585 #endif 586 587 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 588 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 589 590 /* 591 * Command line configuration. 592 */ 593 #define CONFIG_CMD_ERRATA 594 #define CONFIG_CMD_IRQ 595 #define CONFIG_CMD_PING 596 #define CONFIG_CMD_I2C 597 #define CONFIG_CMD_MII 598 #define CONFIG_CMD_REGINFO 599 600 #if defined(CONFIG_PCI) 601 #define CONFIG_CMD_PCI 602 #define CONFIG_CMD_SCSI 603 #define CONFIG_CMD_EXT2 604 #endif 605 606 /* 607 * USB 608 */ 609 #define CONFIG_USB_EHCI 610 611 #ifdef CONFIG_USB_EHCI 612 #define CONFIG_CMD_USB 613 #define CONFIG_USB_EHCI_PCI 614 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 615 #define CONFIG_USB_STORAGE 616 #define CONFIG_PCI_EHCI_DEVICE 0 617 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 618 #endif 619 620 #undef CONFIG_WATCHDOG /* watchdog disabled */ 621 622 /* 623 * Miscellaneous configurable options 624 */ 625 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 626 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 627 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 628 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 629 #if defined(CONFIG_CMD_KGDB) 630 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 631 #else 632 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 633 #endif 634 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 635 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 636 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 637 638 /* 639 * For booting Linux, the board info and command line data 640 * have to be in the first 64 MB of memory, since this is 641 * the maximum mapped by the Linux kernel during initialization. 642 */ 643 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 644 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 645 646 #if defined(CONFIG_CMD_KGDB) 647 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 648 #endif 649 650 /* 651 * Environment Configuration 652 */ 653 #if defined(CONFIG_TSEC_ENET) 654 #define CONFIG_HAS_ETH0 655 #define CONFIG_HAS_ETH1 656 #define CONFIG_HAS_ETH2 657 #define CONFIG_HAS_ETH3 658 #endif 659 660 #define CONFIG_IPADDR 192.168.1.254 661 662 #define CONFIG_HOSTNAME unknown 663 #define CONFIG_ROOTPATH "/opt/nfsroot" 664 #define CONFIG_BOOTFILE "uImage" 665 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 666 667 #define CONFIG_SERVERIP 192.168.1.1 668 #define CONFIG_GATEWAYIP 192.168.1.1 669 #define CONFIG_NETMASK 255.255.255.0 670 671 /* default location for tftp and bootm */ 672 #define CONFIG_LOADADDR 1000000 673 674 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 675 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 676 677 #define CONFIG_BAUDRATE 115200 678 679 #define CONFIG_EXTRA_ENV_SETTINGS \ 680 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 681 "netdev=eth0\0" \ 682 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 683 "tftpflash=tftpboot $loadaddr $uboot; " \ 684 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 685 " +$filesize; " \ 686 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 687 " +$filesize; " \ 688 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 689 " $filesize; " \ 690 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 691 " +$filesize; " \ 692 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 693 " $filesize\0" \ 694 "consoledev=ttyS0\0" \ 695 "ramdiskaddr=2000000\0" \ 696 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 697 "fdtaddr=c00000\0" \ 698 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 699 "bdev=sda3\0" 700 701 #define CONFIG_HDBOOT \ 702 "setenv bootargs root=/dev/$bdev rw " \ 703 "console=$consoledev,$baudrate $othbootargs;" \ 704 "tftp $loadaddr $bootfile;" \ 705 "tftp $fdtaddr $fdtfile;" \ 706 "bootm $loadaddr - $fdtaddr" 707 708 #define CONFIG_NFSBOOTCOMMAND \ 709 "setenv bootargs root=/dev/nfs rw " \ 710 "nfsroot=$serverip:$rootpath " \ 711 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 712 "console=$consoledev,$baudrate $othbootargs;" \ 713 "tftp $loadaddr $bootfile;" \ 714 "tftp $fdtaddr $fdtfile;" \ 715 "bootm $loadaddr - $fdtaddr" 716 717 #define CONFIG_RAMBOOTCOMMAND \ 718 "setenv bootargs root=/dev/ram rw " \ 719 "console=$consoledev,$baudrate $othbootargs;" \ 720 "tftp $ramdiskaddr $ramdiskfile;" \ 721 "tftp $loadaddr $bootfile;" \ 722 "tftp $fdtaddr $fdtfile;" \ 723 "bootm $loadaddr $ramdiskaddr $fdtaddr" 724 725 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 726 727 #endif /* __CONFIG_H */ 728