1 /* 2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8572ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifndef CONFIG_SYS_TEXT_BASE 17 #define CONFIG_SYS_TEXT_BASE 0xeff40000 18 #endif 19 20 #ifndef CONFIG_RESET_VECTOR_ADDRESS 21 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 22 #endif 23 24 #ifndef CONFIG_SYS_MONITOR_BASE 25 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_MP 1 /* support multiple processors */ 30 31 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 32 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 33 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 34 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 35 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 36 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 37 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 38 39 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 40 #define CONFIG_ENV_OVERWRITE 41 42 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 43 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 44 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 45 46 /* 47 * These can be toggled for performance analysis, otherwise use default. 48 */ 49 #define CONFIG_L2_CACHE /* toggle L2 cache */ 50 #define CONFIG_BTB /* toggle branch predition */ 51 52 #define CONFIG_ENABLE_36BIT_PHYS 1 53 54 #ifdef CONFIG_PHYS_64BIT 55 #define CONFIG_ADDR_MAP 1 56 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 57 #endif 58 59 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 60 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 61 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 62 63 /* 64 * Config the L2 Cache as L2 SRAM 65 */ 66 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 67 #ifdef CONFIG_PHYS_64BIT 68 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 69 #else 70 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 71 #endif 72 #define CONFIG_SYS_L2_SIZE (512 << 10) 73 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 74 75 #define CONFIG_SYS_CCSRBAR 0xffe00000 76 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 77 78 #if defined(CONFIG_NAND_SPL) 79 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 80 #endif 81 82 /* DDR Setup */ 83 #define CONFIG_VERY_BIG_RAM 84 #undef CONFIG_FSL_DDR_INTERACTIVE 85 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 86 #define CONFIG_DDR_SPD 87 88 #define CONFIG_DDR_ECC 89 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 90 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 91 92 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 93 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 94 95 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 96 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 97 98 /* I2C addresses of SPD EEPROMs */ 99 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 100 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 101 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 102 103 /* These are used when DDR doesn't use SPD. */ 104 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 105 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 106 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 107 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 108 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 109 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 110 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 111 #define CONFIG_SYS_DDR_MODE_1 0x00440462 112 #define CONFIG_SYS_DDR_MODE_2 0x00000000 113 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 114 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 115 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 116 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 117 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 118 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 119 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 120 121 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 122 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 123 #define CONFIG_SYS_DDR_SBE 0x00010000 124 125 /* 126 * Make sure required options are set 127 */ 128 #ifndef CONFIG_SPD_EEPROM 129 #error ("CONFIG_SPD_EEPROM is required") 130 #endif 131 132 #undef CONFIG_CLOCKS_IN_MHZ 133 134 /* 135 * Memory map 136 * 137 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 138 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 139 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 140 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 141 * 142 * Localbus cacheable (TBD) 143 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 144 * 145 * Localbus non-cacheable 146 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 147 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 148 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 149 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 150 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 151 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 152 */ 153 154 /* 155 * Local Bus Definitions 156 */ 157 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 158 #ifdef CONFIG_PHYS_64BIT 159 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 160 #else 161 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 162 #endif 163 164 #define CONFIG_FLASH_BR_PRELIM \ 165 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 166 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 167 168 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 169 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 170 171 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 172 #define CONFIG_SYS_FLASH_QUIET_TEST 173 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 174 175 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 176 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 177 #undef CONFIG_SYS_FLASH_CHECKSUM 178 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 179 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 180 181 #undef CONFIG_SYS_RAMBOOT 182 183 #define CONFIG_FLASH_CFI_DRIVER 184 #define CONFIG_SYS_FLASH_CFI 185 #define CONFIG_SYS_FLASH_EMPTY_INFO 186 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 187 188 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 189 190 #define CONFIG_HWCONFIG /* enable hwconfig */ 191 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 192 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 193 #ifdef CONFIG_PHYS_64BIT 194 #define PIXIS_BASE_PHYS 0xfffdf0000ull 195 #else 196 #define PIXIS_BASE_PHYS PIXIS_BASE 197 #endif 198 199 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 200 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 201 202 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 203 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 204 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 205 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 206 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 207 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 208 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 209 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 210 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 211 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 212 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 213 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 214 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 215 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 216 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 217 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 218 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 219 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 220 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 221 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 222 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 223 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 224 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 225 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 226 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 227 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 228 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 229 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 230 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 231 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 232 #define PIXIS_LED 0x25 /* LED Register */ 233 234 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 235 236 /* old pixis referenced names */ 237 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 238 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 239 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 240 #define PIXIS_VSPEED2_TSEC1SER 0x8 241 #define PIXIS_VSPEED2_TSEC2SER 0x4 242 #define PIXIS_VSPEED2_TSEC3SER 0x2 243 #define PIXIS_VSPEED2_TSEC4SER 0x1 244 #define PIXIS_VCFGEN1_TSEC1SER 0x20 245 #define PIXIS_VCFGEN1_TSEC2SER 0x20 246 #define PIXIS_VCFGEN1_TSEC3SER 0x20 247 #define PIXIS_VCFGEN1_TSEC4SER 0x20 248 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 249 | PIXIS_VSPEED2_TSEC2SER \ 250 | PIXIS_VSPEED2_TSEC3SER \ 251 | PIXIS_VSPEED2_TSEC4SER) 252 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 253 | PIXIS_VCFGEN1_TSEC2SER \ 254 | PIXIS_VCFGEN1_TSEC3SER \ 255 | PIXIS_VCFGEN1_TSEC4SER) 256 257 #define CONFIG_SYS_INIT_RAM_LOCK 1 258 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 259 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 260 261 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 262 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 263 264 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 265 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 266 267 #ifndef CONFIG_NAND_SPL 268 #define CONFIG_SYS_NAND_BASE 0xffa00000 269 #ifdef CONFIG_PHYS_64BIT 270 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 271 #else 272 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 273 #endif 274 #else 275 #define CONFIG_SYS_NAND_BASE 0xfff00000 276 #ifdef CONFIG_PHYS_64BIT 277 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 278 #else 279 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 280 #endif 281 #endif 282 283 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 284 CONFIG_SYS_NAND_BASE + 0x40000, \ 285 CONFIG_SYS_NAND_BASE + 0x80000,\ 286 CONFIG_SYS_NAND_BASE + 0xC0000} 287 #define CONFIG_SYS_MAX_NAND_DEVICE 4 288 #define CONFIG_CMD_NAND 1 289 #define CONFIG_NAND_FSL_ELBC 1 290 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 291 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 292 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 293 294 /* NAND boot: 4K NAND loader config */ 295 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 296 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 297 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 298 #define CONFIG_SYS_NAND_U_BOOT_START \ 299 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 300 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 301 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 302 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 303 304 /* NAND flash config */ 305 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 306 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 307 | BR_PS_8 /* Port Size = 8 bit */ \ 308 | BR_MS_FCM /* MSEL = FCM */ \ 309 | BR_V) /* valid */ 310 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 311 | OR_FCM_PGS /* Large Page*/ \ 312 | OR_FCM_CSCT \ 313 | OR_FCM_CST \ 314 | OR_FCM_CHT \ 315 | OR_FCM_SCY_1 \ 316 | OR_FCM_TRLX \ 317 | OR_FCM_EHTR) 318 319 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 320 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 321 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 322 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 323 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 324 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 325 | BR_PS_8 /* Port Size = 8 bit */ \ 326 | BR_MS_FCM /* MSEL = FCM */ \ 327 | BR_V) /* valid */ 328 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 329 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 330 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 331 | BR_PS_8 /* Port Size = 8 bit */ \ 332 | BR_MS_FCM /* MSEL = FCM */ \ 333 | BR_V) /* valid */ 334 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 335 336 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 337 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 338 | BR_PS_8 /* Port Size = 8 bit */ \ 339 | BR_MS_FCM /* MSEL = FCM */ \ 340 | BR_V) /* valid */ 341 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 342 343 /* Serial Port - controlled on board with jumper J8 344 * open - index 2 345 * shorted - index 1 346 */ 347 #define CONFIG_CONS_INDEX 1 348 #define CONFIG_SYS_NS16550_SERIAL 349 #define CONFIG_SYS_NS16550_REG_SIZE 1 350 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 351 #ifdef CONFIG_NAND_SPL 352 #define CONFIG_NS16550_MIN_FUNCTIONS 353 #endif 354 355 #define CONFIG_SYS_BAUDRATE_TABLE \ 356 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 357 358 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 359 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 360 361 /* I2C */ 362 #define CONFIG_SYS_I2C 363 #define CONFIG_SYS_I2C_FSL 364 #define CONFIG_SYS_FSL_I2C_SPEED 400000 365 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 366 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 367 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 368 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 369 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 370 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 371 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 372 373 /* 374 * I2C2 EEPROM 375 */ 376 #define CONFIG_ID_EEPROM 377 #ifdef CONFIG_ID_EEPROM 378 #define CONFIG_SYS_I2C_EEPROM_NXID 379 #endif 380 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 381 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 382 #define CONFIG_SYS_EEPROM_BUS_NUM 1 383 384 /* 385 * General PCI 386 * Memory space is mapped 1-1, but I/O space must start from 0. 387 */ 388 389 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 390 #define CONFIG_SYS_PCIE3_NAME "ULI" 391 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 392 #ifdef CONFIG_PHYS_64BIT 393 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 394 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 395 #else 396 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 397 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 398 #endif 399 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 400 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 401 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 402 #ifdef CONFIG_PHYS_64BIT 403 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 404 #else 405 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 406 #endif 407 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 408 409 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 410 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 411 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 412 #ifdef CONFIG_PHYS_64BIT 413 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 414 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 415 #else 416 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 417 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 418 #endif 419 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 420 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 421 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 422 #ifdef CONFIG_PHYS_64BIT 423 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 424 #else 425 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 426 #endif 427 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 428 429 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 430 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 431 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 432 #ifdef CONFIG_PHYS_64BIT 433 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 434 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 435 #else 436 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 437 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 438 #endif 439 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 440 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 441 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 442 #ifdef CONFIG_PHYS_64BIT 443 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 444 #else 445 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 446 #endif 447 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 448 449 #if defined(CONFIG_PCI) 450 451 /*PCIE video card used*/ 452 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 453 454 /* video */ 455 456 #if defined(CONFIG_VIDEO) 457 #define CONFIG_BIOSEMU 458 #define CONFIG_ATI_RADEON_FB 459 #define CONFIG_VIDEO_LOGO 460 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 461 #endif 462 463 #undef CONFIG_EEPRO100 464 #undef CONFIG_TULIP 465 466 #ifndef CONFIG_PCI_PNP 467 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 468 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 469 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 470 #endif 471 472 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 473 #define CONFIG_SCSI_AHCI 474 475 #ifdef CONFIG_SCSI_AHCI 476 #define CONFIG_LIBATA 477 #define CONFIG_SATA_ULI5288 478 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 479 #define CONFIG_SYS_SCSI_MAX_LUN 1 480 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 481 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 482 #endif /* SCSI */ 483 484 #endif /* CONFIG_PCI */ 485 486 #if defined(CONFIG_TSEC_ENET) 487 488 #define CONFIG_MII 1 /* MII PHY management */ 489 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 490 #define CONFIG_TSEC1 1 491 #define CONFIG_TSEC1_NAME "eTSEC1" 492 #define CONFIG_TSEC2 1 493 #define CONFIG_TSEC2_NAME "eTSEC2" 494 #define CONFIG_TSEC3 1 495 #define CONFIG_TSEC3_NAME "eTSEC3" 496 #define CONFIG_TSEC4 1 497 #define CONFIG_TSEC4_NAME "eTSEC4" 498 499 #define CONFIG_PIXIS_SGMII_CMD 500 #define CONFIG_FSL_SGMII_RISER 1 501 #define SGMII_RISER_PHY_OFFSET 0x1c 502 503 #ifdef CONFIG_FSL_SGMII_RISER 504 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 505 #endif 506 507 #define TSEC1_PHY_ADDR 0 508 #define TSEC2_PHY_ADDR 1 509 #define TSEC3_PHY_ADDR 2 510 #define TSEC4_PHY_ADDR 3 511 512 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 513 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 514 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 515 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 516 517 #define TSEC1_PHYIDX 0 518 #define TSEC2_PHYIDX 0 519 #define TSEC3_PHYIDX 0 520 #define TSEC4_PHYIDX 0 521 522 #define CONFIG_ETHPRIME "eTSEC1" 523 524 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 525 #endif /* CONFIG_TSEC_ENET */ 526 527 /* 528 * Environment 529 */ 530 531 #if defined(CONFIG_SYS_RAMBOOT) 532 533 #else 534 #define CONFIG_ENV_IS_IN_FLASH 1 535 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 536 #define CONFIG_ENV_ADDR 0xfff80000 537 #else 538 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 539 #endif 540 #define CONFIG_ENV_SIZE 0x2000 541 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 542 #endif 543 544 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 545 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 546 547 /* 548 * Command line configuration. 549 */ 550 #define CONFIG_CMD_ERRATA 551 #define CONFIG_CMD_IRQ 552 #define CONFIG_CMD_REGINFO 553 554 #if defined(CONFIG_PCI) 555 #define CONFIG_CMD_PCI 556 #define CONFIG_SCSI 557 #endif 558 559 /* 560 * USB 561 */ 562 563 #ifdef CONFIG_USB_EHCI_HCD 564 #define CONFIG_USB_EHCI_PCI 565 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 566 #define CONFIG_PCI_EHCI_DEVICE 0 567 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 568 #endif 569 570 #undef CONFIG_WATCHDOG /* watchdog disabled */ 571 572 /* 573 * Miscellaneous configurable options 574 */ 575 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 576 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 577 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 578 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 579 #if defined(CONFIG_CMD_KGDB) 580 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 581 #else 582 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 583 #endif 584 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 585 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 586 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 587 588 /* 589 * For booting Linux, the board info and command line data 590 * have to be in the first 64 MB of memory, since this is 591 * the maximum mapped by the Linux kernel during initialization. 592 */ 593 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 594 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 595 596 #if defined(CONFIG_CMD_KGDB) 597 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 598 #endif 599 600 /* 601 * Environment Configuration 602 */ 603 #if defined(CONFIG_TSEC_ENET) 604 #define CONFIG_HAS_ETH0 605 #define CONFIG_HAS_ETH1 606 #define CONFIG_HAS_ETH2 607 #define CONFIG_HAS_ETH3 608 #endif 609 610 #define CONFIG_IPADDR 192.168.1.254 611 612 #define CONFIG_HOSTNAME unknown 613 #define CONFIG_ROOTPATH "/opt/nfsroot" 614 #define CONFIG_BOOTFILE "uImage" 615 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 616 617 #define CONFIG_SERVERIP 192.168.1.1 618 #define CONFIG_GATEWAYIP 192.168.1.1 619 #define CONFIG_NETMASK 255.255.255.0 620 621 /* default location for tftp and bootm */ 622 #define CONFIG_LOADADDR 1000000 623 624 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 625 626 #define CONFIG_EXTRA_ENV_SETTINGS \ 627 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 628 "netdev=eth0\0" \ 629 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 630 "tftpflash=tftpboot $loadaddr $uboot; " \ 631 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 632 " +$filesize; " \ 633 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 634 " +$filesize; " \ 635 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 636 " $filesize; " \ 637 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 638 " +$filesize; " \ 639 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 640 " $filesize\0" \ 641 "consoledev=ttyS0\0" \ 642 "ramdiskaddr=2000000\0" \ 643 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 644 "fdtaddr=1e00000\0" \ 645 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 646 "bdev=sda3\0" 647 648 #define CONFIG_HDBOOT \ 649 "setenv bootargs root=/dev/$bdev rw " \ 650 "console=$consoledev,$baudrate $othbootargs;" \ 651 "tftp $loadaddr $bootfile;" \ 652 "tftp $fdtaddr $fdtfile;" \ 653 "bootm $loadaddr - $fdtaddr" 654 655 #define CONFIG_NFSBOOTCOMMAND \ 656 "setenv bootargs root=/dev/nfs rw " \ 657 "nfsroot=$serverip:$rootpath " \ 658 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 659 "console=$consoledev,$baudrate $othbootargs;" \ 660 "tftp $loadaddr $bootfile;" \ 661 "tftp $fdtaddr $fdtfile;" \ 662 "bootm $loadaddr - $fdtaddr" 663 664 #define CONFIG_RAMBOOTCOMMAND \ 665 "setenv bootargs root=/dev/ram rw " \ 666 "console=$consoledev,$baudrate $othbootargs;" \ 667 "tftp $ramdiskaddr $ramdiskfile;" \ 668 "tftp $loadaddr $bootfile;" \ 669 "tftp $fdtaddr $fdtfile;" \ 670 "bootm $loadaddr $ramdiskaddr $fdtaddr" 671 672 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 673 674 #endif /* __CONFIG_H */ 675