1 /* 2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8572ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 #include "../board/freescale/common/ics307_clk.h" 18 19 #ifdef CONFIG_36BIT 20 #define CONFIG_PHYS_64BIT 21 #endif 22 23 #ifndef CONFIG_SYS_TEXT_BASE 24 #define CONFIG_SYS_TEXT_BASE 0xeff40000 25 #endif 26 27 #ifndef CONFIG_RESET_VECTOR_ADDRESS 28 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 29 #endif 30 31 #ifndef CONFIG_SYS_MONITOR_BASE 32 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 33 #endif 34 35 /* High Level Configuration Options */ 36 #define CONFIG_BOOKE 1 /* BOOKE */ 37 #define CONFIG_E500 1 /* BOOKE e500 family */ 38 #define CONFIG_MPC8572 1 39 #define CONFIG_MPC8572DS 1 40 #define CONFIG_MP 1 /* support multiple processors */ 41 42 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 43 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 44 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 45 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 46 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 47 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 48 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 49 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 50 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 51 52 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 53 54 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 55 #define CONFIG_ENV_OVERWRITE 56 57 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 58 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 59 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 60 61 /* 62 * These can be toggled for performance analysis, otherwise use default. 63 */ 64 #define CONFIG_L2_CACHE /* toggle L2 cache */ 65 #define CONFIG_BTB /* toggle branch predition */ 66 67 #define CONFIG_ENABLE_36BIT_PHYS 1 68 69 #ifdef CONFIG_PHYS_64BIT 70 #define CONFIG_ADDR_MAP 1 71 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 72 #endif 73 74 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 75 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 76 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 77 78 /* 79 * Config the L2 Cache as L2 SRAM 80 */ 81 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 82 #ifdef CONFIG_PHYS_64BIT 83 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 84 #else 85 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 86 #endif 87 #define CONFIG_SYS_L2_SIZE (512 << 10) 88 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 89 90 #define CONFIG_SYS_CCSRBAR 0xffe00000 91 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 92 93 #if defined(CONFIG_NAND_SPL) 94 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 95 #endif 96 97 /* DDR Setup */ 98 #define CONFIG_VERY_BIG_RAM 99 #define CONFIG_SYS_FSL_DDR2 100 #undef CONFIG_FSL_DDR_INTERACTIVE 101 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 102 #define CONFIG_DDR_SPD 103 104 #define CONFIG_DDR_ECC 105 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 106 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 107 108 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 109 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 110 111 #define CONFIG_NUM_DDR_CONTROLLERS 2 112 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 113 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 114 115 /* I2C addresses of SPD EEPROMs */ 116 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 117 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 118 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 119 120 /* These are used when DDR doesn't use SPD. */ 121 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 122 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 123 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 124 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 125 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 126 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 127 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 128 #define CONFIG_SYS_DDR_MODE_1 0x00440462 129 #define CONFIG_SYS_DDR_MODE_2 0x00000000 130 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 131 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 132 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 133 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 134 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 135 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 136 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 137 138 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 139 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 140 #define CONFIG_SYS_DDR_SBE 0x00010000 141 142 /* 143 * Make sure required options are set 144 */ 145 #ifndef CONFIG_SPD_EEPROM 146 #error ("CONFIG_SPD_EEPROM is required") 147 #endif 148 149 #undef CONFIG_CLOCKS_IN_MHZ 150 151 /* 152 * Memory map 153 * 154 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 155 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 156 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 157 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 158 * 159 * Localbus cacheable (TBD) 160 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 161 * 162 * Localbus non-cacheable 163 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 164 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 165 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 166 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 167 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 168 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 169 */ 170 171 /* 172 * Local Bus Definitions 173 */ 174 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 175 #ifdef CONFIG_PHYS_64BIT 176 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 177 #else 178 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 179 #endif 180 181 182 #define CONFIG_FLASH_BR_PRELIM \ 183 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 184 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 185 186 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 187 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 188 189 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 190 #define CONFIG_SYS_FLASH_QUIET_TEST 191 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 192 193 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 194 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 195 #undef CONFIG_SYS_FLASH_CHECKSUM 196 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 197 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 198 199 #undef CONFIG_SYS_RAMBOOT 200 201 #define CONFIG_FLASH_CFI_DRIVER 202 #define CONFIG_SYS_FLASH_CFI 203 #define CONFIG_SYS_FLASH_EMPTY_INFO 204 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 205 206 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 207 208 #define CONFIG_HWCONFIG /* enable hwconfig */ 209 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 210 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 211 #ifdef CONFIG_PHYS_64BIT 212 #define PIXIS_BASE_PHYS 0xfffdf0000ull 213 #else 214 #define PIXIS_BASE_PHYS PIXIS_BASE 215 #endif 216 217 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 218 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 219 220 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 221 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 222 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 223 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 224 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 225 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 226 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 227 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 228 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 229 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 230 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 231 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 232 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 233 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 234 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 235 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 236 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 237 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 238 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 239 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 240 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 241 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 242 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 243 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 244 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 245 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 246 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 247 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 248 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 249 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 250 #define PIXIS_LED 0x25 /* LED Register */ 251 252 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 253 254 /* old pixis referenced names */ 255 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 256 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 257 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 258 #define PIXIS_VSPEED2_TSEC1SER 0x8 259 #define PIXIS_VSPEED2_TSEC2SER 0x4 260 #define PIXIS_VSPEED2_TSEC3SER 0x2 261 #define PIXIS_VSPEED2_TSEC4SER 0x1 262 #define PIXIS_VCFGEN1_TSEC1SER 0x20 263 #define PIXIS_VCFGEN1_TSEC2SER 0x20 264 #define PIXIS_VCFGEN1_TSEC3SER 0x20 265 #define PIXIS_VCFGEN1_TSEC4SER 0x20 266 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 267 | PIXIS_VSPEED2_TSEC2SER \ 268 | PIXIS_VSPEED2_TSEC3SER \ 269 | PIXIS_VSPEED2_TSEC4SER) 270 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 271 | PIXIS_VCFGEN1_TSEC2SER \ 272 | PIXIS_VCFGEN1_TSEC3SER \ 273 | PIXIS_VCFGEN1_TSEC4SER) 274 275 #define CONFIG_SYS_INIT_RAM_LOCK 1 276 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 277 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 278 279 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 280 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 281 282 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 283 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 284 285 #ifndef CONFIG_NAND_SPL 286 #define CONFIG_SYS_NAND_BASE 0xffa00000 287 #ifdef CONFIG_PHYS_64BIT 288 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 289 #else 290 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 291 #endif 292 #else 293 #define CONFIG_SYS_NAND_BASE 0xfff00000 294 #ifdef CONFIG_PHYS_64BIT 295 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 296 #else 297 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 298 #endif 299 #endif 300 301 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 302 CONFIG_SYS_NAND_BASE + 0x40000, \ 303 CONFIG_SYS_NAND_BASE + 0x80000,\ 304 CONFIG_SYS_NAND_BASE + 0xC0000} 305 #define CONFIG_SYS_MAX_NAND_DEVICE 4 306 #define CONFIG_MTD_NAND_VERIFY_WRITE 307 #define CONFIG_CMD_NAND 1 308 #define CONFIG_NAND_FSL_ELBC 1 309 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 310 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 311 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 312 313 /* NAND boot: 4K NAND loader config */ 314 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 315 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 316 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 317 #define CONFIG_SYS_NAND_U_BOOT_START \ 318 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 319 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 320 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 321 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 322 323 324 /* NAND flash config */ 325 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 326 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 327 | BR_PS_8 /* Port Size = 8 bit */ \ 328 | BR_MS_FCM /* MSEL = FCM */ \ 329 | BR_V) /* valid */ 330 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 331 | OR_FCM_PGS /* Large Page*/ \ 332 | OR_FCM_CSCT \ 333 | OR_FCM_CST \ 334 | OR_FCM_CHT \ 335 | OR_FCM_SCY_1 \ 336 | OR_FCM_TRLX \ 337 | OR_FCM_EHTR) 338 339 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 340 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 341 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 342 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 343 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 344 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 345 | BR_PS_8 /* Port Size = 8 bit */ \ 346 | BR_MS_FCM /* MSEL = FCM */ \ 347 | BR_V) /* valid */ 348 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 349 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 350 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 351 | BR_PS_8 /* Port Size = 8 bit */ \ 352 | BR_MS_FCM /* MSEL = FCM */ \ 353 | BR_V) /* valid */ 354 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 355 356 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 357 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 358 | BR_PS_8 /* Port Size = 8 bit */ \ 359 | BR_MS_FCM /* MSEL = FCM */ \ 360 | BR_V) /* valid */ 361 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 362 363 364 /* Serial Port - controlled on board with jumper J8 365 * open - index 2 366 * shorted - index 1 367 */ 368 #define CONFIG_CONS_INDEX 1 369 #define CONFIG_SYS_NS16550 370 #define CONFIG_SYS_NS16550_SERIAL 371 #define CONFIG_SYS_NS16550_REG_SIZE 1 372 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 373 #ifdef CONFIG_NAND_SPL 374 #define CONFIG_NS16550_MIN_FUNCTIONS 375 #endif 376 377 #define CONFIG_SYS_BAUDRATE_TABLE \ 378 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 379 380 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 381 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 382 383 /* Use the HUSH parser */ 384 #define CONFIG_SYS_HUSH_PARSER 385 386 /* 387 * Pass open firmware flat tree 388 */ 389 #define CONFIG_OF_LIBFDT 1 390 #define CONFIG_OF_BOARD_SETUP 1 391 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 392 393 /* new uImage format support */ 394 #define CONFIG_FIT 1 395 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 396 397 /* I2C */ 398 #define CONFIG_SYS_I2C 399 #define CONFIG_SYS_I2C_FSL 400 #define CONFIG_SYS_FSL_I2C_SPEED 400000 401 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 402 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 403 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 404 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 405 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 406 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 407 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 408 409 /* 410 * I2C2 EEPROM 411 */ 412 #define CONFIG_ID_EEPROM 413 #ifdef CONFIG_ID_EEPROM 414 #define CONFIG_SYS_I2C_EEPROM_NXID 415 #endif 416 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 417 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 418 #define CONFIG_SYS_EEPROM_BUS_NUM 1 419 420 /* 421 * General PCI 422 * Memory space is mapped 1-1, but I/O space must start from 0. 423 */ 424 425 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 426 #define CONFIG_SYS_PCIE3_NAME "ULI" 427 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 428 #ifdef CONFIG_PHYS_64BIT 429 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 430 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 431 #else 432 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 433 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 434 #endif 435 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 436 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 437 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 438 #ifdef CONFIG_PHYS_64BIT 439 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 440 #else 441 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 442 #endif 443 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 444 445 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 446 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 447 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 448 #ifdef CONFIG_PHYS_64BIT 449 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 450 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 451 #else 452 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 453 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 454 #endif 455 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 456 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 457 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 458 #ifdef CONFIG_PHYS_64BIT 459 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 460 #else 461 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 462 #endif 463 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 464 465 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 466 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 467 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 470 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 471 #else 472 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 473 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 474 #endif 475 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 476 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 477 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 478 #ifdef CONFIG_PHYS_64BIT 479 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 480 #else 481 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 482 #endif 483 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 484 485 #if defined(CONFIG_PCI) 486 487 /*PCIE video card used*/ 488 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 489 490 /* video */ 491 #define CONFIG_VIDEO 492 493 #if defined(CONFIG_VIDEO) 494 #define CONFIG_BIOSEMU 495 #define CONFIG_CFB_CONSOLE 496 #define CONFIG_VIDEO_SW_CURSOR 497 #define CONFIG_VGA_AS_SINGLE_DEVICE 498 #define CONFIG_ATI_RADEON_FB 499 #define CONFIG_VIDEO_LOGO 500 /*#define CONFIG_CONSOLE_CURSOR*/ 501 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 502 #endif 503 504 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 505 506 #undef CONFIG_EEPRO100 507 #undef CONFIG_TULIP 508 #undef CONFIG_RTL8139 509 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 510 511 #ifndef CONFIG_PCI_PNP 512 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 513 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 514 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 515 #endif 516 517 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 518 #define CONFIG_DOS_PARTITION 519 #define CONFIG_SCSI_AHCI 520 521 #ifdef CONFIG_SCSI_AHCI 522 #define CONFIG_LIBATA 523 #define CONFIG_SATA_ULI5288 524 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 525 #define CONFIG_SYS_SCSI_MAX_LUN 1 526 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 527 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 528 #endif /* SCSI */ 529 530 #endif /* CONFIG_PCI */ 531 532 533 #if defined(CONFIG_TSEC_ENET) 534 535 #define CONFIG_MII 1 /* MII PHY management */ 536 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 537 #define CONFIG_TSEC1 1 538 #define CONFIG_TSEC1_NAME "eTSEC1" 539 #define CONFIG_TSEC2 1 540 #define CONFIG_TSEC2_NAME "eTSEC2" 541 #define CONFIG_TSEC3 1 542 #define CONFIG_TSEC3_NAME "eTSEC3" 543 #define CONFIG_TSEC4 1 544 #define CONFIG_TSEC4_NAME "eTSEC4" 545 546 #define CONFIG_PIXIS_SGMII_CMD 547 #define CONFIG_FSL_SGMII_RISER 1 548 #define SGMII_RISER_PHY_OFFSET 0x1c 549 550 #ifdef CONFIG_FSL_SGMII_RISER 551 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 552 #endif 553 554 #define TSEC1_PHY_ADDR 0 555 #define TSEC2_PHY_ADDR 1 556 #define TSEC3_PHY_ADDR 2 557 #define TSEC4_PHY_ADDR 3 558 559 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 560 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 561 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 562 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 563 564 #define TSEC1_PHYIDX 0 565 #define TSEC2_PHYIDX 0 566 #define TSEC3_PHYIDX 0 567 #define TSEC4_PHYIDX 0 568 569 #define CONFIG_ETHPRIME "eTSEC1" 570 571 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 572 #endif /* CONFIG_TSEC_ENET */ 573 574 /* 575 * Environment 576 */ 577 578 #if defined(CONFIG_SYS_RAMBOOT) 579 580 #else 581 #define CONFIG_ENV_IS_IN_FLASH 1 582 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 583 #define CONFIG_ENV_ADDR 0xfff80000 584 #else 585 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 586 #endif 587 #define CONFIG_ENV_SIZE 0x2000 588 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 589 #endif 590 591 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 592 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 593 594 /* 595 * Command line configuration. 596 */ 597 #include <config_cmd_default.h> 598 599 #define CONFIG_CMD_ERRATA 600 #define CONFIG_CMD_IRQ 601 #define CONFIG_CMD_PING 602 #define CONFIG_CMD_I2C 603 #define CONFIG_CMD_MII 604 #define CONFIG_CMD_ELF 605 #define CONFIG_CMD_SETEXPR 606 #define CONFIG_CMD_REGINFO 607 608 #if defined(CONFIG_PCI) 609 #define CONFIG_CMD_PCI 610 #define CONFIG_CMD_NET 611 #define CONFIG_CMD_SCSI 612 #define CONFIG_CMD_EXT2 613 #endif 614 615 /* 616 * USB 617 */ 618 #define CONFIG_USB_EHCI 619 620 #ifdef CONFIG_USB_EHCI 621 #define CONFIG_CMD_USB 622 #define CONFIG_USB_EHCI_PCI 623 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 624 #define CONFIG_USB_STORAGE 625 #define CONFIG_PCI_EHCI_DEVICE 0 626 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 627 #endif 628 629 #undef CONFIG_WATCHDOG /* watchdog disabled */ 630 631 /* 632 * Miscellaneous configurable options 633 */ 634 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 635 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 636 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 637 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 638 #if defined(CONFIG_CMD_KGDB) 639 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 640 #else 641 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 642 #endif 643 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 644 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 645 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 646 647 /* 648 * For booting Linux, the board info and command line data 649 * have to be in the first 64 MB of memory, since this is 650 * the maximum mapped by the Linux kernel during initialization. 651 */ 652 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 653 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 654 655 #if defined(CONFIG_CMD_KGDB) 656 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 657 #endif 658 659 /* 660 * Environment Configuration 661 */ 662 663 /* The mac addresses for all ethernet interface */ 664 #if defined(CONFIG_TSEC_ENET) 665 #define CONFIG_HAS_ETH0 666 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 667 #define CONFIG_HAS_ETH1 668 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 669 #define CONFIG_HAS_ETH2 670 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 671 #define CONFIG_HAS_ETH3 672 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 673 #endif 674 675 #define CONFIG_IPADDR 192.168.1.254 676 677 #define CONFIG_HOSTNAME unknown 678 #define CONFIG_ROOTPATH "/opt/nfsroot" 679 #define CONFIG_BOOTFILE "uImage" 680 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 681 682 #define CONFIG_SERVERIP 192.168.1.1 683 #define CONFIG_GATEWAYIP 192.168.1.1 684 #define CONFIG_NETMASK 255.255.255.0 685 686 /* default location for tftp and bootm */ 687 #define CONFIG_LOADADDR 1000000 688 689 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 690 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 691 692 #define CONFIG_BAUDRATE 115200 693 694 #define CONFIG_EXTRA_ENV_SETTINGS \ 695 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 696 "netdev=eth0\0" \ 697 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 698 "tftpflash=tftpboot $loadaddr $uboot; " \ 699 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 700 " +$filesize; " \ 701 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 702 " +$filesize; " \ 703 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 704 " $filesize; " \ 705 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 706 " +$filesize; " \ 707 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 708 " $filesize\0" \ 709 "consoledev=ttyS0\0" \ 710 "ramdiskaddr=2000000\0" \ 711 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 712 "fdtaddr=c00000\0" \ 713 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 714 "bdev=sda3\0" 715 716 #define CONFIG_HDBOOT \ 717 "setenv bootargs root=/dev/$bdev rw " \ 718 "console=$consoledev,$baudrate $othbootargs;" \ 719 "tftp $loadaddr $bootfile;" \ 720 "tftp $fdtaddr $fdtfile;" \ 721 "bootm $loadaddr - $fdtaddr" 722 723 #define CONFIG_NFSBOOTCOMMAND \ 724 "setenv bootargs root=/dev/nfs rw " \ 725 "nfsroot=$serverip:$rootpath " \ 726 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 727 "console=$consoledev,$baudrate $othbootargs;" \ 728 "tftp $loadaddr $bootfile;" \ 729 "tftp $fdtaddr $fdtfile;" \ 730 "bootm $loadaddr - $fdtaddr" 731 732 #define CONFIG_RAMBOOTCOMMAND \ 733 "setenv bootargs root=/dev/ram rw " \ 734 "console=$consoledev,$baudrate $othbootargs;" \ 735 "tftp $ramdiskaddr $ramdiskfile;" \ 736 "tftp $loadaddr $bootfile;" \ 737 "tftp $fdtaddr $fdtfile;" \ 738 "bootm $loadaddr $ramdiskaddr $fdtaddr" 739 740 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 741 742 #endif /* __CONFIG_H */ 743