1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * mpc8572ds board configuration file 8 * 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifndef CONFIG_RESET_VECTOR_ADDRESS 16 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 17 #endif 18 19 #ifndef CONFIG_SYS_MONITOR_BASE 20 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 21 #endif 22 23 /* High Level Configuration Options */ 24 #define CONFIG_MP 1 /* support multiple processors */ 25 26 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 27 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 28 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 29 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 30 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 31 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 32 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 33 34 #define CONFIG_ENV_OVERWRITE 35 36 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 37 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 38 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 39 40 /* 41 * These can be toggled for performance analysis, otherwise use default. 42 */ 43 #define CONFIG_L2_CACHE /* toggle L2 cache */ 44 #define CONFIG_BTB /* toggle branch predition */ 45 46 #define CONFIG_ENABLE_36BIT_PHYS 1 47 48 #ifdef CONFIG_PHYS_64BIT 49 #define CONFIG_ADDR_MAP 1 50 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 51 #endif 52 53 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 54 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 55 56 /* 57 * Config the L2 Cache as L2 SRAM 58 */ 59 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 60 #ifdef CONFIG_PHYS_64BIT 61 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 62 #else 63 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 64 #endif 65 #define CONFIG_SYS_L2_SIZE (512 << 10) 66 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 67 68 #define CONFIG_SYS_CCSRBAR 0xffe00000 69 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 70 71 #if defined(CONFIG_NAND_SPL) 72 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 73 #endif 74 75 /* DDR Setup */ 76 #define CONFIG_VERY_BIG_RAM 77 #undef CONFIG_FSL_DDR_INTERACTIVE 78 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 79 #define CONFIG_DDR_SPD 80 81 #define CONFIG_DDR_ECC 82 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 83 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 84 85 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 86 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 87 88 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 89 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 90 91 /* I2C addresses of SPD EEPROMs */ 92 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 93 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 94 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 95 96 /* These are used when DDR doesn't use SPD. */ 97 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 98 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 99 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 100 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 101 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 102 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 103 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 104 #define CONFIG_SYS_DDR_MODE_1 0x00440462 105 #define CONFIG_SYS_DDR_MODE_2 0x00000000 106 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 107 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 108 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 109 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 110 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 111 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 112 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 113 114 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 115 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 116 #define CONFIG_SYS_DDR_SBE 0x00010000 117 118 /* 119 * Make sure required options are set 120 */ 121 #ifndef CONFIG_SPD_EEPROM 122 #error ("CONFIG_SPD_EEPROM is required") 123 #endif 124 125 #undef CONFIG_CLOCKS_IN_MHZ 126 127 /* 128 * Memory map 129 * 130 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 131 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 132 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 133 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 134 * 135 * Localbus cacheable (TBD) 136 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 137 * 138 * Localbus non-cacheable 139 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 140 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 141 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 142 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 143 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 144 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 145 */ 146 147 /* 148 * Local Bus Definitions 149 */ 150 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 151 #ifdef CONFIG_PHYS_64BIT 152 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 153 #else 154 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 155 #endif 156 157 #define CONFIG_FLASH_BR_PRELIM \ 158 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 159 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 160 161 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 162 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 163 164 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 165 #define CONFIG_SYS_FLASH_QUIET_TEST 166 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 167 168 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 169 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 170 #undef CONFIG_SYS_FLASH_CHECKSUM 171 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 172 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 173 174 #undef CONFIG_SYS_RAMBOOT 175 176 #define CONFIG_FLASH_CFI_DRIVER 177 #define CONFIG_SYS_FLASH_CFI 178 #define CONFIG_SYS_FLASH_EMPTY_INFO 179 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 180 181 #define CONFIG_HWCONFIG /* enable hwconfig */ 182 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 183 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 184 #ifdef CONFIG_PHYS_64BIT 185 #define PIXIS_BASE_PHYS 0xfffdf0000ull 186 #else 187 #define PIXIS_BASE_PHYS PIXIS_BASE 188 #endif 189 190 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 191 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 192 193 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 194 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 195 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 196 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 197 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 198 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 199 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 200 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 201 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 202 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 203 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 204 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 205 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 206 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 207 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 208 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 209 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 210 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 211 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 212 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 213 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 214 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 215 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 216 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 217 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 218 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 219 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 220 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 221 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 222 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 223 #define PIXIS_LED 0x25 /* LED Register */ 224 225 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 226 227 /* old pixis referenced names */ 228 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 229 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 230 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 231 #define PIXIS_VSPEED2_TSEC1SER 0x8 232 #define PIXIS_VSPEED2_TSEC2SER 0x4 233 #define PIXIS_VSPEED2_TSEC3SER 0x2 234 #define PIXIS_VSPEED2_TSEC4SER 0x1 235 #define PIXIS_VCFGEN1_TSEC1SER 0x20 236 #define PIXIS_VCFGEN1_TSEC2SER 0x20 237 #define PIXIS_VCFGEN1_TSEC3SER 0x20 238 #define PIXIS_VCFGEN1_TSEC4SER 0x20 239 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 240 | PIXIS_VSPEED2_TSEC2SER \ 241 | PIXIS_VSPEED2_TSEC3SER \ 242 | PIXIS_VSPEED2_TSEC4SER) 243 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 244 | PIXIS_VCFGEN1_TSEC2SER \ 245 | PIXIS_VCFGEN1_TSEC3SER \ 246 | PIXIS_VCFGEN1_TSEC4SER) 247 248 #define CONFIG_SYS_INIT_RAM_LOCK 1 249 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 250 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 251 252 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 253 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 254 255 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 256 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 257 258 #ifndef CONFIG_NAND_SPL 259 #define CONFIG_SYS_NAND_BASE 0xffa00000 260 #ifdef CONFIG_PHYS_64BIT 261 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 262 #else 263 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 264 #endif 265 #else 266 #define CONFIG_SYS_NAND_BASE 0xfff00000 267 #ifdef CONFIG_PHYS_64BIT 268 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 269 #else 270 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 271 #endif 272 #endif 273 274 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 275 CONFIG_SYS_NAND_BASE + 0x40000, \ 276 CONFIG_SYS_NAND_BASE + 0x80000,\ 277 CONFIG_SYS_NAND_BASE + 0xC0000} 278 #define CONFIG_SYS_MAX_NAND_DEVICE 4 279 #define CONFIG_NAND_FSL_ELBC 1 280 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 281 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 282 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 283 284 /* NAND boot: 4K NAND loader config */ 285 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 286 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 287 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 288 #define CONFIG_SYS_NAND_U_BOOT_START \ 289 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 290 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 291 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 292 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 293 294 /* NAND flash config */ 295 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 296 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 297 | BR_PS_8 /* Port Size = 8 bit */ \ 298 | BR_MS_FCM /* MSEL = FCM */ \ 299 | BR_V) /* valid */ 300 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 301 | OR_FCM_PGS /* Large Page*/ \ 302 | OR_FCM_CSCT \ 303 | OR_FCM_CST \ 304 | OR_FCM_CHT \ 305 | OR_FCM_SCY_1 \ 306 | OR_FCM_TRLX \ 307 | OR_FCM_EHTR) 308 309 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 310 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 311 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 312 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 313 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 314 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 315 | BR_PS_8 /* Port Size = 8 bit */ \ 316 | BR_MS_FCM /* MSEL = FCM */ \ 317 | BR_V) /* valid */ 318 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 319 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 320 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 321 | BR_PS_8 /* Port Size = 8 bit */ \ 322 | BR_MS_FCM /* MSEL = FCM */ \ 323 | BR_V) /* valid */ 324 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 325 326 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 327 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 328 | BR_PS_8 /* Port Size = 8 bit */ \ 329 | BR_MS_FCM /* MSEL = FCM */ \ 330 | BR_V) /* valid */ 331 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 332 333 /* Serial Port - controlled on board with jumper J8 334 * open - index 2 335 * shorted - index 1 336 */ 337 #define CONFIG_SYS_NS16550_SERIAL 338 #define CONFIG_SYS_NS16550_REG_SIZE 1 339 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 340 #ifdef CONFIG_NAND_SPL 341 #define CONFIG_NS16550_MIN_FUNCTIONS 342 #endif 343 344 #define CONFIG_SYS_BAUDRATE_TABLE \ 345 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 346 347 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 348 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 349 350 /* I2C */ 351 #define CONFIG_SYS_I2C 352 #define CONFIG_SYS_I2C_FSL 353 #define CONFIG_SYS_FSL_I2C_SPEED 400000 354 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 355 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 356 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 357 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 358 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 359 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 360 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 361 362 /* 363 * I2C2 EEPROM 364 */ 365 #define CONFIG_ID_EEPROM 366 #ifdef CONFIG_ID_EEPROM 367 #define CONFIG_SYS_I2C_EEPROM_NXID 368 #endif 369 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 370 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 371 #define CONFIG_SYS_EEPROM_BUS_NUM 1 372 373 /* 374 * General PCI 375 * Memory space is mapped 1-1, but I/O space must start from 0. 376 */ 377 378 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 379 #define CONFIG_SYS_PCIE3_NAME "ULI" 380 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 381 #ifdef CONFIG_PHYS_64BIT 382 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 383 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 384 #else 385 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 386 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 387 #endif 388 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 389 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 390 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 391 #ifdef CONFIG_PHYS_64BIT 392 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 393 #else 394 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 395 #endif 396 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 397 398 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 399 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 400 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 401 #ifdef CONFIG_PHYS_64BIT 402 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 403 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 404 #else 405 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 406 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 407 #endif 408 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 409 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 410 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 411 #ifdef CONFIG_PHYS_64BIT 412 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 413 #else 414 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 415 #endif 416 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 417 418 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 419 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 420 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 421 #ifdef CONFIG_PHYS_64BIT 422 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 423 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 424 #else 425 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 426 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 427 #endif 428 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 429 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 430 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 431 #ifdef CONFIG_PHYS_64BIT 432 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 433 #else 434 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 435 #endif 436 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 437 438 #if defined(CONFIG_PCI) 439 440 /*PCIE video card used*/ 441 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 442 443 /* video */ 444 445 #if defined(CONFIG_VIDEO) 446 #define CONFIG_BIOSEMU 447 #define CONFIG_ATI_RADEON_FB 448 #define CONFIG_VIDEO_LOGO 449 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 450 #endif 451 452 #undef CONFIG_EEPRO100 453 #undef CONFIG_TULIP 454 455 #ifndef CONFIG_PCI_PNP 456 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 457 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 458 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 459 #endif 460 461 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 462 463 #ifdef CONFIG_SCSI_AHCI 464 #define CONFIG_SATA_ULI5288 465 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 466 #define CONFIG_SYS_SCSI_MAX_LUN 1 467 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 468 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 469 #endif /* SCSI */ 470 471 #endif /* CONFIG_PCI */ 472 473 #if defined(CONFIG_TSEC_ENET) 474 475 #define CONFIG_MII 1 /* MII PHY management */ 476 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 477 #define CONFIG_TSEC1 1 478 #define CONFIG_TSEC1_NAME "eTSEC1" 479 #define CONFIG_TSEC2 1 480 #define CONFIG_TSEC2_NAME "eTSEC2" 481 #define CONFIG_TSEC3 1 482 #define CONFIG_TSEC3_NAME "eTSEC3" 483 #define CONFIG_TSEC4 1 484 #define CONFIG_TSEC4_NAME "eTSEC4" 485 486 #define CONFIG_PIXIS_SGMII_CMD 487 #define CONFIG_FSL_SGMII_RISER 1 488 #define SGMII_RISER_PHY_OFFSET 0x1c 489 490 #ifdef CONFIG_FSL_SGMII_RISER 491 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 492 #endif 493 494 #define TSEC1_PHY_ADDR 0 495 #define TSEC2_PHY_ADDR 1 496 #define TSEC3_PHY_ADDR 2 497 #define TSEC4_PHY_ADDR 3 498 499 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 500 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 501 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 502 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 503 504 #define TSEC1_PHYIDX 0 505 #define TSEC2_PHYIDX 0 506 #define TSEC3_PHYIDX 0 507 #define TSEC4_PHYIDX 0 508 509 #define CONFIG_ETHPRIME "eTSEC1" 510 #endif /* CONFIG_TSEC_ENET */ 511 512 /* 513 * Environment 514 */ 515 516 #if defined(CONFIG_SYS_RAMBOOT) 517 518 #else 519 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 520 #define CONFIG_ENV_ADDR 0xfff80000 521 #else 522 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 523 #endif 524 #define CONFIG_ENV_SIZE 0x2000 525 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 526 #endif 527 528 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 529 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 530 531 /* 532 * USB 533 */ 534 535 #ifdef CONFIG_USB_EHCI_HCD 536 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 537 #define CONFIG_PCI_EHCI_DEVICE 0 538 #endif 539 540 #undef CONFIG_WATCHDOG /* watchdog disabled */ 541 542 /* 543 * Miscellaneous configurable options 544 */ 545 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 546 547 /* 548 * For booting Linux, the board info and command line data 549 * have to be in the first 64 MB of memory, since this is 550 * the maximum mapped by the Linux kernel during initialization. 551 */ 552 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 553 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 554 555 #if defined(CONFIG_CMD_KGDB) 556 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 557 #endif 558 559 /* 560 * Environment Configuration 561 */ 562 #if defined(CONFIG_TSEC_ENET) 563 #define CONFIG_HAS_ETH0 564 #define CONFIG_HAS_ETH1 565 #define CONFIG_HAS_ETH2 566 #define CONFIG_HAS_ETH3 567 #endif 568 569 #define CONFIG_IPADDR 192.168.1.254 570 571 #define CONFIG_HOSTNAME "unknown" 572 #define CONFIG_ROOTPATH "/opt/nfsroot" 573 #define CONFIG_BOOTFILE "uImage" 574 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 575 576 #define CONFIG_SERVERIP 192.168.1.1 577 #define CONFIG_GATEWAYIP 192.168.1.1 578 #define CONFIG_NETMASK 255.255.255.0 579 580 /* default location for tftp and bootm */ 581 #define CONFIG_LOADADDR 1000000 582 583 #define CONFIG_EXTRA_ENV_SETTINGS \ 584 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 585 "netdev=eth0\0" \ 586 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 587 "tftpflash=tftpboot $loadaddr $uboot; " \ 588 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 589 " +$filesize; " \ 590 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 591 " +$filesize; " \ 592 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 593 " $filesize; " \ 594 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 595 " +$filesize; " \ 596 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 597 " $filesize\0" \ 598 "consoledev=ttyS0\0" \ 599 "ramdiskaddr=2000000\0" \ 600 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 601 "fdtaddr=1e00000\0" \ 602 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 603 "bdev=sda3\0" 604 605 #define CONFIG_HDBOOT \ 606 "setenv bootargs root=/dev/$bdev rw " \ 607 "console=$consoledev,$baudrate $othbootargs;" \ 608 "tftp $loadaddr $bootfile;" \ 609 "tftp $fdtaddr $fdtfile;" \ 610 "bootm $loadaddr - $fdtaddr" 611 612 #define CONFIG_NFSBOOTCOMMAND \ 613 "setenv bootargs root=/dev/nfs rw " \ 614 "nfsroot=$serverip:$rootpath " \ 615 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 616 "console=$consoledev,$baudrate $othbootargs;" \ 617 "tftp $loadaddr $bootfile;" \ 618 "tftp $fdtaddr $fdtfile;" \ 619 "bootm $loadaddr - $fdtaddr" 620 621 #define CONFIG_RAMBOOTCOMMAND \ 622 "setenv bootargs root=/dev/ram rw " \ 623 "console=$consoledev,$baudrate $othbootargs;" \ 624 "tftp $ramdiskaddr $ramdiskfile;" \ 625 "tftp $loadaddr $bootfile;" \ 626 "tftp $fdtaddr $fdtfile;" \ 627 "bootm $loadaddr $ramdiskaddr $fdtaddr" 628 629 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 630 631 #endif /* __CONFIG_H */ 632