1 /* 2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8572ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifndef CONFIG_RESET_VECTOR_ADDRESS 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 18 #endif 19 20 #ifndef CONFIG_SYS_MONITOR_BASE 21 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 22 #endif 23 24 /* High Level Configuration Options */ 25 #define CONFIG_MP 1 /* support multiple processors */ 26 27 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 28 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 29 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 30 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 31 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 32 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 34 35 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 36 #define CONFIG_ENV_OVERWRITE 37 38 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 39 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 40 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 41 42 /* 43 * These can be toggled for performance analysis, otherwise use default. 44 */ 45 #define CONFIG_L2_CACHE /* toggle L2 cache */ 46 #define CONFIG_BTB /* toggle branch predition */ 47 48 #define CONFIG_ENABLE_36BIT_PHYS 1 49 50 #ifdef CONFIG_PHYS_64BIT 51 #define CONFIG_ADDR_MAP 1 52 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 53 #endif 54 55 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 56 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 57 58 /* 59 * Config the L2 Cache as L2 SRAM 60 */ 61 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 62 #ifdef CONFIG_PHYS_64BIT 63 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 64 #else 65 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 66 #endif 67 #define CONFIG_SYS_L2_SIZE (512 << 10) 68 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 69 70 #define CONFIG_SYS_CCSRBAR 0xffe00000 71 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 72 73 #if defined(CONFIG_NAND_SPL) 74 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 75 #endif 76 77 /* DDR Setup */ 78 #define CONFIG_VERY_BIG_RAM 79 #undef CONFIG_FSL_DDR_INTERACTIVE 80 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 81 #define CONFIG_DDR_SPD 82 83 #define CONFIG_DDR_ECC 84 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 85 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 86 87 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 88 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 89 90 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 91 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 92 93 /* I2C addresses of SPD EEPROMs */ 94 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 95 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 96 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 97 98 /* These are used when DDR doesn't use SPD. */ 99 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 100 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 101 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 102 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 103 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 104 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 105 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 106 #define CONFIG_SYS_DDR_MODE_1 0x00440462 107 #define CONFIG_SYS_DDR_MODE_2 0x00000000 108 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 109 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 110 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 111 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 112 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 113 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 114 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 115 116 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 117 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 118 #define CONFIG_SYS_DDR_SBE 0x00010000 119 120 /* 121 * Make sure required options are set 122 */ 123 #ifndef CONFIG_SPD_EEPROM 124 #error ("CONFIG_SPD_EEPROM is required") 125 #endif 126 127 #undef CONFIG_CLOCKS_IN_MHZ 128 129 /* 130 * Memory map 131 * 132 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 133 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 134 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 135 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 136 * 137 * Localbus cacheable (TBD) 138 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 139 * 140 * Localbus non-cacheable 141 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 142 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 143 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 144 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 145 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 146 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 147 */ 148 149 /* 150 * Local Bus Definitions 151 */ 152 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 153 #ifdef CONFIG_PHYS_64BIT 154 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 155 #else 156 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 157 #endif 158 159 #define CONFIG_FLASH_BR_PRELIM \ 160 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 161 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 162 163 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 164 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 165 166 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 167 #define CONFIG_SYS_FLASH_QUIET_TEST 168 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 169 170 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 171 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 172 #undef CONFIG_SYS_FLASH_CHECKSUM 173 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 174 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 175 176 #undef CONFIG_SYS_RAMBOOT 177 178 #define CONFIG_FLASH_CFI_DRIVER 179 #define CONFIG_SYS_FLASH_CFI 180 #define CONFIG_SYS_FLASH_EMPTY_INFO 181 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 182 183 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 184 185 #define CONFIG_HWCONFIG /* enable hwconfig */ 186 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 187 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 188 #ifdef CONFIG_PHYS_64BIT 189 #define PIXIS_BASE_PHYS 0xfffdf0000ull 190 #else 191 #define PIXIS_BASE_PHYS PIXIS_BASE 192 #endif 193 194 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 195 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 196 197 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 198 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 199 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 200 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 201 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 202 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 203 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 204 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 205 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 206 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 207 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 208 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 209 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 210 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 211 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 212 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 213 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 214 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 215 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 216 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 217 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 218 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 219 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 220 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 221 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 222 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 223 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 224 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 225 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 226 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 227 #define PIXIS_LED 0x25 /* LED Register */ 228 229 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 230 231 /* old pixis referenced names */ 232 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 233 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 234 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 235 #define PIXIS_VSPEED2_TSEC1SER 0x8 236 #define PIXIS_VSPEED2_TSEC2SER 0x4 237 #define PIXIS_VSPEED2_TSEC3SER 0x2 238 #define PIXIS_VSPEED2_TSEC4SER 0x1 239 #define PIXIS_VCFGEN1_TSEC1SER 0x20 240 #define PIXIS_VCFGEN1_TSEC2SER 0x20 241 #define PIXIS_VCFGEN1_TSEC3SER 0x20 242 #define PIXIS_VCFGEN1_TSEC4SER 0x20 243 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 244 | PIXIS_VSPEED2_TSEC2SER \ 245 | PIXIS_VSPEED2_TSEC3SER \ 246 | PIXIS_VSPEED2_TSEC4SER) 247 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 248 | PIXIS_VCFGEN1_TSEC2SER \ 249 | PIXIS_VCFGEN1_TSEC3SER \ 250 | PIXIS_VCFGEN1_TSEC4SER) 251 252 #define CONFIG_SYS_INIT_RAM_LOCK 1 253 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 254 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 255 256 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 257 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 258 259 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 260 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 261 262 #ifndef CONFIG_NAND_SPL 263 #define CONFIG_SYS_NAND_BASE 0xffa00000 264 #ifdef CONFIG_PHYS_64BIT 265 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 266 #else 267 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 268 #endif 269 #else 270 #define CONFIG_SYS_NAND_BASE 0xfff00000 271 #ifdef CONFIG_PHYS_64BIT 272 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 273 #else 274 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 275 #endif 276 #endif 277 278 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 279 CONFIG_SYS_NAND_BASE + 0x40000, \ 280 CONFIG_SYS_NAND_BASE + 0x80000,\ 281 CONFIG_SYS_NAND_BASE + 0xC0000} 282 #define CONFIG_SYS_MAX_NAND_DEVICE 4 283 #define CONFIG_NAND_FSL_ELBC 1 284 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 285 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 286 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 287 288 /* NAND boot: 4K NAND loader config */ 289 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 290 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 291 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 292 #define CONFIG_SYS_NAND_U_BOOT_START \ 293 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 294 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 295 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 296 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 297 298 /* NAND flash config */ 299 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 300 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 301 | BR_PS_8 /* Port Size = 8 bit */ \ 302 | BR_MS_FCM /* MSEL = FCM */ \ 303 | BR_V) /* valid */ 304 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 305 | OR_FCM_PGS /* Large Page*/ \ 306 | OR_FCM_CSCT \ 307 | OR_FCM_CST \ 308 | OR_FCM_CHT \ 309 | OR_FCM_SCY_1 \ 310 | OR_FCM_TRLX \ 311 | OR_FCM_EHTR) 312 313 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 314 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 315 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 316 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 317 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 318 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 319 | BR_PS_8 /* Port Size = 8 bit */ \ 320 | BR_MS_FCM /* MSEL = FCM */ \ 321 | BR_V) /* valid */ 322 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 323 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 324 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 325 | BR_PS_8 /* Port Size = 8 bit */ \ 326 | BR_MS_FCM /* MSEL = FCM */ \ 327 | BR_V) /* valid */ 328 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 329 330 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 331 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 332 | BR_PS_8 /* Port Size = 8 bit */ \ 333 | BR_MS_FCM /* MSEL = FCM */ \ 334 | BR_V) /* valid */ 335 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 336 337 /* Serial Port - controlled on board with jumper J8 338 * open - index 2 339 * shorted - index 1 340 */ 341 #define CONFIG_CONS_INDEX 1 342 #define CONFIG_SYS_NS16550_SERIAL 343 #define CONFIG_SYS_NS16550_REG_SIZE 1 344 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 345 #ifdef CONFIG_NAND_SPL 346 #define CONFIG_NS16550_MIN_FUNCTIONS 347 #endif 348 349 #define CONFIG_SYS_BAUDRATE_TABLE \ 350 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 351 352 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 353 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 354 355 /* I2C */ 356 #define CONFIG_SYS_I2C 357 #define CONFIG_SYS_I2C_FSL 358 #define CONFIG_SYS_FSL_I2C_SPEED 400000 359 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 360 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 361 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 362 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 363 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 364 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 365 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 366 367 /* 368 * I2C2 EEPROM 369 */ 370 #define CONFIG_ID_EEPROM 371 #ifdef CONFIG_ID_EEPROM 372 #define CONFIG_SYS_I2C_EEPROM_NXID 373 #endif 374 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 375 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 376 #define CONFIG_SYS_EEPROM_BUS_NUM 1 377 378 /* 379 * General PCI 380 * Memory space is mapped 1-1, but I/O space must start from 0. 381 */ 382 383 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 384 #define CONFIG_SYS_PCIE3_NAME "ULI" 385 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 386 #ifdef CONFIG_PHYS_64BIT 387 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 388 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 389 #else 390 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 391 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 392 #endif 393 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 394 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 395 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 396 #ifdef CONFIG_PHYS_64BIT 397 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 398 #else 399 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 400 #endif 401 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 402 403 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 404 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 405 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 406 #ifdef CONFIG_PHYS_64BIT 407 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 408 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 409 #else 410 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 411 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 412 #endif 413 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 414 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 415 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 416 #ifdef CONFIG_PHYS_64BIT 417 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 418 #else 419 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 420 #endif 421 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 422 423 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 424 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 425 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 426 #ifdef CONFIG_PHYS_64BIT 427 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 428 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 429 #else 430 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 431 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 432 #endif 433 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 434 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 435 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 436 #ifdef CONFIG_PHYS_64BIT 437 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 438 #else 439 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 440 #endif 441 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 442 443 #if defined(CONFIG_PCI) 444 445 /*PCIE video card used*/ 446 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 447 448 /* video */ 449 450 #if defined(CONFIG_VIDEO) 451 #define CONFIG_BIOSEMU 452 #define CONFIG_ATI_RADEON_FB 453 #define CONFIG_VIDEO_LOGO 454 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 455 #endif 456 457 #undef CONFIG_EEPRO100 458 #undef CONFIG_TULIP 459 460 #ifndef CONFIG_PCI_PNP 461 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 462 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 463 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 464 #endif 465 466 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 467 468 #ifdef CONFIG_SCSI_AHCI 469 #define CONFIG_SATA_ULI5288 470 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 471 #define CONFIG_SYS_SCSI_MAX_LUN 1 472 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 473 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 474 #endif /* SCSI */ 475 476 #endif /* CONFIG_PCI */ 477 478 #if defined(CONFIG_TSEC_ENET) 479 480 #define CONFIG_MII 1 /* MII PHY management */ 481 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 482 #define CONFIG_TSEC1 1 483 #define CONFIG_TSEC1_NAME "eTSEC1" 484 #define CONFIG_TSEC2 1 485 #define CONFIG_TSEC2_NAME "eTSEC2" 486 #define CONFIG_TSEC3 1 487 #define CONFIG_TSEC3_NAME "eTSEC3" 488 #define CONFIG_TSEC4 1 489 #define CONFIG_TSEC4_NAME "eTSEC4" 490 491 #define CONFIG_PIXIS_SGMII_CMD 492 #define CONFIG_FSL_SGMII_RISER 1 493 #define SGMII_RISER_PHY_OFFSET 0x1c 494 495 #ifdef CONFIG_FSL_SGMII_RISER 496 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 497 #endif 498 499 #define TSEC1_PHY_ADDR 0 500 #define TSEC2_PHY_ADDR 1 501 #define TSEC3_PHY_ADDR 2 502 #define TSEC4_PHY_ADDR 3 503 504 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 505 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 506 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 507 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 508 509 #define TSEC1_PHYIDX 0 510 #define TSEC2_PHYIDX 0 511 #define TSEC3_PHYIDX 0 512 #define TSEC4_PHYIDX 0 513 514 #define CONFIG_ETHPRIME "eTSEC1" 515 #endif /* CONFIG_TSEC_ENET */ 516 517 /* 518 * Environment 519 */ 520 521 #if defined(CONFIG_SYS_RAMBOOT) 522 523 #else 524 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 525 #define CONFIG_ENV_ADDR 0xfff80000 526 #else 527 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 528 #endif 529 #define CONFIG_ENV_SIZE 0x2000 530 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 531 #endif 532 533 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 534 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 535 536 /* 537 * USB 538 */ 539 540 #ifdef CONFIG_USB_EHCI_HCD 541 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 542 #define CONFIG_PCI_EHCI_DEVICE 0 543 #endif 544 545 #undef CONFIG_WATCHDOG /* watchdog disabled */ 546 547 /* 548 * Miscellaneous configurable options 549 */ 550 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 551 552 /* 553 * For booting Linux, the board info and command line data 554 * have to be in the first 64 MB of memory, since this is 555 * the maximum mapped by the Linux kernel during initialization. 556 */ 557 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 558 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 559 560 #if defined(CONFIG_CMD_KGDB) 561 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 562 #endif 563 564 /* 565 * Environment Configuration 566 */ 567 #if defined(CONFIG_TSEC_ENET) 568 #define CONFIG_HAS_ETH0 569 #define CONFIG_HAS_ETH1 570 #define CONFIG_HAS_ETH2 571 #define CONFIG_HAS_ETH3 572 #endif 573 574 #define CONFIG_IPADDR 192.168.1.254 575 576 #define CONFIG_HOSTNAME unknown 577 #define CONFIG_ROOTPATH "/opt/nfsroot" 578 #define CONFIG_BOOTFILE "uImage" 579 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 580 581 #define CONFIG_SERVERIP 192.168.1.1 582 #define CONFIG_GATEWAYIP 192.168.1.1 583 #define CONFIG_NETMASK 255.255.255.0 584 585 /* default location for tftp and bootm */ 586 #define CONFIG_LOADADDR 1000000 587 588 #define CONFIG_EXTRA_ENV_SETTINGS \ 589 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 590 "netdev=eth0\0" \ 591 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 592 "tftpflash=tftpboot $loadaddr $uboot; " \ 593 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 594 " +$filesize; " \ 595 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 596 " +$filesize; " \ 597 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 598 " $filesize; " \ 599 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 600 " +$filesize; " \ 601 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 602 " $filesize\0" \ 603 "consoledev=ttyS0\0" \ 604 "ramdiskaddr=2000000\0" \ 605 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 606 "fdtaddr=1e00000\0" \ 607 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 608 "bdev=sda3\0" 609 610 #define CONFIG_HDBOOT \ 611 "setenv bootargs root=/dev/$bdev rw " \ 612 "console=$consoledev,$baudrate $othbootargs;" \ 613 "tftp $loadaddr $bootfile;" \ 614 "tftp $fdtaddr $fdtfile;" \ 615 "bootm $loadaddr - $fdtaddr" 616 617 #define CONFIG_NFSBOOTCOMMAND \ 618 "setenv bootargs root=/dev/nfs rw " \ 619 "nfsroot=$serverip:$rootpath " \ 620 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 621 "console=$consoledev,$baudrate $othbootargs;" \ 622 "tftp $loadaddr $bootfile;" \ 623 "tftp $fdtaddr $fdtfile;" \ 624 "bootm $loadaddr - $fdtaddr" 625 626 #define CONFIG_RAMBOOTCOMMAND \ 627 "setenv bootargs root=/dev/ram rw " \ 628 "console=$consoledev,$baudrate $othbootargs;" \ 629 "tftp $ramdiskaddr $ramdiskfile;" \ 630 "tftp $loadaddr $bootfile;" \ 631 "tftp $fdtaddr $fdtfile;" \ 632 "bootm $loadaddr $ramdiskaddr $fdtaddr" 633 634 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 635 636 #endif /* __CONFIG_H */ 637