1 /* 2 * Copyright 2007-2008 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8572ds board configuration file 25 * 26 */ 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #ifdef CONFIG_MK_36BIT 31 #define CONFIG_PHYS_64BIT 32 #endif 33 34 /* High Level Configuration Options */ 35 #define CONFIG_BOOKE 1 /* BOOKE */ 36 #define CONFIG_E500 1 /* BOOKE e500 family */ 37 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 38 #define CONFIG_MPC8572 1 39 #define CONFIG_MPC8572DS 1 40 #define CONFIG_MP 1 /* support multiple processors */ 41 42 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 43 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 44 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 45 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 46 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 47 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 48 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 49 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 50 51 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 52 53 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 54 #define CONFIG_ENV_OVERWRITE 55 56 /* 57 * When initializing flash, if we cannot find the manufacturer ID, 58 * assume this is the AMD flash associated with the CDS board. 59 * This allows booting from a promjet. 60 */ 61 #define CONFIG_ASSUME_AMD_FLASH 62 63 #ifndef __ASSEMBLY__ 64 extern unsigned long get_board_sys_clk(unsigned long dummy); 65 extern unsigned long get_board_ddr_clk(unsigned long dummy); 66 #endif 67 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 68 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 69 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 70 #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 71 from ICS307 instead of switches */ 72 73 /* 74 * These can be toggled for performance analysis, otherwise use default. 75 */ 76 #define CONFIG_L2_CACHE /* toggle L2 cache */ 77 #define CONFIG_BTB /* toggle branch predition */ 78 79 #define CONFIG_ENABLE_36BIT_PHYS 1 80 81 #ifdef CONFIG_PHYS_64BIT 82 #define CONFIG_ADDR_MAP 1 83 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 84 #endif 85 86 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 87 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 88 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 89 90 /* 91 * Base addresses -- Note these are effective addresses where the 92 * actual resources get mapped (not physical addresses) 93 */ 94 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 95 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 96 #ifdef CONFIG_PHYS_64BIT 97 #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 98 #else 99 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 100 #endif 101 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 102 103 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 104 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 105 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 106 107 /* DDR Setup */ 108 #define CONFIG_SYS_DDR_TLB_START 9 109 #define CONFIG_VERY_BIG_RAM 110 #define CONFIG_FSL_DDR2 111 #undef CONFIG_FSL_DDR_INTERACTIVE 112 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 113 #define CONFIG_DDR_SPD 114 #undef CONFIG_DDR_DLL 115 116 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 117 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 118 119 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 120 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 121 122 #define CONFIG_NUM_DDR_CONTROLLERS 2 123 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 124 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 125 126 /* I2C addresses of SPD EEPROMs */ 127 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 128 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 129 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 130 131 /* These are used when DDR doesn't use SPD. */ 132 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 133 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 134 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 135 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 136 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 137 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 138 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 139 #define CONFIG_SYS_DDR_MODE_1 0x00440462 140 #define CONFIG_SYS_DDR_MODE_2 0x00000000 141 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 142 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 143 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 144 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 145 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 146 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 147 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 148 149 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 150 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 151 #define CONFIG_SYS_DDR_SBE 0x00010000 152 153 /* 154 * Make sure required options are set 155 */ 156 #ifndef CONFIG_SPD_EEPROM 157 #error ("CONFIG_SPD_EEPROM is required") 158 #endif 159 160 #undef CONFIG_CLOCKS_IN_MHZ 161 162 /* 163 * Memory map 164 * 165 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 166 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 167 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 168 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 169 * 170 * Localbus cacheable (TBD) 171 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 172 * 173 * Localbus non-cacheable 174 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 175 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 176 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 177 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 178 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 179 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 180 */ 181 182 /* 183 * Local Bus Definitions 184 */ 185 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 186 #ifdef CONFIG_PHYS_64BIT 187 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 188 #else 189 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 190 #endif 191 192 #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 193 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 194 195 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 196 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 197 198 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 199 #define CONFIG_SYS_FLASH_QUIET_TEST 200 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 201 202 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 203 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 204 #undef CONFIG_SYS_FLASH_CHECKSUM 205 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 206 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 207 208 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 209 210 #define CONFIG_FLASH_CFI_DRIVER 211 #define CONFIG_SYS_FLASH_CFI 212 #define CONFIG_SYS_FLASH_EMPTY_INFO 213 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 214 215 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 216 217 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 218 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 219 #ifdef CONFIG_PHYS_64BIT 220 #define PIXIS_BASE_PHYS 0xfffdf0000ull 221 #else 222 #define PIXIS_BASE_PHYS PIXIS_BASE 223 #endif 224 225 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 226 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 227 228 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 229 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 230 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 231 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 232 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 233 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 234 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 235 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 236 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 237 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 238 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 239 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 240 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 241 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 242 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 243 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 244 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 245 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 246 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 247 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 248 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 249 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 250 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 251 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 252 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 253 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 254 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 255 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 256 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 257 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 258 #define PIXIS_LED 0x25 /* LED Register */ 259 260 /* old pixis referenced names */ 261 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 262 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 263 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 264 #define PIXIS_VSPEED2_TSEC1SER 0x8 265 #define PIXIS_VSPEED2_TSEC2SER 0x4 266 #define PIXIS_VSPEED2_TSEC3SER 0x2 267 #define PIXIS_VSPEED2_TSEC4SER 0x1 268 #define PIXIS_VCFGEN1_TSEC1SER 0x20 269 #define PIXIS_VCFGEN1_TSEC2SER 0x20 270 #define PIXIS_VCFGEN1_TSEC3SER 0x20 271 #define PIXIS_VCFGEN1_TSEC4SER 0x20 272 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 273 | PIXIS_VSPEED2_TSEC2SER \ 274 | PIXIS_VSPEED2_TSEC3SER \ 275 | PIXIS_VSPEED2_TSEC4SER) 276 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 277 | PIXIS_VCFGEN1_TSEC2SER \ 278 | PIXIS_VCFGEN1_TSEC3SER \ 279 | PIXIS_VCFGEN1_TSEC4SER) 280 281 #define CONFIG_SYS_INIT_RAM_LOCK 1 282 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 283 #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 284 285 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 286 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 287 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 288 289 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 290 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 291 292 #define CONFIG_SYS_NAND_BASE 0xffa00000 293 #ifdef CONFIG_PHYS_64BIT 294 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 295 #else 296 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 297 #endif 298 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 299 CONFIG_SYS_NAND_BASE + 0x40000, \ 300 CONFIG_SYS_NAND_BASE + 0x80000,\ 301 CONFIG_SYS_NAND_BASE + 0xC0000} 302 #define CONFIG_SYS_MAX_NAND_DEVICE 4 303 #define CONFIG_MTD_NAND_VERIFY_WRITE 304 #define CONFIG_CMD_NAND 1 305 #define CONFIG_NAND_FSL_ELBC 1 306 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 307 308 /* NAND flash config */ 309 #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 310 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 311 | BR_PS_8 /* Port Size = 8 bit */ \ 312 | BR_MS_FCM /* MSEL = FCM */ \ 313 | BR_V) /* valid */ 314 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 315 | OR_FCM_PGS /* Large Page*/ \ 316 | OR_FCM_CSCT \ 317 | OR_FCM_CST \ 318 | OR_FCM_CHT \ 319 | OR_FCM_SCY_1 \ 320 | OR_FCM_TRLX \ 321 | OR_FCM_EHTR) 322 323 #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 324 #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 325 326 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 327 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 328 | BR_PS_8 /* Port Size = 8 bit */ \ 329 | BR_MS_FCM /* MSEL = FCM */ \ 330 | BR_V) /* valid */ 331 #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 332 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 333 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 334 | BR_PS_8 /* Port Size = 8 bit */ \ 335 | BR_MS_FCM /* MSEL = FCM */ \ 336 | BR_V) /* valid */ 337 #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 338 339 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 340 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 341 | BR_PS_8 /* Port Size = 8 bit */ \ 342 | BR_MS_FCM /* MSEL = FCM */ \ 343 | BR_V) /* valid */ 344 #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 345 346 347 /* Serial Port - controlled on board with jumper J8 348 * open - index 2 349 * shorted - index 1 350 */ 351 #define CONFIG_CONS_INDEX 1 352 #undef CONFIG_SERIAL_SOFTWARE_FIFO 353 #define CONFIG_SYS_NS16550 354 #define CONFIG_SYS_NS16550_SERIAL 355 #define CONFIG_SYS_NS16550_REG_SIZE 1 356 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 357 358 #define CONFIG_SYS_BAUDRATE_TABLE \ 359 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 360 361 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 362 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 363 364 /* Use the HUSH parser */ 365 #define CONFIG_SYS_HUSH_PARSER 366 #ifdef CONFIG_SYS_HUSH_PARSER 367 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 368 #endif 369 370 /* 371 * Pass open firmware flat tree 372 */ 373 #define CONFIG_OF_LIBFDT 1 374 #define CONFIG_OF_BOARD_SETUP 1 375 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 376 377 #define CONFIG_SYS_64BIT_VSPRINTF 1 378 #define CONFIG_SYS_64BIT_STRTOUL 1 379 380 /* new uImage format support */ 381 #define CONFIG_FIT 1 382 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 383 384 /* I2C */ 385 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 386 #define CONFIG_HARD_I2C /* I2C with hardware support */ 387 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 388 #define CONFIG_I2C_MULTI_BUS 389 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 390 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 391 #define CONFIG_SYS_I2C_SLAVE 0x7F 392 #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 393 #define CONFIG_SYS_I2C_OFFSET 0x3000 394 #define CONFIG_SYS_I2C2_OFFSET 0x3100 395 396 /* 397 * I2C2 EEPROM 398 */ 399 #define CONFIG_ID_EEPROM 400 #ifdef CONFIG_ID_EEPROM 401 #define CONFIG_SYS_I2C_EEPROM_NXID 402 #endif 403 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 404 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 405 #define CONFIG_SYS_EEPROM_BUS_NUM 1 406 407 /* 408 * General PCI 409 * Memory space is mapped 1-1, but I/O space must start from 0. 410 */ 411 412 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 413 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 414 #ifdef CONFIG_PHYS_64BIT 415 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 416 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 417 #else 418 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 419 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 420 #endif 421 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 422 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 423 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 426 #else 427 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 428 #endif 429 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 430 431 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 432 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 433 #ifdef CONFIG_PHYS_64BIT 434 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 435 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 436 #else 437 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 438 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 439 #endif 440 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 441 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 442 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 443 #ifdef CONFIG_PHYS_64BIT 444 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 445 #else 446 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 447 #endif 448 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 449 450 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 451 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 452 #ifdef CONFIG_PHYS_64BIT 453 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 454 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 455 #else 456 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 457 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 458 #endif 459 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 460 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 461 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 462 #ifdef CONFIG_PHYS_64BIT 463 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 464 #else 465 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 466 #endif 467 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 468 469 #if defined(CONFIG_PCI) 470 471 /*PCIE video card used*/ 472 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 473 474 /* video */ 475 #define CONFIG_VIDEO 476 477 #if defined(CONFIG_VIDEO) 478 #define CONFIG_BIOSEMU 479 #define CONFIG_CFB_CONSOLE 480 #define CONFIG_VIDEO_SW_CURSOR 481 #define CONFIG_VGA_AS_SINGLE_DEVICE 482 #define CONFIG_ATI_RADEON_FB 483 #define CONFIG_VIDEO_LOGO 484 /*#define CONFIG_CONSOLE_CURSOR*/ 485 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 486 #endif 487 488 #define CONFIG_NET_MULTI 489 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 490 491 #undef CONFIG_EEPRO100 492 #undef CONFIG_TULIP 493 #undef CONFIG_RTL8139 494 495 #ifndef CONFIG_PCI_PNP 496 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 497 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 498 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 499 #endif 500 501 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 502 #define CONFIG_DOS_PARTITION 503 #define CONFIG_SCSI_AHCI 504 505 #ifdef CONFIG_SCSI_AHCI 506 #define CONFIG_SATA_ULI5288 507 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 508 #define CONFIG_SYS_SCSI_MAX_LUN 1 509 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 510 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 511 #endif /* SCSI */ 512 513 #endif /* CONFIG_PCI */ 514 515 516 #if defined(CONFIG_TSEC_ENET) 517 518 #ifndef CONFIG_NET_MULTI 519 #define CONFIG_NET_MULTI 1 520 #endif 521 522 #define CONFIG_MII 1 /* MII PHY management */ 523 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 524 #define CONFIG_TSEC1 1 525 #define CONFIG_TSEC1_NAME "eTSEC1" 526 #define CONFIG_TSEC2 1 527 #define CONFIG_TSEC2_NAME "eTSEC2" 528 #define CONFIG_TSEC3 1 529 #define CONFIG_TSEC3_NAME "eTSEC3" 530 #define CONFIG_TSEC4 1 531 #define CONFIG_TSEC4_NAME "eTSEC4" 532 533 #define CONFIG_PIXIS_SGMII_CMD 534 #define CONFIG_FSL_SGMII_RISER 1 535 #define SGMII_RISER_PHY_OFFSET 0x1c 536 537 #ifdef CONFIG_FSL_SGMII_RISER 538 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 539 #endif 540 541 #define TSEC1_PHY_ADDR 0 542 #define TSEC2_PHY_ADDR 1 543 #define TSEC3_PHY_ADDR 2 544 #define TSEC4_PHY_ADDR 3 545 546 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 547 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 548 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 549 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 550 551 #define TSEC1_PHYIDX 0 552 #define TSEC2_PHYIDX 0 553 #define TSEC3_PHYIDX 0 554 #define TSEC4_PHYIDX 0 555 556 #define CONFIG_ETHPRIME "eTSEC1" 557 558 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 559 #endif /* CONFIG_TSEC_ENET */ 560 561 /* 562 * Environment 563 */ 564 #define CONFIG_ENV_IS_IN_FLASH 1 565 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 566 #define CONFIG_ENV_ADDR 0xfff80000 567 #else 568 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 569 #endif 570 #define CONFIG_ENV_SIZE 0x2000 571 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 572 573 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 574 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 575 576 /* 577 * Command line configuration. 578 */ 579 #include <config_cmd_default.h> 580 581 #define CONFIG_CMD_IRQ 582 #define CONFIG_CMD_PING 583 #define CONFIG_CMD_I2C 584 #define CONFIG_CMD_MII 585 #define CONFIG_CMD_ELF 586 #define CONFIG_CMD_IRQ 587 #define CONFIG_CMD_SETEXPR 588 589 #if defined(CONFIG_PCI) 590 #define CONFIG_CMD_PCI 591 #define CONFIG_CMD_NET 592 #define CONFIG_CMD_SCSI 593 #define CONFIG_CMD_EXT2 594 #endif 595 596 #undef CONFIG_WATCHDOG /* watchdog disabled */ 597 598 /* 599 * Miscellaneous configurable options 600 */ 601 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 602 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 603 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 604 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 605 #if defined(CONFIG_CMD_KGDB) 606 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 607 #else 608 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 609 #endif 610 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 611 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 612 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 613 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 614 615 /* 616 * For booting Linux, the board info and command line data 617 * have to be in the first 16 MB of memory, since this is 618 * the maximum mapped by the Linux kernel during initialization. 619 */ 620 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 621 622 /* 623 * Internal Definitions 624 * 625 * Boot Flags 626 */ 627 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 628 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 629 630 #if defined(CONFIG_CMD_KGDB) 631 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 632 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 633 #endif 634 635 /* 636 * Environment Configuration 637 */ 638 639 /* The mac addresses for all ethernet interface */ 640 #if defined(CONFIG_TSEC_ENET) 641 #define CONFIG_HAS_ETH0 642 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 643 #define CONFIG_HAS_ETH1 644 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 645 #define CONFIG_HAS_ETH2 646 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 647 #define CONFIG_HAS_ETH3 648 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 649 #endif 650 651 #define CONFIG_IPADDR 192.168.1.254 652 653 #define CONFIG_HOSTNAME unknown 654 #define CONFIG_ROOTPATH /opt/nfsroot 655 #define CONFIG_BOOTFILE uImage 656 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 657 658 #define CONFIG_SERVERIP 192.168.1.1 659 #define CONFIG_GATEWAYIP 192.168.1.1 660 #define CONFIG_NETMASK 255.255.255.0 661 662 /* default location for tftp and bootm */ 663 #define CONFIG_LOADADDR 1000000 664 665 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 666 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 667 668 #define CONFIG_BAUDRATE 115200 669 670 #define CONFIG_EXTRA_ENV_SETTINGS \ 671 "memctl_intlv_ctl=2\0" \ 672 "netdev=eth0\0" \ 673 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 674 "tftpflash=tftpboot $loadaddr $uboot; " \ 675 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 676 "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 677 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 678 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 679 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 680 "consoledev=ttyS0\0" \ 681 "ramdiskaddr=2000000\0" \ 682 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 683 "fdtaddr=c00000\0" \ 684 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 685 "bdev=sda3\0" 686 687 #define CONFIG_HDBOOT \ 688 "setenv bootargs root=/dev/$bdev rw " \ 689 "console=$consoledev,$baudrate $othbootargs;" \ 690 "tftp $loadaddr $bootfile;" \ 691 "tftp $fdtaddr $fdtfile;" \ 692 "bootm $loadaddr - $fdtaddr" 693 694 #define CONFIG_NFSBOOTCOMMAND \ 695 "setenv bootargs root=/dev/nfs rw " \ 696 "nfsroot=$serverip:$rootpath " \ 697 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 698 "console=$consoledev,$baudrate $othbootargs;" \ 699 "tftp $loadaddr $bootfile;" \ 700 "tftp $fdtaddr $fdtfile;" \ 701 "bootm $loadaddr - $fdtaddr" 702 703 #define CONFIG_RAMBOOTCOMMAND \ 704 "setenv bootargs root=/dev/ram rw " \ 705 "console=$consoledev,$baudrate $othbootargs;" \ 706 "tftp $ramdiskaddr $ramdiskfile;" \ 707 "tftp $loadaddr $bootfile;" \ 708 "tftp $fdtaddr $fdtfile;" \ 709 "bootm $loadaddr $ramdiskaddr $fdtaddr" 710 711 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 712 713 #endif /* __CONFIG_H */ 714