1 /* 2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8572ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 #include "../board/freescale/common/ics307_clk.h" 18 19 #ifdef CONFIG_36BIT 20 #define CONFIG_PHYS_64BIT 21 #endif 22 23 #ifdef CONFIG_NAND 24 #define CONFIG_NAND_U_BOOT 25 #define CONFIG_RAMBOOT_NAND 26 #ifdef CONFIG_NAND_SPL 27 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 28 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 29 #else 30 #define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds 31 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 32 #endif /* CONFIG_NAND_SPL */ 33 #endif 34 35 #ifndef CONFIG_SYS_TEXT_BASE 36 #define CONFIG_SYS_TEXT_BASE 0xeff40000 37 #endif 38 39 #ifndef CONFIG_RESET_VECTOR_ADDRESS 40 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 41 #endif 42 43 #ifndef CONFIG_SYS_MONITOR_BASE 44 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 45 #endif 46 47 /* High Level Configuration Options */ 48 #define CONFIG_BOOKE 1 /* BOOKE */ 49 #define CONFIG_E500 1 /* BOOKE e500 family */ 50 #define CONFIG_MPC8572 1 51 #define CONFIG_MPC8572DS 1 52 #define CONFIG_MP 1 /* support multiple processors */ 53 54 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 55 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 56 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 57 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 58 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 59 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 60 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 61 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 62 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 63 64 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 65 66 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 67 #define CONFIG_ENV_OVERWRITE 68 69 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 70 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 71 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 72 73 /* 74 * These can be toggled for performance analysis, otherwise use default. 75 */ 76 #define CONFIG_L2_CACHE /* toggle L2 cache */ 77 #define CONFIG_BTB /* toggle branch predition */ 78 79 #define CONFIG_ENABLE_36BIT_PHYS 1 80 81 #ifdef CONFIG_PHYS_64BIT 82 #define CONFIG_ADDR_MAP 1 83 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 84 #endif 85 86 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 87 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 88 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 89 90 /* 91 * Config the L2 Cache as L2 SRAM 92 */ 93 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 94 #ifdef CONFIG_PHYS_64BIT 95 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 96 #else 97 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 98 #endif 99 #define CONFIG_SYS_L2_SIZE (512 << 10) 100 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 101 102 #define CONFIG_SYS_CCSRBAR 0xffe00000 103 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 104 105 #if defined(CONFIG_NAND_SPL) 106 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 107 #endif 108 109 /* DDR Setup */ 110 #define CONFIG_VERY_BIG_RAM 111 #define CONFIG_SYS_FSL_DDR2 112 #undef CONFIG_FSL_DDR_INTERACTIVE 113 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 114 #define CONFIG_DDR_SPD 115 116 #define CONFIG_DDR_ECC 117 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 118 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 119 120 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 121 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 122 123 #define CONFIG_NUM_DDR_CONTROLLERS 2 124 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 125 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 126 127 /* I2C addresses of SPD EEPROMs */ 128 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 129 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 130 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 131 132 /* These are used when DDR doesn't use SPD. */ 133 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 134 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 135 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 136 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 137 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 138 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 139 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 140 #define CONFIG_SYS_DDR_MODE_1 0x00440462 141 #define CONFIG_SYS_DDR_MODE_2 0x00000000 142 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 143 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 144 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 145 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 146 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 147 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 148 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 149 150 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 151 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 152 #define CONFIG_SYS_DDR_SBE 0x00010000 153 154 /* 155 * Make sure required options are set 156 */ 157 #ifndef CONFIG_SPD_EEPROM 158 #error ("CONFIG_SPD_EEPROM is required") 159 #endif 160 161 #undef CONFIG_CLOCKS_IN_MHZ 162 163 /* 164 * Memory map 165 * 166 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 167 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 168 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 169 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 170 * 171 * Localbus cacheable (TBD) 172 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 173 * 174 * Localbus non-cacheable 175 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 176 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 177 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 178 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 179 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 180 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 181 */ 182 183 /* 184 * Local Bus Definitions 185 */ 186 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 187 #ifdef CONFIG_PHYS_64BIT 188 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 189 #else 190 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 191 #endif 192 193 194 #define CONFIG_FLASH_BR_PRELIM \ 195 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 196 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 197 198 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 199 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 200 201 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 202 #define CONFIG_SYS_FLASH_QUIET_TEST 203 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 204 205 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 206 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 207 #undef CONFIG_SYS_FLASH_CHECKSUM 208 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 209 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 210 211 #if defined(CONFIG_RAMBOOT_NAND) 212 #define CONFIG_SYS_RAMBOOT 213 #define CONFIG_SYS_EXTRA_ENV_RELOC 214 #else 215 #undef CONFIG_SYS_RAMBOOT 216 #endif 217 218 #define CONFIG_FLASH_CFI_DRIVER 219 #define CONFIG_SYS_FLASH_CFI 220 #define CONFIG_SYS_FLASH_EMPTY_INFO 221 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 222 223 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 224 225 #define CONFIG_HWCONFIG /* enable hwconfig */ 226 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 227 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 228 #ifdef CONFIG_PHYS_64BIT 229 #define PIXIS_BASE_PHYS 0xfffdf0000ull 230 #else 231 #define PIXIS_BASE_PHYS PIXIS_BASE 232 #endif 233 234 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 235 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 236 237 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 238 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 239 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 240 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 241 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 242 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 243 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 244 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 245 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 246 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 247 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 248 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 249 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 250 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 251 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 252 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 253 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 254 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 255 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 256 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 257 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 258 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 259 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 260 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 261 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 262 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 263 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 264 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 265 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 266 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 267 #define PIXIS_LED 0x25 /* LED Register */ 268 269 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 270 271 /* old pixis referenced names */ 272 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 273 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 274 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 275 #define PIXIS_VSPEED2_TSEC1SER 0x8 276 #define PIXIS_VSPEED2_TSEC2SER 0x4 277 #define PIXIS_VSPEED2_TSEC3SER 0x2 278 #define PIXIS_VSPEED2_TSEC4SER 0x1 279 #define PIXIS_VCFGEN1_TSEC1SER 0x20 280 #define PIXIS_VCFGEN1_TSEC2SER 0x20 281 #define PIXIS_VCFGEN1_TSEC3SER 0x20 282 #define PIXIS_VCFGEN1_TSEC4SER 0x20 283 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 284 | PIXIS_VSPEED2_TSEC2SER \ 285 | PIXIS_VSPEED2_TSEC3SER \ 286 | PIXIS_VSPEED2_TSEC4SER) 287 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 288 | PIXIS_VCFGEN1_TSEC2SER \ 289 | PIXIS_VCFGEN1_TSEC3SER \ 290 | PIXIS_VCFGEN1_TSEC4SER) 291 292 #define CONFIG_SYS_INIT_RAM_LOCK 1 293 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 294 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 295 296 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 297 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 298 299 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 300 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 301 302 #ifndef CONFIG_NAND_SPL 303 #define CONFIG_SYS_NAND_BASE 0xffa00000 304 #ifdef CONFIG_PHYS_64BIT 305 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 306 #else 307 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 308 #endif 309 #else 310 #define CONFIG_SYS_NAND_BASE 0xfff00000 311 #ifdef CONFIG_PHYS_64BIT 312 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 313 #else 314 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 315 #endif 316 #endif 317 318 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 319 CONFIG_SYS_NAND_BASE + 0x40000, \ 320 CONFIG_SYS_NAND_BASE + 0x80000,\ 321 CONFIG_SYS_NAND_BASE + 0xC0000} 322 #define CONFIG_SYS_MAX_NAND_DEVICE 4 323 #define CONFIG_MTD_NAND_VERIFY_WRITE 324 #define CONFIG_CMD_NAND 1 325 #define CONFIG_NAND_FSL_ELBC 1 326 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 327 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 328 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 329 330 /* NAND boot: 4K NAND loader config */ 331 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 332 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 333 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 334 #define CONFIG_SYS_NAND_U_BOOT_START \ 335 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 336 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 337 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 338 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 339 340 341 /* NAND flash config */ 342 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 343 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 344 | BR_PS_8 /* Port Size = 8 bit */ \ 345 | BR_MS_FCM /* MSEL = FCM */ \ 346 | BR_V) /* valid */ 347 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 348 | OR_FCM_PGS /* Large Page*/ \ 349 | OR_FCM_CSCT \ 350 | OR_FCM_CST \ 351 | OR_FCM_CHT \ 352 | OR_FCM_SCY_1 \ 353 | OR_FCM_TRLX \ 354 | OR_FCM_EHTR) 355 356 #ifdef CONFIG_RAMBOOT_NAND 357 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 358 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 359 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 360 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 361 #else 362 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 363 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 364 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 365 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 366 #endif 367 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 368 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 369 | BR_PS_8 /* Port Size = 8 bit */ \ 370 | BR_MS_FCM /* MSEL = FCM */ \ 371 | BR_V) /* valid */ 372 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 373 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 374 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 375 | BR_PS_8 /* Port Size = 8 bit */ \ 376 | BR_MS_FCM /* MSEL = FCM */ \ 377 | BR_V) /* valid */ 378 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 379 380 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 381 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 382 | BR_PS_8 /* Port Size = 8 bit */ \ 383 | BR_MS_FCM /* MSEL = FCM */ \ 384 | BR_V) /* valid */ 385 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 386 387 388 /* Serial Port - controlled on board with jumper J8 389 * open - index 2 390 * shorted - index 1 391 */ 392 #define CONFIG_CONS_INDEX 1 393 #define CONFIG_SYS_NS16550 394 #define CONFIG_SYS_NS16550_SERIAL 395 #define CONFIG_SYS_NS16550_REG_SIZE 1 396 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 397 #ifdef CONFIG_NAND_SPL 398 #define CONFIG_NS16550_MIN_FUNCTIONS 399 #endif 400 401 #define CONFIG_SYS_BAUDRATE_TABLE \ 402 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 403 404 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 405 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 406 407 /* Use the HUSH parser */ 408 #define CONFIG_SYS_HUSH_PARSER 409 410 /* 411 * Pass open firmware flat tree 412 */ 413 #define CONFIG_OF_LIBFDT 1 414 #define CONFIG_OF_BOARD_SETUP 1 415 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 416 417 /* new uImage format support */ 418 #define CONFIG_FIT 1 419 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 420 421 /* I2C */ 422 #define CONFIG_SYS_I2C 423 #define CONFIG_SYS_I2C_FSL 424 #define CONFIG_SYS_FSL_I2C_SPEED 400000 425 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 426 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 427 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 428 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 429 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 430 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 431 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 432 433 /* 434 * I2C2 EEPROM 435 */ 436 #define CONFIG_ID_EEPROM 437 #ifdef CONFIG_ID_EEPROM 438 #define CONFIG_SYS_I2C_EEPROM_NXID 439 #endif 440 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 441 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 442 #define CONFIG_SYS_EEPROM_BUS_NUM 1 443 444 /* 445 * General PCI 446 * Memory space is mapped 1-1, but I/O space must start from 0. 447 */ 448 449 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 450 #define CONFIG_SYS_PCIE3_NAME "ULI" 451 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 452 #ifdef CONFIG_PHYS_64BIT 453 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 454 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 455 #else 456 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 457 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 458 #endif 459 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 460 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 461 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 462 #ifdef CONFIG_PHYS_64BIT 463 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 464 #else 465 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 466 #endif 467 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 468 469 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 470 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 471 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 472 #ifdef CONFIG_PHYS_64BIT 473 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 474 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 475 #else 476 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 477 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 478 #endif 479 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 480 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 481 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 482 #ifdef CONFIG_PHYS_64BIT 483 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 484 #else 485 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 486 #endif 487 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 488 489 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 490 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 491 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 492 #ifdef CONFIG_PHYS_64BIT 493 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 494 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 495 #else 496 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 497 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 498 #endif 499 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 500 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 501 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 502 #ifdef CONFIG_PHYS_64BIT 503 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 504 #else 505 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 506 #endif 507 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 508 509 #if defined(CONFIG_PCI) 510 511 /*PCIE video card used*/ 512 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 513 514 /* video */ 515 #define CONFIG_VIDEO 516 517 #if defined(CONFIG_VIDEO) 518 #define CONFIG_BIOSEMU 519 #define CONFIG_CFB_CONSOLE 520 #define CONFIG_VIDEO_SW_CURSOR 521 #define CONFIG_VGA_AS_SINGLE_DEVICE 522 #define CONFIG_ATI_RADEON_FB 523 #define CONFIG_VIDEO_LOGO 524 /*#define CONFIG_CONSOLE_CURSOR*/ 525 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 526 #endif 527 528 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 529 530 #undef CONFIG_EEPRO100 531 #undef CONFIG_TULIP 532 #undef CONFIG_RTL8139 533 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 534 535 #ifndef CONFIG_PCI_PNP 536 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 537 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 538 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 539 #endif 540 541 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 542 #define CONFIG_DOS_PARTITION 543 #define CONFIG_SCSI_AHCI 544 545 #ifdef CONFIG_SCSI_AHCI 546 #define CONFIG_LIBATA 547 #define CONFIG_SATA_ULI5288 548 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 549 #define CONFIG_SYS_SCSI_MAX_LUN 1 550 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 551 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 552 #endif /* SCSI */ 553 554 #endif /* CONFIG_PCI */ 555 556 557 #if defined(CONFIG_TSEC_ENET) 558 559 #define CONFIG_MII 1 /* MII PHY management */ 560 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 561 #define CONFIG_TSEC1 1 562 #define CONFIG_TSEC1_NAME "eTSEC1" 563 #define CONFIG_TSEC2 1 564 #define CONFIG_TSEC2_NAME "eTSEC2" 565 #define CONFIG_TSEC3 1 566 #define CONFIG_TSEC3_NAME "eTSEC3" 567 #define CONFIG_TSEC4 1 568 #define CONFIG_TSEC4_NAME "eTSEC4" 569 570 #define CONFIG_PIXIS_SGMII_CMD 571 #define CONFIG_FSL_SGMII_RISER 1 572 #define SGMII_RISER_PHY_OFFSET 0x1c 573 574 #ifdef CONFIG_FSL_SGMII_RISER 575 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 576 #endif 577 578 #define TSEC1_PHY_ADDR 0 579 #define TSEC2_PHY_ADDR 1 580 #define TSEC3_PHY_ADDR 2 581 #define TSEC4_PHY_ADDR 3 582 583 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 584 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 585 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 586 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 587 588 #define TSEC1_PHYIDX 0 589 #define TSEC2_PHYIDX 0 590 #define TSEC3_PHYIDX 0 591 #define TSEC4_PHYIDX 0 592 593 #define CONFIG_ETHPRIME "eTSEC1" 594 595 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 596 #endif /* CONFIG_TSEC_ENET */ 597 598 /* 599 * Environment 600 */ 601 602 #if defined(CONFIG_SYS_RAMBOOT) 603 #if defined(CONFIG_RAMBOOT_NAND) 604 #define CONFIG_ENV_IS_IN_NAND 1 605 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 606 #define CONFIG_ENV_OFFSET ((512 * 1024)\ 607 + CONFIG_SYS_NAND_BLOCK_SIZE) 608 #endif 609 610 #else 611 #define CONFIG_ENV_IS_IN_FLASH 1 612 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 613 #define CONFIG_ENV_ADDR 0xfff80000 614 #else 615 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 616 #endif 617 #define CONFIG_ENV_SIZE 0x2000 618 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 619 #endif 620 621 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 622 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 623 624 /* 625 * Command line configuration. 626 */ 627 #include <config_cmd_default.h> 628 629 #define CONFIG_CMD_ERRATA 630 #define CONFIG_CMD_IRQ 631 #define CONFIG_CMD_PING 632 #define CONFIG_CMD_I2C 633 #define CONFIG_CMD_MII 634 #define CONFIG_CMD_ELF 635 #define CONFIG_CMD_SETEXPR 636 #define CONFIG_CMD_REGINFO 637 638 #if defined(CONFIG_PCI) 639 #define CONFIG_CMD_PCI 640 #define CONFIG_CMD_NET 641 #define CONFIG_CMD_SCSI 642 #define CONFIG_CMD_EXT2 643 #endif 644 645 /* 646 * USB 647 */ 648 #define CONFIG_USB_EHCI 649 650 #ifdef CONFIG_USB_EHCI 651 #define CONFIG_CMD_USB 652 #define CONFIG_USB_EHCI_PCI 653 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 654 #define CONFIG_USB_STORAGE 655 #define CONFIG_PCI_EHCI_DEVICE 0 656 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 657 #endif 658 659 #undef CONFIG_WATCHDOG /* watchdog disabled */ 660 661 /* 662 * Miscellaneous configurable options 663 */ 664 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 665 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 666 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 667 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 668 #if defined(CONFIG_CMD_KGDB) 669 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 670 #else 671 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 672 #endif 673 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 674 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 675 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 676 677 /* 678 * For booting Linux, the board info and command line data 679 * have to be in the first 64 MB of memory, since this is 680 * the maximum mapped by the Linux kernel during initialization. 681 */ 682 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 683 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 684 685 #if defined(CONFIG_CMD_KGDB) 686 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 687 #endif 688 689 /* 690 * Environment Configuration 691 */ 692 693 /* The mac addresses for all ethernet interface */ 694 #if defined(CONFIG_TSEC_ENET) 695 #define CONFIG_HAS_ETH0 696 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 697 #define CONFIG_HAS_ETH1 698 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 699 #define CONFIG_HAS_ETH2 700 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 701 #define CONFIG_HAS_ETH3 702 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 703 #endif 704 705 #define CONFIG_IPADDR 192.168.1.254 706 707 #define CONFIG_HOSTNAME unknown 708 #define CONFIG_ROOTPATH "/opt/nfsroot" 709 #define CONFIG_BOOTFILE "uImage" 710 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 711 712 #define CONFIG_SERVERIP 192.168.1.1 713 #define CONFIG_GATEWAYIP 192.168.1.1 714 #define CONFIG_NETMASK 255.255.255.0 715 716 /* default location for tftp and bootm */ 717 #define CONFIG_LOADADDR 1000000 718 719 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 720 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 721 722 #define CONFIG_BAUDRATE 115200 723 724 #define CONFIG_EXTRA_ENV_SETTINGS \ 725 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 726 "netdev=eth0\0" \ 727 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 728 "tftpflash=tftpboot $loadaddr $uboot; " \ 729 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 730 " +$filesize; " \ 731 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 732 " +$filesize; " \ 733 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 734 " $filesize; " \ 735 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 736 " +$filesize; " \ 737 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 738 " $filesize\0" \ 739 "consoledev=ttyS0\0" \ 740 "ramdiskaddr=2000000\0" \ 741 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 742 "fdtaddr=c00000\0" \ 743 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 744 "bdev=sda3\0" 745 746 #define CONFIG_HDBOOT \ 747 "setenv bootargs root=/dev/$bdev rw " \ 748 "console=$consoledev,$baudrate $othbootargs;" \ 749 "tftp $loadaddr $bootfile;" \ 750 "tftp $fdtaddr $fdtfile;" \ 751 "bootm $loadaddr - $fdtaddr" 752 753 #define CONFIG_NFSBOOTCOMMAND \ 754 "setenv bootargs root=/dev/nfs rw " \ 755 "nfsroot=$serverip:$rootpath " \ 756 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 757 "console=$consoledev,$baudrate $othbootargs;" \ 758 "tftp $loadaddr $bootfile;" \ 759 "tftp $fdtaddr $fdtfile;" \ 760 "bootm $loadaddr - $fdtaddr" 761 762 #define CONFIG_RAMBOOTCOMMAND \ 763 "setenv bootargs root=/dev/ram rw " \ 764 "console=$consoledev,$baudrate $othbootargs;" \ 765 "tftp $ramdiskaddr $ramdiskfile;" \ 766 "tftp $loadaddr $bootfile;" \ 767 "tftp $fdtaddr $fdtfile;" \ 768 "bootm $loadaddr $ramdiskaddr $fdtaddr" 769 770 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 771 772 #endif /* __CONFIG_H */ 773