1 /* 2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8572ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifndef CONFIG_RESET_VECTOR_ADDRESS 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 18 #endif 19 20 #ifndef CONFIG_SYS_MONITOR_BASE 21 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 22 #endif 23 24 /* High Level Configuration Options */ 25 #define CONFIG_MP 1 /* support multiple processors */ 26 27 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 28 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 29 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 30 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 31 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 32 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 33 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 34 35 #define CONFIG_ENV_OVERWRITE 36 37 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 38 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 39 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 40 41 /* 42 * These can be toggled for performance analysis, otherwise use default. 43 */ 44 #define CONFIG_L2_CACHE /* toggle L2 cache */ 45 #define CONFIG_BTB /* toggle branch predition */ 46 47 #define CONFIG_ENABLE_36BIT_PHYS 1 48 49 #ifdef CONFIG_PHYS_64BIT 50 #define CONFIG_ADDR_MAP 1 51 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 52 #endif 53 54 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 55 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 56 57 /* 58 * Config the L2 Cache as L2 SRAM 59 */ 60 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 61 #ifdef CONFIG_PHYS_64BIT 62 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 63 #else 64 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 65 #endif 66 #define CONFIG_SYS_L2_SIZE (512 << 10) 67 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 68 69 #define CONFIG_SYS_CCSRBAR 0xffe00000 70 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 71 72 #if defined(CONFIG_NAND_SPL) 73 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 74 #endif 75 76 /* DDR Setup */ 77 #define CONFIG_VERY_BIG_RAM 78 #undef CONFIG_FSL_DDR_INTERACTIVE 79 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 80 #define CONFIG_DDR_SPD 81 82 #define CONFIG_DDR_ECC 83 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 84 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 85 86 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 87 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 88 89 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 90 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 91 92 /* I2C addresses of SPD EEPROMs */ 93 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 94 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 95 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 96 97 /* These are used when DDR doesn't use SPD. */ 98 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 99 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 100 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 101 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 102 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 103 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 104 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 105 #define CONFIG_SYS_DDR_MODE_1 0x00440462 106 #define CONFIG_SYS_DDR_MODE_2 0x00000000 107 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 108 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 109 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 110 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 111 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 112 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 113 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 114 115 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 116 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 117 #define CONFIG_SYS_DDR_SBE 0x00010000 118 119 /* 120 * Make sure required options are set 121 */ 122 #ifndef CONFIG_SPD_EEPROM 123 #error ("CONFIG_SPD_EEPROM is required") 124 #endif 125 126 #undef CONFIG_CLOCKS_IN_MHZ 127 128 /* 129 * Memory map 130 * 131 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 132 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 133 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 134 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 135 * 136 * Localbus cacheable (TBD) 137 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 138 * 139 * Localbus non-cacheable 140 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 141 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 142 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 143 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 144 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 145 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 146 */ 147 148 /* 149 * Local Bus Definitions 150 */ 151 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 152 #ifdef CONFIG_PHYS_64BIT 153 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 154 #else 155 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 156 #endif 157 158 #define CONFIG_FLASH_BR_PRELIM \ 159 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 160 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 161 162 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 163 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 164 165 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 166 #define CONFIG_SYS_FLASH_QUIET_TEST 167 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 168 169 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 170 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 171 #undef CONFIG_SYS_FLASH_CHECKSUM 172 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 173 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 174 175 #undef CONFIG_SYS_RAMBOOT 176 177 #define CONFIG_FLASH_CFI_DRIVER 178 #define CONFIG_SYS_FLASH_CFI 179 #define CONFIG_SYS_FLASH_EMPTY_INFO 180 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 181 182 #define CONFIG_HWCONFIG /* enable hwconfig */ 183 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 184 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 185 #ifdef CONFIG_PHYS_64BIT 186 #define PIXIS_BASE_PHYS 0xfffdf0000ull 187 #else 188 #define PIXIS_BASE_PHYS PIXIS_BASE 189 #endif 190 191 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 192 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 193 194 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 195 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 196 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 197 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 198 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 199 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 200 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 201 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 202 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 203 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 204 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 205 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 206 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 207 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 208 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 209 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 210 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 211 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 212 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 213 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 214 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 215 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 216 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 217 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 218 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 219 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 220 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 221 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 222 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 223 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 224 #define PIXIS_LED 0x25 /* LED Register */ 225 226 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 227 228 /* old pixis referenced names */ 229 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 230 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 231 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 232 #define PIXIS_VSPEED2_TSEC1SER 0x8 233 #define PIXIS_VSPEED2_TSEC2SER 0x4 234 #define PIXIS_VSPEED2_TSEC3SER 0x2 235 #define PIXIS_VSPEED2_TSEC4SER 0x1 236 #define PIXIS_VCFGEN1_TSEC1SER 0x20 237 #define PIXIS_VCFGEN1_TSEC2SER 0x20 238 #define PIXIS_VCFGEN1_TSEC3SER 0x20 239 #define PIXIS_VCFGEN1_TSEC4SER 0x20 240 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 241 | PIXIS_VSPEED2_TSEC2SER \ 242 | PIXIS_VSPEED2_TSEC3SER \ 243 | PIXIS_VSPEED2_TSEC4SER) 244 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 245 | PIXIS_VCFGEN1_TSEC2SER \ 246 | PIXIS_VCFGEN1_TSEC3SER \ 247 | PIXIS_VCFGEN1_TSEC4SER) 248 249 #define CONFIG_SYS_INIT_RAM_LOCK 1 250 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 251 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 252 253 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 254 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 255 256 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 257 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 258 259 #ifndef CONFIG_NAND_SPL 260 #define CONFIG_SYS_NAND_BASE 0xffa00000 261 #ifdef CONFIG_PHYS_64BIT 262 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 263 #else 264 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 265 #endif 266 #else 267 #define CONFIG_SYS_NAND_BASE 0xfff00000 268 #ifdef CONFIG_PHYS_64BIT 269 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 270 #else 271 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 272 #endif 273 #endif 274 275 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 276 CONFIG_SYS_NAND_BASE + 0x40000, \ 277 CONFIG_SYS_NAND_BASE + 0x80000,\ 278 CONFIG_SYS_NAND_BASE + 0xC0000} 279 #define CONFIG_SYS_MAX_NAND_DEVICE 4 280 #define CONFIG_NAND_FSL_ELBC 1 281 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 282 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 283 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 284 285 /* NAND boot: 4K NAND loader config */ 286 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 287 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 288 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 289 #define CONFIG_SYS_NAND_U_BOOT_START \ 290 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 291 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 292 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 293 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 294 295 /* NAND flash config */ 296 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 297 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 298 | BR_PS_8 /* Port Size = 8 bit */ \ 299 | BR_MS_FCM /* MSEL = FCM */ \ 300 | BR_V) /* valid */ 301 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 302 | OR_FCM_PGS /* Large Page*/ \ 303 | OR_FCM_CSCT \ 304 | OR_FCM_CST \ 305 | OR_FCM_CHT \ 306 | OR_FCM_SCY_1 \ 307 | OR_FCM_TRLX \ 308 | OR_FCM_EHTR) 309 310 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 311 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 312 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 313 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 314 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 315 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 316 | BR_PS_8 /* Port Size = 8 bit */ \ 317 | BR_MS_FCM /* MSEL = FCM */ \ 318 | BR_V) /* valid */ 319 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 320 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 321 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 322 | BR_PS_8 /* Port Size = 8 bit */ \ 323 | BR_MS_FCM /* MSEL = FCM */ \ 324 | BR_V) /* valid */ 325 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 326 327 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 328 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 329 | BR_PS_8 /* Port Size = 8 bit */ \ 330 | BR_MS_FCM /* MSEL = FCM */ \ 331 | BR_V) /* valid */ 332 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 333 334 /* Serial Port - controlled on board with jumper J8 335 * open - index 2 336 * shorted - index 1 337 */ 338 #define CONFIG_SYS_NS16550_SERIAL 339 #define CONFIG_SYS_NS16550_REG_SIZE 1 340 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 341 #ifdef CONFIG_NAND_SPL 342 #define CONFIG_NS16550_MIN_FUNCTIONS 343 #endif 344 345 #define CONFIG_SYS_BAUDRATE_TABLE \ 346 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 347 348 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 349 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 350 351 /* I2C */ 352 #define CONFIG_SYS_I2C 353 #define CONFIG_SYS_I2C_FSL 354 #define CONFIG_SYS_FSL_I2C_SPEED 400000 355 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 356 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 357 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 358 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 359 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 360 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 361 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 362 363 /* 364 * I2C2 EEPROM 365 */ 366 #define CONFIG_ID_EEPROM 367 #ifdef CONFIG_ID_EEPROM 368 #define CONFIG_SYS_I2C_EEPROM_NXID 369 #endif 370 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 371 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 372 #define CONFIG_SYS_EEPROM_BUS_NUM 1 373 374 /* 375 * General PCI 376 * Memory space is mapped 1-1, but I/O space must start from 0. 377 */ 378 379 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 380 #define CONFIG_SYS_PCIE3_NAME "ULI" 381 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 382 #ifdef CONFIG_PHYS_64BIT 383 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 384 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 385 #else 386 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 387 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 388 #endif 389 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 390 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 391 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 392 #ifdef CONFIG_PHYS_64BIT 393 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 394 #else 395 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 396 #endif 397 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 398 399 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 400 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 401 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 402 #ifdef CONFIG_PHYS_64BIT 403 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 404 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 405 #else 406 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 407 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 408 #endif 409 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 410 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 411 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 412 #ifdef CONFIG_PHYS_64BIT 413 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 414 #else 415 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 416 #endif 417 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 418 419 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 420 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 421 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 422 #ifdef CONFIG_PHYS_64BIT 423 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 424 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 425 #else 426 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 427 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 428 #endif 429 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 430 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 431 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 432 #ifdef CONFIG_PHYS_64BIT 433 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 434 #else 435 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 436 #endif 437 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 438 439 #if defined(CONFIG_PCI) 440 441 /*PCIE video card used*/ 442 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 443 444 /* video */ 445 446 #if defined(CONFIG_VIDEO) 447 #define CONFIG_BIOSEMU 448 #define CONFIG_ATI_RADEON_FB 449 #define CONFIG_VIDEO_LOGO 450 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 451 #endif 452 453 #undef CONFIG_EEPRO100 454 #undef CONFIG_TULIP 455 456 #ifndef CONFIG_PCI_PNP 457 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 458 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 459 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 460 #endif 461 462 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 463 464 #ifdef CONFIG_SCSI_AHCI 465 #define CONFIG_SATA_ULI5288 466 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 467 #define CONFIG_SYS_SCSI_MAX_LUN 1 468 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 469 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 470 #endif /* SCSI */ 471 472 #endif /* CONFIG_PCI */ 473 474 #if defined(CONFIG_TSEC_ENET) 475 476 #define CONFIG_MII 1 /* MII PHY management */ 477 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 478 #define CONFIG_TSEC1 1 479 #define CONFIG_TSEC1_NAME "eTSEC1" 480 #define CONFIG_TSEC2 1 481 #define CONFIG_TSEC2_NAME "eTSEC2" 482 #define CONFIG_TSEC3 1 483 #define CONFIG_TSEC3_NAME "eTSEC3" 484 #define CONFIG_TSEC4 1 485 #define CONFIG_TSEC4_NAME "eTSEC4" 486 487 #define CONFIG_PIXIS_SGMII_CMD 488 #define CONFIG_FSL_SGMII_RISER 1 489 #define SGMII_RISER_PHY_OFFSET 0x1c 490 491 #ifdef CONFIG_FSL_SGMII_RISER 492 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 493 #endif 494 495 #define TSEC1_PHY_ADDR 0 496 #define TSEC2_PHY_ADDR 1 497 #define TSEC3_PHY_ADDR 2 498 #define TSEC4_PHY_ADDR 3 499 500 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 501 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 502 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 503 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 504 505 #define TSEC1_PHYIDX 0 506 #define TSEC2_PHYIDX 0 507 #define TSEC3_PHYIDX 0 508 #define TSEC4_PHYIDX 0 509 510 #define CONFIG_ETHPRIME "eTSEC1" 511 #endif /* CONFIG_TSEC_ENET */ 512 513 /* 514 * Environment 515 */ 516 517 #if defined(CONFIG_SYS_RAMBOOT) 518 519 #else 520 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 521 #define CONFIG_ENV_ADDR 0xfff80000 522 #else 523 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 524 #endif 525 #define CONFIG_ENV_SIZE 0x2000 526 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 527 #endif 528 529 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 530 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 531 532 /* 533 * USB 534 */ 535 536 #ifdef CONFIG_USB_EHCI_HCD 537 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 538 #define CONFIG_PCI_EHCI_DEVICE 0 539 #endif 540 541 #undef CONFIG_WATCHDOG /* watchdog disabled */ 542 543 /* 544 * Miscellaneous configurable options 545 */ 546 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 547 548 /* 549 * For booting Linux, the board info and command line data 550 * have to be in the first 64 MB of memory, since this is 551 * the maximum mapped by the Linux kernel during initialization. 552 */ 553 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 554 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 555 556 #if defined(CONFIG_CMD_KGDB) 557 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 558 #endif 559 560 /* 561 * Environment Configuration 562 */ 563 #if defined(CONFIG_TSEC_ENET) 564 #define CONFIG_HAS_ETH0 565 #define CONFIG_HAS_ETH1 566 #define CONFIG_HAS_ETH2 567 #define CONFIG_HAS_ETH3 568 #endif 569 570 #define CONFIG_IPADDR 192.168.1.254 571 572 #define CONFIG_HOSTNAME "unknown" 573 #define CONFIG_ROOTPATH "/opt/nfsroot" 574 #define CONFIG_BOOTFILE "uImage" 575 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 576 577 #define CONFIG_SERVERIP 192.168.1.1 578 #define CONFIG_GATEWAYIP 192.168.1.1 579 #define CONFIG_NETMASK 255.255.255.0 580 581 /* default location for tftp and bootm */ 582 #define CONFIG_LOADADDR 1000000 583 584 #define CONFIG_EXTRA_ENV_SETTINGS \ 585 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 586 "netdev=eth0\0" \ 587 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 588 "tftpflash=tftpboot $loadaddr $uboot; " \ 589 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 590 " +$filesize; " \ 591 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 592 " +$filesize; " \ 593 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 594 " $filesize; " \ 595 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 596 " +$filesize; " \ 597 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 598 " $filesize\0" \ 599 "consoledev=ttyS0\0" \ 600 "ramdiskaddr=2000000\0" \ 601 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 602 "fdtaddr=1e00000\0" \ 603 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 604 "bdev=sda3\0" 605 606 #define CONFIG_HDBOOT \ 607 "setenv bootargs root=/dev/$bdev rw " \ 608 "console=$consoledev,$baudrate $othbootargs;" \ 609 "tftp $loadaddr $bootfile;" \ 610 "tftp $fdtaddr $fdtfile;" \ 611 "bootm $loadaddr - $fdtaddr" 612 613 #define CONFIG_NFSBOOTCOMMAND \ 614 "setenv bootargs root=/dev/nfs rw " \ 615 "nfsroot=$serverip:$rootpath " \ 616 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 617 "console=$consoledev,$baudrate $othbootargs;" \ 618 "tftp $loadaddr $bootfile;" \ 619 "tftp $fdtaddr $fdtfile;" \ 620 "bootm $loadaddr - $fdtaddr" 621 622 #define CONFIG_RAMBOOTCOMMAND \ 623 "setenv bootargs root=/dev/ram rw " \ 624 "console=$consoledev,$baudrate $othbootargs;" \ 625 "tftp $ramdiskaddr $ramdiskfile;" \ 626 "tftp $loadaddr $bootfile;" \ 627 "tftp $fdtaddr $fdtfile;" \ 628 "bootm $loadaddr $ramdiskaddr $fdtaddr" 629 630 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 631 632 #endif /* __CONFIG_H */ 633