xref: /openbmc/u-boot/include/configs/MPC8572DS.h (revision 6b59e03e)
1 /*
2  * Copyright 2007-2008 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 /*
24  * mpc8572ds board configuration file
25  *
26  */
27 #ifndef __CONFIG_H
28 #define __CONFIG_H
29 
30 /* High Level Configuration Options */
31 #define CONFIG_BOOKE		1	/* BOOKE */
32 #define CONFIG_E500		1	/* BOOKE e500 family */
33 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
34 #define CONFIG_MPC8572		1
35 #define CONFIG_MPC8572DS	1
36 #define CONFIG_MP		1	/* support multiple processors */
37 #define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
38 
39 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
40 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
41 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
42 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
43 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
44 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
45 
46 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
47 
48 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
49 #define CONFIG_ENV_OVERWRITE
50 
51 /*
52  * When initializing flash, if we cannot find the manufacturer ID,
53  * assume this is the AMD flash associated with the CDS board.
54  * This allows booting from a promjet.
55  */
56 #define CONFIG_ASSUME_AMD_FLASH
57 
58 #ifndef __ASSEMBLY__
59 extern unsigned long get_board_sys_clk(unsigned long dummy);
60 extern unsigned long get_board_ddr_clk(unsigned long dummy);
61 #endif
62 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
63 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk(0) /* ddrclk for MPC85xx */
64 #define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
65 #define CONFIG_GET_CLK_FROM_ICS307	  /* decode sysclk and ddrclk freq
66 					     from ICS307 instead of switches */
67 
68 /*
69  * These can be toggled for performance analysis, otherwise use default.
70  */
71 #define CONFIG_L2_CACHE			/* toggle L2 cache */
72 #define CONFIG_BTB			/* toggle branch predition */
73 #define CONFIG_ADDR_STREAMING		/* toggle addr streaming */
74 
75 #define CONFIG_ENABLE_36BIT_PHYS	1
76 
77 #define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
78 #define CONFIG_SYS_MEMTEST_END		0x7fffffff
79 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
80 
81 /*
82  * Base addresses -- Note these are effective addresses where the
83  * actual resources get mapped (not physical addresses)
84  */
85 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
86 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
87 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
88 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
89 
90 #define CONFIG_SYS_PCIE3_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
91 #define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
92 #define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
93 
94 /* DDR Setup */
95 #define CONFIG_FSL_DDR2
96 #undef CONFIG_FSL_DDR_INTERACTIVE
97 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
98 #define CONFIG_DDR_SPD
99 #undef CONFIG_DDR_DLL
100 
101 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
102 
103 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
104 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
105 
106 #define CONFIG_NUM_DDR_CONTROLLERS	2
107 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
108 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
109 
110 /* I2C addresses of SPD EEPROMs */
111 #define CONFIG_SYS_SPD_BUS_NUM		1	/* SPD EEPROMS locate on I2C bus 1 */
112 #define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
113 #define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 1 DIMM 0 */
114 
115 /* These are used when DDR doesn't use SPD.  */
116 #define CONFIG_SYS_SDRAM_SIZE		256		/* DDR is 256MB */
117 #define CONFIG_SYS_DDR_CS0_BNDS	0x0000001F
118 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010102	/* Enable, no interleaving */
119 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
120 #define CONFIG_SYS_DDR_TIMING_0	0x00260802
121 #define CONFIG_SYS_DDR_TIMING_1	0x3935d322
122 #define CONFIG_SYS_DDR_TIMING_2	0x14904cc8
123 #define CONFIG_SYS_DDR_MODE_1		0x00480432
124 #define CONFIG_SYS_DDR_MODE_2		0x00000000
125 #define CONFIG_SYS_DDR_INTERVAL	0x06180100
126 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
127 #define CONFIG_SYS_DDR_CLK_CTRL	0x03800000
128 #define CONFIG_SYS_DDR_OCD_CTRL	0x00000000
129 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
130 #define CONFIG_SYS_DDR_CONTROL		0xC3008000	/* Type = DDR2 */
131 #define CONFIG_SYS_DDR_CONTROL2	0x04400010
132 
133 #define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
134 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000
135 #define CONFIG_SYS_DDR_SBE		0x00010000
136 
137 /*
138  * FIXME: Not used in fixed_sdram function
139  */
140 #define CONFIG_SYS_DDR_MODE		0x00000022
141 #define CONFIG_SYS_DDR_CS1_BNDS	0x00000000
142 #define CONFIG_SYS_DDR_CS2_BNDS	0x00000FFF	/* Not done */
143 #define CONFIG_SYS_DDR_CS3_BNDS	0x00000FFF	/* Not done */
144 #define CONFIG_SYS_DDR_CS4_BNDS	0x00000FFF	/* Not done */
145 #define CONFIG_SYS_DDR_CS5_BNDS	0x00000FFF	/* Not done */
146 
147 /*
148  * Make sure required options are set
149  */
150 #ifndef CONFIG_SPD_EEPROM
151 #error ("CONFIG_SPD_EEPROM is required")
152 #endif
153 
154 #undef CONFIG_CLOCKS_IN_MHZ
155 
156 /*
157  * Memory map
158  *
159  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
160  * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
161  * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
162  * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
163  *
164  * Localbus cacheable (TBD)
165  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
166  *
167  * Localbus non-cacheable
168  * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
169  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
170  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
171  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
172  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
173  */
174 
175 /*
176  * Local Bus Definitions
177  */
178 #define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
179 
180 #define CONFIG_SYS_BR0_PRELIM		0xe8001001
181 #define CONFIG_SYS_OR0_PRELIM		0xf8000ff7
182 
183 #define CONFIG_SYS_BR1_PRELIM		0xe0001001
184 #define CONFIG_SYS_OR1_PRELIM		0xf8000ff7
185 
186 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE}
187 #define CONFIG_SYS_FLASH_QUIET_TEST
188 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
189 
190 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
191 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
192 #undef	CONFIG_SYS_FLASH_CHECKSUM
193 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
194 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
195 
196 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
197 
198 #define CONFIG_FLASH_CFI_DRIVER
199 #define CONFIG_SYS_FLASH_CFI
200 #define CONFIG_SYS_FLASH_EMPTY_INFO
201 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
202 
203 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
204 
205 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
206 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
207 
208 #define CONFIG_SYS_BR3_PRELIM	(PIXIS_BASE | 0x0801)	/* port size 8bit */
209 #define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
210 
211 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
212 #define PIXIS_VER		0x1	/* Board version at offset 1 */
213 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
214 #define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
215 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
216 #define PIXIS_PWR		0x5	/* PIXIS Power status register */
217 #define PIXIS_AUX		0x6	/* Auxiliary 1 register */
218 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
219 #define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
220 #define PIXIS_VCTL		0x10	/* VELA Control Register */
221 #define PIXIS_VSTAT		0x11	/* VELA Status Register */
222 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
223 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
224 #define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
225 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
226 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
227 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
228 #define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
229 #define PIXIS_VSYSCLK0		0x1C	/* VELA SYSCLK0 Register */
230 #define PIXIS_VSYSCLK1		0x1D	/* VELA SYSCLK1 Register */
231 #define PIXIS_VSYSCLK2		0x1E	/* VELA SYSCLK2 Register */
232 #define PIXIS_VDDRCLK0		0x1F	/* VELA DDRCLK0 Register */
233 #define PIXIS_VDDRCLK1		0x20	/* VELA DDRCLK1 Register */
234 #define PIXIS_VDDRCLK2		0x21	/* VELA DDRCLK2 Register */
235 #define PIXIS_VWATCH		0x24    /* Watchdog Register */
236 #define PIXIS_LED		0x25    /* LED Register */
237 
238 /* old pixis referenced names */
239 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
240 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
241 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
242 #define PIXIS_VSPEED2_TSEC1SER	0x8
243 #define PIXIS_VSPEED2_TSEC2SER	0x4
244 #define PIXIS_VSPEED2_TSEC3SER	0x2
245 #define PIXIS_VSPEED2_TSEC4SER	0x1
246 #define PIXIS_VCFGEN1_TSEC1SER	0x20
247 #define PIXIS_VCFGEN1_TSEC2SER	0x20
248 #define PIXIS_VCFGEN1_TSEC3SER	0x20
249 #define PIXIS_VCFGEN1_TSEC4SER	0x20
250 #define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER \
251 					| PIXIS_VSPEED2_TSEC2SER \
252 					| PIXIS_VSPEED2_TSEC3SER \
253 					| PIXIS_VSPEED2_TSEC4SER)
254 #define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER \
255 					| PIXIS_VCFGEN1_TSEC2SER \
256 					| PIXIS_VCFGEN1_TSEC3SER \
257 					| PIXIS_VCFGEN1_TSEC4SER)
258 
259 /* define to use L1 as initial stack */
260 #define CONFIG_L1_INIT_RAM
261 #define CONFIG_SYS_INIT_RAM_LOCK	1
262 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
263 #define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
264 
265 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
266 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
267 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
268 
269 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
270 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
271 
272 /* Serial Port - controlled on board with jumper J8
273  * open - index 2
274  * shorted - index 1
275  */
276 #define CONFIG_CONS_INDEX	1
277 #undef	CONFIG_SERIAL_SOFTWARE_FIFO
278 #define CONFIG_SYS_NS16550
279 #define CONFIG_SYS_NS16550_SERIAL
280 #define CONFIG_SYS_NS16550_REG_SIZE	1
281 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
282 
283 #define CONFIG_SYS_BAUDRATE_TABLE	\
284 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
285 
286 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
287 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
288 
289 /* Use the HUSH parser */
290 #define CONFIG_SYS_HUSH_PARSER
291 #ifdef	CONFIG_SYS_HUSH_PARSER
292 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
293 #endif
294 
295 /*
296  * Pass open firmware flat tree
297  */
298 #define CONFIG_OF_LIBFDT		1
299 #define CONFIG_OF_BOARD_SETUP		1
300 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
301 
302 #define CONFIG_SYS_64BIT_VSPRINTF	1
303 #define CONFIG_SYS_64BIT_STRTOUL	1
304 
305 /* new uImage format support */
306 #define CONFIG_FIT		1
307 #define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
308 
309 /* I2C */
310 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
311 #define CONFIG_HARD_I2C		/* I2C with hardware support */
312 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
313 #define CONFIG_I2C_MULTI_BUS
314 #define CONFIG_I2C_CMD_TREE
315 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
316 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
317 #define CONFIG_SYS_I2C_SLAVE		0x7F
318 #define CONFIG_SYS_I2C_NOPROBES	{{0,0x29}}/* Don't probe these addrs */
319 #define CONFIG_SYS_I2C_OFFSET		0x3000
320 #define CONFIG_SYS_I2C2_OFFSET		0x3100
321 
322 /*
323  * I2C2 EEPROM
324  */
325 #define CONFIG_ID_EEPROM
326 #ifdef CONFIG_ID_EEPROM
327 #define CONFIG_SYS_I2C_EEPROM_NXID
328 #endif
329 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
330 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
331 #define CONFIG_SYS_EEPROM_BUS_NUM	1
332 
333 /*
334  * General PCI
335  * Memory space is mapped 1-1, but I/O space must start from 0.
336  */
337 
338 /* PCI view of System Memory */
339 #define CONFIG_SYS_PCI_MEMORY_BUS	0x00000000
340 #define CONFIG_SYS_PCI_MEMORY_PHYS	0x00000000
341 #define CONFIG_SYS_PCI_MEMORY_SIZE	0x80000000
342 
343 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
344 #define CONFIG_SYS_PCIE3_MEM_BASE	0x80000000
345 #define CONFIG_SYS_PCIE3_MEM_PHYS	CONFIG_SYS_PCIE3_MEM_BASE
346 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
347 #define CONFIG_SYS_PCIE3_IO_BASE	0x00000000
348 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
349 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
350 
351 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
352 #define CONFIG_SYS_PCIE2_MEM_BASE	0xa0000000
353 #define CONFIG_SYS_PCIE2_MEM_PHYS	CONFIG_SYS_PCIE2_MEM_BASE
354 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
355 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
356 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
357 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
358 
359 /* controller 1, Slot 1, tgtid 1, Base address a000 */
360 #define CONFIG_SYS_PCIE1_MEM_BASE	0xc0000000
361 #define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BASE
362 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
363 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
364 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
365 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
366 
367 #if defined(CONFIG_PCI)
368 
369 /*PCIE video card used*/
370 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_PHYS
371 
372 /* video */
373 #define CONFIG_VIDEO
374 
375 #if defined(CONFIG_VIDEO)
376 #define CONFIG_BIOSEMU
377 #define CONFIG_CFB_CONSOLE
378 #define CONFIG_VIDEO_SW_CURSOR
379 #define CONFIG_VGA_AS_SINGLE_DEVICE
380 #define CONFIG_ATI_RADEON_FB
381 #define CONFIG_VIDEO_LOGO
382 /*#define CONFIG_CONSOLE_CURSOR*/
383 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
384 #endif
385 
386 #define CONFIG_NET_MULTI
387 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
388 
389 #undef CONFIG_EEPRO100
390 #undef CONFIG_TULIP
391 #undef CONFIG_RTL8139
392 
393 #ifdef CONFIG_RTL8139
394 /* This macro is used by RTL8139 but not defined in PPC architecture */
395 #define KSEG1ADDR(x)		(x)
396 #define _IO_BASE	0x00000000
397 #endif
398 
399 #ifndef CONFIG_PCI_PNP
400 	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCIE3_IO_BASE
401 	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCIE3_IO_BASE
402 	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
403 #endif
404 
405 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
406 #define CONFIG_DOS_PARTITION
407 #define CONFIG_SCSI_AHCI
408 
409 #ifdef CONFIG_SCSI_AHCI
410 #define CONFIG_SATA_ULI5288
411 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
412 #define CONFIG_SYS_SCSI_MAX_LUN	1
413 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
414 #define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
415 #endif /* SCSI */
416 
417 #endif	/* CONFIG_PCI */
418 
419 
420 #if defined(CONFIG_TSEC_ENET)
421 
422 #ifndef CONFIG_NET_MULTI
423 #define CONFIG_NET_MULTI	1
424 #endif
425 
426 #define CONFIG_MII		1	/* MII PHY management */
427 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
428 #define CONFIG_TSEC1	1
429 #define CONFIG_TSEC1_NAME	"eTSEC1"
430 #define CONFIG_TSEC2	1
431 #define CONFIG_TSEC2_NAME	"eTSEC2"
432 #define CONFIG_TSEC3	1
433 #define CONFIG_TSEC3_NAME	"eTSEC3"
434 #define CONFIG_TSEC4	1
435 #define CONFIG_TSEC4_NAME	"eTSEC4"
436 
437 #define CONFIG_PIXIS_SGMII_CMD
438 #define CONFIG_FSL_SGMII_RISER	1
439 #define SGMII_RISER_PHY_OFFSET	0x1c
440 
441 #ifdef CONFIG_FSL_SGMII_RISER
442 #define CONFIG_SYS_TBIPA_VALUE		0x10 /* avoid conflict with eTSEC4 paddr */
443 #endif
444 
445 #define TSEC1_PHY_ADDR		0
446 #define TSEC2_PHY_ADDR		1
447 #define TSEC3_PHY_ADDR		2
448 #define TSEC4_PHY_ADDR		3
449 
450 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
451 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
452 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
453 #define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
454 
455 #define TSEC1_PHYIDX		0
456 #define TSEC2_PHYIDX		0
457 #define TSEC3_PHYIDX		0
458 #define TSEC4_PHYIDX		0
459 
460 #define CONFIG_ETHPRIME		"eTSEC1"
461 
462 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
463 #endif	/* CONFIG_TSEC_ENET */
464 
465 /*
466  * Environment
467  */
468 #define CONFIG_ENV_IS_IN_FLASH	1
469 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
470 #define CONFIG_ENV_ADDR		0xfff80000
471 #else
472 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x70000)
473 #endif
474 #define CONFIG_ENV_SIZE		0x2000
475 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
476 
477 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
478 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
479 
480 /*
481  * Command line configuration.
482  */
483 #include <config_cmd_default.h>
484 
485 #define CONFIG_CMD_IRQ
486 #define CONFIG_CMD_PING
487 #define CONFIG_CMD_I2C
488 #define CONFIG_CMD_MII
489 #define CONFIG_CMD_ELF
490 #define CONFIG_CMD_IRQ
491 #define CONFIG_CMD_SETEXPR
492 
493 #if defined(CONFIG_PCI)
494 #define CONFIG_CMD_PCI
495 #define CONFIG_CMD_BEDBUG
496 #define CONFIG_CMD_NET
497 #define CONFIG_CMD_SCSI
498 #define CONFIG_CMD_EXT2
499 #endif
500 
501 #undef CONFIG_WATCHDOG			/* watchdog disabled */
502 
503 /*
504  * Miscellaneous configurable options
505  */
506 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
507 #define CONFIG_CMDLINE_EDITING		/* Command-line editing */
508 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
509 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
510 #if defined(CONFIG_CMD_KGDB)
511 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
512 #else
513 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
514 #endif
515 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
516 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
517 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
518 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
519 
520 /*
521  * For booting Linux, the board info and command line data
522  * have to be in the first 8 MB of memory, since this is
523  * the maximum mapped by the Linux kernel during initialization.
524  */
525 #define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
526 
527 /*
528  * Internal Definitions
529  *
530  * Boot Flags
531  */
532 #define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
533 #define BOOTFLAG_WARM	0x02		/* Software reboot */
534 
535 #if defined(CONFIG_CMD_KGDB)
536 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
537 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
538 #endif
539 
540 /*
541  * Environment Configuration
542  */
543 
544 /* The mac addresses for all ethernet interface */
545 #if defined(CONFIG_TSEC_ENET)
546 #define CONFIG_HAS_ETH0
547 #define CONFIG_ETHADDR	00:E0:0C:02:00:FD
548 #define CONFIG_HAS_ETH1
549 #define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
550 #define CONFIG_HAS_ETH2
551 #define CONFIG_ETH2ADDR	00:E0:0C:02:02:FD
552 #define CONFIG_HAS_ETH3
553 #define CONFIG_ETH3ADDR	00:E0:0C:02:03:FD
554 #endif
555 
556 #define CONFIG_IPADDR		192.168.1.254
557 
558 #define CONFIG_HOSTNAME		unknown
559 #define CONFIG_ROOTPATH		/opt/nfsroot
560 #define CONFIG_BOOTFILE		uImage
561 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
562 
563 #define CONFIG_SERVERIP		192.168.1.1
564 #define CONFIG_GATEWAYIP	192.168.1.1
565 #define CONFIG_NETMASK		255.255.255.0
566 
567 /* default location for tftp and bootm */
568 #define CONFIG_LOADADDR		1000000
569 
570 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
571 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
572 
573 #define CONFIG_BAUDRATE	115200
574 
575 #define	CONFIG_EXTRA_ENV_SETTINGS				\
576  "memctl_intlv_ctl=2\0"						\
577  "netdev=eth0\0"						\
578  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
579  "tftpflash=tftpboot $loadaddr $uboot; "			\
580 	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
581 	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
582 	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
583 	"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
584 	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
585  "consoledev=ttyS0\0"				\
586  "ramdiskaddr=2000000\0"			\
587  "ramdiskfile=8572ds/ramdisk.uboot\0"		\
588  "fdtaddr=c00000\0"				\
589  "fdtfile=8572ds/mpc8572ds.dtb\0"		\
590  "bdev=sda3\0"
591 
592 #define CONFIG_HDBOOT				\
593  "setenv bootargs root=/dev/$bdev rw "		\
594  "console=$consoledev,$baudrate $othbootargs;"	\
595  "tftp $loadaddr $bootfile;"			\
596  "tftp $fdtaddr $fdtfile;"			\
597  "bootm $loadaddr - $fdtaddr"
598 
599 #define CONFIG_NFSBOOTCOMMAND		\
600  "setenv bootargs root=/dev/nfs rw "	\
601  "nfsroot=$serverip:$rootpath "		\
602  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
603  "console=$consoledev,$baudrate $othbootargs;"	\
604  "tftp $loadaddr $bootfile;"		\
605  "tftp $fdtaddr $fdtfile;"		\
606  "bootm $loadaddr - $fdtaddr"
607 
608 #define CONFIG_RAMBOOTCOMMAND		\
609  "setenv bootargs root=/dev/ram rw "	\
610  "console=$consoledev,$baudrate $othbootargs;"	\
611  "tftp $ramdiskaddr $ramdiskfile;"	\
612  "tftp $loadaddr $bootfile;"		\
613  "tftp $fdtaddr $fdtfile;"		\
614  "bootm $loadaddr $ramdiskaddr $fdtaddr"
615 
616 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
617 
618 #endif	/* __CONFIG_H */
619