1 /* 2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8572ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifdef CONFIG_36BIT 17 #define CONFIG_PHYS_64BIT 18 #endif 19 20 #ifdef CONFIG_NAND 21 #define CONFIG_NAND_U_BOOT 22 #define CONFIG_RAMBOOT_NAND 23 #ifdef CONFIG_NAND_SPL 24 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 25 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 26 #else 27 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds 28 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 29 #endif /* CONFIG_NAND_SPL */ 30 #endif 31 32 #ifndef CONFIG_SYS_TEXT_BASE 33 #define CONFIG_SYS_TEXT_BASE 0xeff80000 34 #endif 35 36 #ifndef CONFIG_RESET_VECTOR_ADDRESS 37 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 38 #endif 39 40 #ifndef CONFIG_SYS_MONITOR_BASE 41 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 42 #endif 43 44 /* High Level Configuration Options */ 45 #define CONFIG_BOOKE 1 /* BOOKE */ 46 #define CONFIG_E500 1 /* BOOKE e500 family */ 47 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 48 #define CONFIG_MPC8572 1 49 #define CONFIG_MPC8572DS 1 50 #define CONFIG_MP 1 /* support multiple processors */ 51 52 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 53 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 54 #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 55 #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 56 #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 57 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 58 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 59 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 60 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 61 62 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 63 64 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 65 #define CONFIG_ENV_OVERWRITE 66 67 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 68 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 69 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 70 71 /* 72 * These can be toggled for performance analysis, otherwise use default. 73 */ 74 #define CONFIG_L2_CACHE /* toggle L2 cache */ 75 #define CONFIG_BTB /* toggle branch predition */ 76 77 #define CONFIG_ENABLE_36BIT_PHYS 1 78 79 #ifdef CONFIG_PHYS_64BIT 80 #define CONFIG_ADDR_MAP 1 81 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 82 #endif 83 84 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 85 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 86 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 87 88 /* 89 * Config the L2 Cache as L2 SRAM 90 */ 91 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 92 #ifdef CONFIG_PHYS_64BIT 93 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 94 #else 95 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 96 #endif 97 #define CONFIG_SYS_L2_SIZE (512 << 10) 98 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 99 100 #define CONFIG_SYS_CCSRBAR 0xffe00000 101 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 102 103 #if defined(CONFIG_NAND_SPL) 104 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 105 #endif 106 107 /* DDR Setup */ 108 #define CONFIG_VERY_BIG_RAM 109 #define CONFIG_SYS_FSL_DDR2 110 #undef CONFIG_FSL_DDR_INTERACTIVE 111 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 112 #define CONFIG_DDR_SPD 113 114 #define CONFIG_DDR_ECC 115 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 116 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 117 118 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 120 121 #define CONFIG_NUM_DDR_CONTROLLERS 2 122 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 123 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 124 125 /* I2C addresses of SPD EEPROMs */ 126 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 127 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 128 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 129 130 /* These are used when DDR doesn't use SPD. */ 131 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 132 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 133 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 134 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 135 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 136 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 137 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 138 #define CONFIG_SYS_DDR_MODE_1 0x00440462 139 #define CONFIG_SYS_DDR_MODE_2 0x00000000 140 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 141 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 142 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 143 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 144 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 145 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 146 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 147 148 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 149 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 150 #define CONFIG_SYS_DDR_SBE 0x00010000 151 152 /* 153 * Make sure required options are set 154 */ 155 #ifndef CONFIG_SPD_EEPROM 156 #error ("CONFIG_SPD_EEPROM is required") 157 #endif 158 159 #undef CONFIG_CLOCKS_IN_MHZ 160 161 /* 162 * Memory map 163 * 164 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 165 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 166 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 167 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 168 * 169 * Localbus cacheable (TBD) 170 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 171 * 172 * Localbus non-cacheable 173 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 174 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 175 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 176 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 177 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 178 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 179 */ 180 181 /* 182 * Local Bus Definitions 183 */ 184 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 185 #ifdef CONFIG_PHYS_64BIT 186 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 187 #else 188 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 189 #endif 190 191 192 #define CONFIG_FLASH_BR_PRELIM \ 193 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 194 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 195 196 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 197 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 198 199 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 200 #define CONFIG_SYS_FLASH_QUIET_TEST 201 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 202 203 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 204 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 205 #undef CONFIG_SYS_FLASH_CHECKSUM 206 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 207 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 208 209 #if defined(CONFIG_RAMBOOT_NAND) 210 #define CONFIG_SYS_RAMBOOT 211 #define CONFIG_SYS_EXTRA_ENV_RELOC 212 #else 213 #undef CONFIG_SYS_RAMBOOT 214 #endif 215 216 #define CONFIG_FLASH_CFI_DRIVER 217 #define CONFIG_SYS_FLASH_CFI 218 #define CONFIG_SYS_FLASH_EMPTY_INFO 219 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 220 221 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 222 223 #define CONFIG_HWCONFIG /* enable hwconfig */ 224 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 225 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 226 #ifdef CONFIG_PHYS_64BIT 227 #define PIXIS_BASE_PHYS 0xfffdf0000ull 228 #else 229 #define PIXIS_BASE_PHYS PIXIS_BASE 230 #endif 231 232 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 233 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 234 235 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 236 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 237 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 238 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 239 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 240 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 241 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 242 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 243 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 244 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 245 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 246 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 247 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 248 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 249 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 250 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 251 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 252 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 253 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 254 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 255 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 256 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 257 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 258 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 259 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 260 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 261 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 262 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 263 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 264 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 265 #define PIXIS_LED 0x25 /* LED Register */ 266 267 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 268 269 /* old pixis referenced names */ 270 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 271 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 272 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 273 #define PIXIS_VSPEED2_TSEC1SER 0x8 274 #define PIXIS_VSPEED2_TSEC2SER 0x4 275 #define PIXIS_VSPEED2_TSEC3SER 0x2 276 #define PIXIS_VSPEED2_TSEC4SER 0x1 277 #define PIXIS_VCFGEN1_TSEC1SER 0x20 278 #define PIXIS_VCFGEN1_TSEC2SER 0x20 279 #define PIXIS_VCFGEN1_TSEC3SER 0x20 280 #define PIXIS_VCFGEN1_TSEC4SER 0x20 281 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 282 | PIXIS_VSPEED2_TSEC2SER \ 283 | PIXIS_VSPEED2_TSEC3SER \ 284 | PIXIS_VSPEED2_TSEC4SER) 285 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 286 | PIXIS_VCFGEN1_TSEC2SER \ 287 | PIXIS_VCFGEN1_TSEC3SER \ 288 | PIXIS_VCFGEN1_TSEC4SER) 289 290 #define CONFIG_SYS_INIT_RAM_LOCK 1 291 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 292 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 293 294 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 295 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 296 297 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 298 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 299 300 #ifndef CONFIG_NAND_SPL 301 #define CONFIG_SYS_NAND_BASE 0xffa00000 302 #ifdef CONFIG_PHYS_64BIT 303 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 304 #else 305 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 306 #endif 307 #else 308 #define CONFIG_SYS_NAND_BASE 0xfff00000 309 #ifdef CONFIG_PHYS_64BIT 310 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 311 #else 312 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 313 #endif 314 #endif 315 316 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 317 CONFIG_SYS_NAND_BASE + 0x40000, \ 318 CONFIG_SYS_NAND_BASE + 0x80000,\ 319 CONFIG_SYS_NAND_BASE + 0xC0000} 320 #define CONFIG_SYS_MAX_NAND_DEVICE 4 321 #define CONFIG_MTD_NAND_VERIFY_WRITE 322 #define CONFIG_CMD_NAND 1 323 #define CONFIG_NAND_FSL_ELBC 1 324 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 325 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 326 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 327 328 /* NAND boot: 4K NAND loader config */ 329 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 330 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 331 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 332 #define CONFIG_SYS_NAND_U_BOOT_START \ 333 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 334 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 335 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 336 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 337 338 339 /* NAND flash config */ 340 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 341 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 342 | BR_PS_8 /* Port Size = 8 bit */ \ 343 | BR_MS_FCM /* MSEL = FCM */ \ 344 | BR_V) /* valid */ 345 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 346 | OR_FCM_PGS /* Large Page*/ \ 347 | OR_FCM_CSCT \ 348 | OR_FCM_CST \ 349 | OR_FCM_CHT \ 350 | OR_FCM_SCY_1 \ 351 | OR_FCM_TRLX \ 352 | OR_FCM_EHTR) 353 354 #ifdef CONFIG_RAMBOOT_NAND 355 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 356 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 357 #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 358 #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 359 #else 360 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 361 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 362 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 363 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 364 #endif 365 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 366 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 367 | BR_PS_8 /* Port Size = 8 bit */ \ 368 | BR_MS_FCM /* MSEL = FCM */ \ 369 | BR_V) /* valid */ 370 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 371 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 372 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 373 | BR_PS_8 /* Port Size = 8 bit */ \ 374 | BR_MS_FCM /* MSEL = FCM */ \ 375 | BR_V) /* valid */ 376 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 377 378 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 379 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 380 | BR_PS_8 /* Port Size = 8 bit */ \ 381 | BR_MS_FCM /* MSEL = FCM */ \ 382 | BR_V) /* valid */ 383 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 384 385 386 /* Serial Port - controlled on board with jumper J8 387 * open - index 2 388 * shorted - index 1 389 */ 390 #define CONFIG_CONS_INDEX 1 391 #define CONFIG_SYS_NS16550 392 #define CONFIG_SYS_NS16550_SERIAL 393 #define CONFIG_SYS_NS16550_REG_SIZE 1 394 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 395 #ifdef CONFIG_NAND_SPL 396 #define CONFIG_NS16550_MIN_FUNCTIONS 397 #endif 398 399 #define CONFIG_SYS_BAUDRATE_TABLE \ 400 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 401 402 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 403 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 404 405 /* Use the HUSH parser */ 406 #define CONFIG_SYS_HUSH_PARSER 407 408 /* 409 * Pass open firmware flat tree 410 */ 411 #define CONFIG_OF_LIBFDT 1 412 #define CONFIG_OF_BOARD_SETUP 1 413 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 414 415 /* new uImage format support */ 416 #define CONFIG_FIT 1 417 #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 418 419 /* I2C */ 420 #define CONFIG_SYS_I2C 421 #define CONFIG_SYS_I2C_FSL 422 #define CONFIG_SYS_FSL_I2C_SPEED 400000 423 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 424 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 425 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 426 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 427 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 428 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 429 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 430 431 /* 432 * I2C2 EEPROM 433 */ 434 #define CONFIG_ID_EEPROM 435 #ifdef CONFIG_ID_EEPROM 436 #define CONFIG_SYS_I2C_EEPROM_NXID 437 #endif 438 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 439 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 440 #define CONFIG_SYS_EEPROM_BUS_NUM 1 441 442 /* 443 * General PCI 444 * Memory space is mapped 1-1, but I/O space must start from 0. 445 */ 446 447 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 448 #define CONFIG_SYS_PCIE3_NAME "ULI" 449 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 450 #ifdef CONFIG_PHYS_64BIT 451 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 452 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 453 #else 454 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 455 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 456 #endif 457 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 458 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 459 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 460 #ifdef CONFIG_PHYS_64BIT 461 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 462 #else 463 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 464 #endif 465 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 466 467 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 468 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 469 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 470 #ifdef CONFIG_PHYS_64BIT 471 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 472 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 473 #else 474 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 475 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 476 #endif 477 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 478 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 479 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 480 #ifdef CONFIG_PHYS_64BIT 481 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 482 #else 483 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 484 #endif 485 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 486 487 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 488 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 489 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 490 #ifdef CONFIG_PHYS_64BIT 491 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 492 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 493 #else 494 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 495 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 496 #endif 497 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 498 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 499 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 500 #ifdef CONFIG_PHYS_64BIT 501 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 502 #else 503 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 504 #endif 505 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 506 507 #if defined(CONFIG_PCI) 508 509 /*PCIE video card used*/ 510 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 511 512 /* video */ 513 #define CONFIG_VIDEO 514 515 #if defined(CONFIG_VIDEO) 516 #define CONFIG_BIOSEMU 517 #define CONFIG_CFB_CONSOLE 518 #define CONFIG_VIDEO_SW_CURSOR 519 #define CONFIG_VGA_AS_SINGLE_DEVICE 520 #define CONFIG_ATI_RADEON_FB 521 #define CONFIG_VIDEO_LOGO 522 /*#define CONFIG_CONSOLE_CURSOR*/ 523 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 524 #endif 525 526 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 527 528 #undef CONFIG_EEPRO100 529 #undef CONFIG_TULIP 530 #undef CONFIG_RTL8139 531 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 532 533 #ifndef CONFIG_PCI_PNP 534 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 535 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 536 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 537 #endif 538 539 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 540 #define CONFIG_DOS_PARTITION 541 #define CONFIG_SCSI_AHCI 542 543 #ifdef CONFIG_SCSI_AHCI 544 #define CONFIG_LIBATA 545 #define CONFIG_SATA_ULI5288 546 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 547 #define CONFIG_SYS_SCSI_MAX_LUN 1 548 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 549 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 550 #endif /* SCSI */ 551 552 #endif /* CONFIG_PCI */ 553 554 555 #if defined(CONFIG_TSEC_ENET) 556 557 #define CONFIG_MII 1 /* MII PHY management */ 558 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 559 #define CONFIG_TSEC1 1 560 #define CONFIG_TSEC1_NAME "eTSEC1" 561 #define CONFIG_TSEC2 1 562 #define CONFIG_TSEC2_NAME "eTSEC2" 563 #define CONFIG_TSEC3 1 564 #define CONFIG_TSEC3_NAME "eTSEC3" 565 #define CONFIG_TSEC4 1 566 #define CONFIG_TSEC4_NAME "eTSEC4" 567 568 #define CONFIG_PIXIS_SGMII_CMD 569 #define CONFIG_FSL_SGMII_RISER 1 570 #define SGMII_RISER_PHY_OFFSET 0x1c 571 572 #ifdef CONFIG_FSL_SGMII_RISER 573 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 574 #endif 575 576 #define TSEC1_PHY_ADDR 0 577 #define TSEC2_PHY_ADDR 1 578 #define TSEC3_PHY_ADDR 2 579 #define TSEC4_PHY_ADDR 3 580 581 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 582 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 583 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 584 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 585 586 #define TSEC1_PHYIDX 0 587 #define TSEC2_PHYIDX 0 588 #define TSEC3_PHYIDX 0 589 #define TSEC4_PHYIDX 0 590 591 #define CONFIG_ETHPRIME "eTSEC1" 592 593 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 594 #endif /* CONFIG_TSEC_ENET */ 595 596 /* 597 * Environment 598 */ 599 600 #if defined(CONFIG_SYS_RAMBOOT) 601 #if defined(CONFIG_RAMBOOT_NAND) 602 #define CONFIG_ENV_IS_IN_NAND 1 603 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 604 #define CONFIG_ENV_OFFSET ((512 * 1024)\ 605 + CONFIG_SYS_NAND_BLOCK_SIZE) 606 #endif 607 608 #else 609 #define CONFIG_ENV_IS_IN_FLASH 1 610 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 611 #define CONFIG_ENV_ADDR 0xfff80000 612 #else 613 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 614 #endif 615 #define CONFIG_ENV_SIZE 0x2000 616 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 617 #endif 618 619 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 620 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 621 622 /* 623 * Command line configuration. 624 */ 625 #include <config_cmd_default.h> 626 627 #define CONFIG_CMD_ERRATA 628 #define CONFIG_CMD_IRQ 629 #define CONFIG_CMD_PING 630 #define CONFIG_CMD_I2C 631 #define CONFIG_CMD_MII 632 #define CONFIG_CMD_ELF 633 #define CONFIG_CMD_SETEXPR 634 #define CONFIG_CMD_REGINFO 635 636 #if defined(CONFIG_PCI) 637 #define CONFIG_CMD_PCI 638 #define CONFIG_CMD_NET 639 #define CONFIG_CMD_SCSI 640 #define CONFIG_CMD_EXT2 641 #endif 642 643 /* 644 * USB 645 */ 646 #define CONFIG_USB_EHCI 647 648 #ifdef CONFIG_USB_EHCI 649 #define CONFIG_CMD_USB 650 #define CONFIG_USB_EHCI_PCI 651 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 652 #define CONFIG_USB_STORAGE 653 #define CONFIG_PCI_EHCI_DEVICE 0 654 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 655 #endif 656 657 #undef CONFIG_WATCHDOG /* watchdog disabled */ 658 659 /* 660 * Miscellaneous configurable options 661 */ 662 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 663 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 664 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 665 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 666 #if defined(CONFIG_CMD_KGDB) 667 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 668 #else 669 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 670 #endif 671 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 672 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 673 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 674 675 /* 676 * For booting Linux, the board info and command line data 677 * have to be in the first 64 MB of memory, since this is 678 * the maximum mapped by the Linux kernel during initialization. 679 */ 680 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 681 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 682 683 #if defined(CONFIG_CMD_KGDB) 684 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 685 #endif 686 687 /* 688 * Environment Configuration 689 */ 690 691 /* The mac addresses for all ethernet interface */ 692 #if defined(CONFIG_TSEC_ENET) 693 #define CONFIG_HAS_ETH0 694 #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 695 #define CONFIG_HAS_ETH1 696 #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 697 #define CONFIG_HAS_ETH2 698 #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 699 #define CONFIG_HAS_ETH3 700 #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 701 #endif 702 703 #define CONFIG_IPADDR 192.168.1.254 704 705 #define CONFIG_HOSTNAME unknown 706 #define CONFIG_ROOTPATH "/opt/nfsroot" 707 #define CONFIG_BOOTFILE "uImage" 708 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 709 710 #define CONFIG_SERVERIP 192.168.1.1 711 #define CONFIG_GATEWAYIP 192.168.1.1 712 #define CONFIG_NETMASK 255.255.255.0 713 714 /* default location for tftp and bootm */ 715 #define CONFIG_LOADADDR 1000000 716 717 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 718 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 719 720 #define CONFIG_BAUDRATE 115200 721 722 #define CONFIG_EXTRA_ENV_SETTINGS \ 723 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 724 "netdev=eth0\0" \ 725 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 726 "tftpflash=tftpboot $loadaddr $uboot; " \ 727 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 728 " +$filesize; " \ 729 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 730 " +$filesize; " \ 731 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 732 " $filesize; " \ 733 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 734 " +$filesize; " \ 735 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 736 " $filesize\0" \ 737 "consoledev=ttyS0\0" \ 738 "ramdiskaddr=2000000\0" \ 739 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 740 "fdtaddr=c00000\0" \ 741 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 742 "bdev=sda3\0" 743 744 #define CONFIG_HDBOOT \ 745 "setenv bootargs root=/dev/$bdev rw " \ 746 "console=$consoledev,$baudrate $othbootargs;" \ 747 "tftp $loadaddr $bootfile;" \ 748 "tftp $fdtaddr $fdtfile;" \ 749 "bootm $loadaddr - $fdtaddr" 750 751 #define CONFIG_NFSBOOTCOMMAND \ 752 "setenv bootargs root=/dev/nfs rw " \ 753 "nfsroot=$serverip:$rootpath " \ 754 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 755 "console=$consoledev,$baudrate $othbootargs;" \ 756 "tftp $loadaddr $bootfile;" \ 757 "tftp $fdtaddr $fdtfile;" \ 758 "bootm $loadaddr - $fdtaddr" 759 760 #define CONFIG_RAMBOOTCOMMAND \ 761 "setenv bootargs root=/dev/ram rw " \ 762 "console=$consoledev,$baudrate $othbootargs;" \ 763 "tftp $ramdiskaddr $ramdiskfile;" \ 764 "tftp $loadaddr $bootfile;" \ 765 "tftp $fdtaddr $fdtfile;" \ 766 "bootm $loadaddr $ramdiskaddr $fdtaddr" 767 768 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 769 770 #endif /* __CONFIG_H */ 771