1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * mpc8572ds board configuration file 8 * 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifndef CONFIG_RESET_VECTOR_ADDRESS 16 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 17 #endif 18 19 #ifndef CONFIG_SYS_MONITOR_BASE 20 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 21 #endif 22 23 /* High Level Configuration Options */ 24 25 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 26 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 27 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 28 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 29 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 30 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 32 33 #define CONFIG_ENV_OVERWRITE 34 35 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 36 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 37 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 38 39 /* 40 * These can be toggled for performance analysis, otherwise use default. 41 */ 42 #define CONFIG_L2_CACHE /* toggle L2 cache */ 43 #define CONFIG_BTB /* toggle branch predition */ 44 45 #define CONFIG_ENABLE_36BIT_PHYS 1 46 47 #ifdef CONFIG_PHYS_64BIT 48 #define CONFIG_ADDR_MAP 1 49 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 50 #endif 51 52 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 53 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 54 55 /* 56 * Config the L2 Cache as L2 SRAM 57 */ 58 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 59 #ifdef CONFIG_PHYS_64BIT 60 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 61 #else 62 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 63 #endif 64 #define CONFIG_SYS_L2_SIZE (512 << 10) 65 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 66 67 #define CONFIG_SYS_CCSRBAR 0xffe00000 68 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 69 70 #if defined(CONFIG_NAND_SPL) 71 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 72 #endif 73 74 /* DDR Setup */ 75 #define CONFIG_VERY_BIG_RAM 76 #undef CONFIG_FSL_DDR_INTERACTIVE 77 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 78 #define CONFIG_DDR_SPD 79 80 #define CONFIG_DDR_ECC 81 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 82 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 83 84 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 85 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 86 87 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 88 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 89 90 /* I2C addresses of SPD EEPROMs */ 91 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 92 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 93 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 94 95 /* These are used when DDR doesn't use SPD. */ 96 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 97 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 98 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 99 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 100 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 101 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 102 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 103 #define CONFIG_SYS_DDR_MODE_1 0x00440462 104 #define CONFIG_SYS_DDR_MODE_2 0x00000000 105 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 106 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 107 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 108 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 109 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 110 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 111 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 112 113 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 114 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 115 #define CONFIG_SYS_DDR_SBE 0x00010000 116 117 /* 118 * Make sure required options are set 119 */ 120 #ifndef CONFIG_SPD_EEPROM 121 #error ("CONFIG_SPD_EEPROM is required") 122 #endif 123 124 #undef CONFIG_CLOCKS_IN_MHZ 125 126 /* 127 * Memory map 128 * 129 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 130 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 131 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 132 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 133 * 134 * Localbus cacheable (TBD) 135 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 136 * 137 * Localbus non-cacheable 138 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 139 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 140 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 141 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 142 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 143 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 144 */ 145 146 /* 147 * Local Bus Definitions 148 */ 149 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 150 #ifdef CONFIG_PHYS_64BIT 151 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 152 #else 153 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 154 #endif 155 156 #define CONFIG_FLASH_BR_PRELIM \ 157 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 158 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 159 160 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 161 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 162 163 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 164 #define CONFIG_SYS_FLASH_QUIET_TEST 165 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 166 167 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 168 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 169 #undef CONFIG_SYS_FLASH_CHECKSUM 170 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 171 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 172 173 #undef CONFIG_SYS_RAMBOOT 174 175 #define CONFIG_SYS_FLASH_EMPTY_INFO 176 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 177 178 #define CONFIG_HWCONFIG /* enable hwconfig */ 179 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 180 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 181 #ifdef CONFIG_PHYS_64BIT 182 #define PIXIS_BASE_PHYS 0xfffdf0000ull 183 #else 184 #define PIXIS_BASE_PHYS PIXIS_BASE 185 #endif 186 187 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 188 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 189 190 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 191 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 192 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 193 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 194 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 195 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 196 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 197 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 198 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 199 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 200 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 201 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 202 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 203 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 204 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 205 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 206 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 207 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 208 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 209 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 210 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 211 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 212 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 213 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 214 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 215 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 216 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 217 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 218 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 219 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 220 #define PIXIS_LED 0x25 /* LED Register */ 221 222 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 223 224 /* old pixis referenced names */ 225 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 226 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 227 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 228 #define PIXIS_VSPEED2_TSEC1SER 0x8 229 #define PIXIS_VSPEED2_TSEC2SER 0x4 230 #define PIXIS_VSPEED2_TSEC3SER 0x2 231 #define PIXIS_VSPEED2_TSEC4SER 0x1 232 #define PIXIS_VCFGEN1_TSEC1SER 0x20 233 #define PIXIS_VCFGEN1_TSEC2SER 0x20 234 #define PIXIS_VCFGEN1_TSEC3SER 0x20 235 #define PIXIS_VCFGEN1_TSEC4SER 0x20 236 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 237 | PIXIS_VSPEED2_TSEC2SER \ 238 | PIXIS_VSPEED2_TSEC3SER \ 239 | PIXIS_VSPEED2_TSEC4SER) 240 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 241 | PIXIS_VCFGEN1_TSEC2SER \ 242 | PIXIS_VCFGEN1_TSEC3SER \ 243 | PIXIS_VCFGEN1_TSEC4SER) 244 245 #define CONFIG_SYS_INIT_RAM_LOCK 1 246 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 247 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 248 249 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 250 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 251 252 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 253 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 254 255 #ifndef CONFIG_NAND_SPL 256 #define CONFIG_SYS_NAND_BASE 0xffa00000 257 #ifdef CONFIG_PHYS_64BIT 258 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 259 #else 260 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 261 #endif 262 #else 263 #define CONFIG_SYS_NAND_BASE 0xfff00000 264 #ifdef CONFIG_PHYS_64BIT 265 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 266 #else 267 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 268 #endif 269 #endif 270 271 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 272 CONFIG_SYS_NAND_BASE + 0x40000, \ 273 CONFIG_SYS_NAND_BASE + 0x80000,\ 274 CONFIG_SYS_NAND_BASE + 0xC0000} 275 #define CONFIG_SYS_MAX_NAND_DEVICE 4 276 #define CONFIG_NAND_FSL_ELBC 1 277 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 278 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 279 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 280 281 /* NAND boot: 4K NAND loader config */ 282 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 283 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 284 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 285 #define CONFIG_SYS_NAND_U_BOOT_START \ 286 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 287 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 288 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 289 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 290 291 /* NAND flash config */ 292 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 293 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 294 | BR_PS_8 /* Port Size = 8 bit */ \ 295 | BR_MS_FCM /* MSEL = FCM */ \ 296 | BR_V) /* valid */ 297 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 298 | OR_FCM_PGS /* Large Page*/ \ 299 | OR_FCM_CSCT \ 300 | OR_FCM_CST \ 301 | OR_FCM_CHT \ 302 | OR_FCM_SCY_1 \ 303 | OR_FCM_TRLX \ 304 | OR_FCM_EHTR) 305 306 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 307 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 308 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 309 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 310 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 311 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 312 | BR_PS_8 /* Port Size = 8 bit */ \ 313 | BR_MS_FCM /* MSEL = FCM */ \ 314 | BR_V) /* valid */ 315 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 316 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 317 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 318 | BR_PS_8 /* Port Size = 8 bit */ \ 319 | BR_MS_FCM /* MSEL = FCM */ \ 320 | BR_V) /* valid */ 321 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 322 323 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 324 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 325 | BR_PS_8 /* Port Size = 8 bit */ \ 326 | BR_MS_FCM /* MSEL = FCM */ \ 327 | BR_V) /* valid */ 328 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 329 330 /* Serial Port - controlled on board with jumper J8 331 * open - index 2 332 * shorted - index 1 333 */ 334 #define CONFIG_SYS_NS16550_SERIAL 335 #define CONFIG_SYS_NS16550_REG_SIZE 1 336 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 337 #ifdef CONFIG_NAND_SPL 338 #define CONFIG_NS16550_MIN_FUNCTIONS 339 #endif 340 341 #define CONFIG_SYS_BAUDRATE_TABLE \ 342 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 343 344 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 345 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 346 347 /* I2C */ 348 #define CONFIG_SYS_I2C 349 #define CONFIG_SYS_I2C_FSL 350 #define CONFIG_SYS_FSL_I2C_SPEED 400000 351 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 352 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 353 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 354 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 355 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 356 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 357 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 358 359 /* 360 * I2C2 EEPROM 361 */ 362 #define CONFIG_ID_EEPROM 363 #ifdef CONFIG_ID_EEPROM 364 #define CONFIG_SYS_I2C_EEPROM_NXID 365 #endif 366 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 367 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 368 #define CONFIG_SYS_EEPROM_BUS_NUM 1 369 370 /* 371 * General PCI 372 * Memory space is mapped 1-1, but I/O space must start from 0. 373 */ 374 375 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 376 #define CONFIG_SYS_PCIE3_NAME "ULI" 377 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 378 #ifdef CONFIG_PHYS_64BIT 379 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 380 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 381 #else 382 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 383 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 384 #endif 385 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 386 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 387 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 388 #ifdef CONFIG_PHYS_64BIT 389 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 390 #else 391 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 392 #endif 393 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 394 395 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 396 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 397 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 398 #ifdef CONFIG_PHYS_64BIT 399 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 400 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 401 #else 402 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 403 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 404 #endif 405 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 406 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 407 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 408 #ifdef CONFIG_PHYS_64BIT 409 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 410 #else 411 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 412 #endif 413 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 414 415 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 416 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 417 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 418 #ifdef CONFIG_PHYS_64BIT 419 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 420 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 421 #else 422 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 423 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 424 #endif 425 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 426 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 427 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 428 #ifdef CONFIG_PHYS_64BIT 429 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 430 #else 431 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 432 #endif 433 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 434 435 #if defined(CONFIG_PCI) 436 437 /*PCIE video card used*/ 438 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 439 440 /* video */ 441 442 #if defined(CONFIG_VIDEO) 443 #define CONFIG_BIOSEMU 444 #define CONFIG_ATI_RADEON_FB 445 #define CONFIG_VIDEO_LOGO 446 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 447 #endif 448 449 #undef CONFIG_EEPRO100 450 #undef CONFIG_TULIP 451 452 #ifndef CONFIG_PCI_PNP 453 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 454 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 455 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 456 #endif 457 458 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 459 460 #ifdef CONFIG_SCSI_AHCI 461 #define CONFIG_SATA_ULI5288 462 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 463 #define CONFIG_SYS_SCSI_MAX_LUN 1 464 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 465 #endif /* SCSI */ 466 467 #endif /* CONFIG_PCI */ 468 469 #if defined(CONFIG_TSEC_ENET) 470 471 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 472 #define CONFIG_TSEC1 1 473 #define CONFIG_TSEC1_NAME "eTSEC1" 474 #define CONFIG_TSEC2 1 475 #define CONFIG_TSEC2_NAME "eTSEC2" 476 #define CONFIG_TSEC3 1 477 #define CONFIG_TSEC3_NAME "eTSEC3" 478 #define CONFIG_TSEC4 1 479 #define CONFIG_TSEC4_NAME "eTSEC4" 480 481 #define CONFIG_PIXIS_SGMII_CMD 482 #define CONFIG_FSL_SGMII_RISER 1 483 #define SGMII_RISER_PHY_OFFSET 0x1c 484 485 #ifdef CONFIG_FSL_SGMII_RISER 486 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 487 #endif 488 489 #define TSEC1_PHY_ADDR 0 490 #define TSEC2_PHY_ADDR 1 491 #define TSEC3_PHY_ADDR 2 492 #define TSEC4_PHY_ADDR 3 493 494 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 495 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 496 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 497 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 498 499 #define TSEC1_PHYIDX 0 500 #define TSEC2_PHYIDX 0 501 #define TSEC3_PHYIDX 0 502 #define TSEC4_PHYIDX 0 503 504 #define CONFIG_ETHPRIME "eTSEC1" 505 #endif /* CONFIG_TSEC_ENET */ 506 507 /* 508 * Environment 509 */ 510 511 #if defined(CONFIG_SYS_RAMBOOT) 512 513 #else 514 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 515 #define CONFIG_ENV_ADDR 0xfff80000 516 #else 517 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 518 #endif 519 #define CONFIG_ENV_SIZE 0x2000 520 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 521 #endif 522 523 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 524 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 525 526 /* 527 * USB 528 */ 529 530 #ifdef CONFIG_USB_EHCI_HCD 531 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 532 #define CONFIG_PCI_EHCI_DEVICE 0 533 #endif 534 535 #undef CONFIG_WATCHDOG /* watchdog disabled */ 536 537 /* 538 * Miscellaneous configurable options 539 */ 540 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 541 542 /* 543 * For booting Linux, the board info and command line data 544 * have to be in the first 64 MB of memory, since this is 545 * the maximum mapped by the Linux kernel during initialization. 546 */ 547 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 548 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 549 550 #if defined(CONFIG_CMD_KGDB) 551 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 552 #endif 553 554 /* 555 * Environment Configuration 556 */ 557 #if defined(CONFIG_TSEC_ENET) 558 #define CONFIG_HAS_ETH0 559 #define CONFIG_HAS_ETH1 560 #define CONFIG_HAS_ETH2 561 #define CONFIG_HAS_ETH3 562 #endif 563 564 #define CONFIG_IPADDR 192.168.1.254 565 566 #define CONFIG_HOSTNAME "unknown" 567 #define CONFIG_ROOTPATH "/opt/nfsroot" 568 #define CONFIG_BOOTFILE "uImage" 569 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 570 571 #define CONFIG_SERVERIP 192.168.1.1 572 #define CONFIG_GATEWAYIP 192.168.1.1 573 #define CONFIG_NETMASK 255.255.255.0 574 575 /* default location for tftp and bootm */ 576 #define CONFIG_LOADADDR 1000000 577 578 #define CONFIG_EXTRA_ENV_SETTINGS \ 579 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 580 "netdev=eth0\0" \ 581 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 582 "tftpflash=tftpboot $loadaddr $uboot; " \ 583 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 584 " +$filesize; " \ 585 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 586 " +$filesize; " \ 587 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 588 " $filesize; " \ 589 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 590 " +$filesize; " \ 591 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 592 " $filesize\0" \ 593 "consoledev=ttyS0\0" \ 594 "ramdiskaddr=2000000\0" \ 595 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 596 "fdtaddr=1e00000\0" \ 597 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 598 "bdev=sda3\0" 599 600 #define CONFIG_HDBOOT \ 601 "setenv bootargs root=/dev/$bdev rw " \ 602 "console=$consoledev,$baudrate $othbootargs;" \ 603 "tftp $loadaddr $bootfile;" \ 604 "tftp $fdtaddr $fdtfile;" \ 605 "bootm $loadaddr - $fdtaddr" 606 607 #define CONFIG_NFSBOOTCOMMAND \ 608 "setenv bootargs root=/dev/nfs rw " \ 609 "nfsroot=$serverip:$rootpath " \ 610 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 611 "console=$consoledev,$baudrate $othbootargs;" \ 612 "tftp $loadaddr $bootfile;" \ 613 "tftp $fdtaddr $fdtfile;" \ 614 "bootm $loadaddr - $fdtaddr" 615 616 #define CONFIG_RAMBOOTCOMMAND \ 617 "setenv bootargs root=/dev/ram rw " \ 618 "console=$consoledev,$baudrate $othbootargs;" \ 619 "tftp $ramdiskaddr $ramdiskfile;" \ 620 "tftp $loadaddr $bootfile;" \ 621 "tftp $fdtaddr $fdtfile;" \ 622 "bootm $loadaddr $ramdiskaddr $fdtaddr" 623 624 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 625 626 #endif /* __CONFIG_H */ 627