1 /* 2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8572ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #include "../board/freescale/common/ics307_clk.h" 17 18 #ifndef CONFIG_SYS_TEXT_BASE 19 #define CONFIG_SYS_TEXT_BASE 0xeff40000 20 #endif 21 22 #ifndef CONFIG_RESET_VECTOR_ADDRESS 23 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 24 #endif 25 26 #ifndef CONFIG_SYS_MONITOR_BASE 27 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 28 #endif 29 30 /* High Level Configuration Options */ 31 #define CONFIG_BOOKE 1 /* BOOKE */ 32 #define CONFIG_E500 1 /* BOOKE e500 family */ 33 #define CONFIG_MPC8572 1 34 #define CONFIG_MPC8572DS 1 35 #define CONFIG_MP 1 /* support multiple processors */ 36 37 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 38 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 39 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 40 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 41 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 42 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 43 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 44 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 45 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 46 47 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 48 49 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 50 #define CONFIG_ENV_OVERWRITE 51 52 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 53 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 54 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 55 56 /* 57 * These can be toggled for performance analysis, otherwise use default. 58 */ 59 #define CONFIG_L2_CACHE /* toggle L2 cache */ 60 #define CONFIG_BTB /* toggle branch predition */ 61 62 #define CONFIG_ENABLE_36BIT_PHYS 1 63 64 #ifdef CONFIG_PHYS_64BIT 65 #define CONFIG_ADDR_MAP 1 66 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 67 #endif 68 69 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 70 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 71 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 72 73 /* 74 * Config the L2 Cache as L2 SRAM 75 */ 76 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 77 #ifdef CONFIG_PHYS_64BIT 78 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 79 #else 80 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 81 #endif 82 #define CONFIG_SYS_L2_SIZE (512 << 10) 83 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 84 85 #define CONFIG_SYS_CCSRBAR 0xffe00000 86 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 87 88 #if defined(CONFIG_NAND_SPL) 89 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 90 #endif 91 92 /* DDR Setup */ 93 #define CONFIG_VERY_BIG_RAM 94 #define CONFIG_SYS_FSL_DDR2 95 #undef CONFIG_FSL_DDR_INTERACTIVE 96 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 97 #define CONFIG_DDR_SPD 98 99 #define CONFIG_DDR_ECC 100 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 101 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 102 103 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 104 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 105 106 #define CONFIG_NUM_DDR_CONTROLLERS 2 107 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 108 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 109 110 /* I2C addresses of SPD EEPROMs */ 111 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 112 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 113 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 114 115 /* These are used when DDR doesn't use SPD. */ 116 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 117 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 118 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 119 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 120 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 121 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 122 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 123 #define CONFIG_SYS_DDR_MODE_1 0x00440462 124 #define CONFIG_SYS_DDR_MODE_2 0x00000000 125 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 126 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 127 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 128 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 129 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 130 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 131 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 132 133 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 134 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 135 #define CONFIG_SYS_DDR_SBE 0x00010000 136 137 /* 138 * Make sure required options are set 139 */ 140 #ifndef CONFIG_SPD_EEPROM 141 #error ("CONFIG_SPD_EEPROM is required") 142 #endif 143 144 #undef CONFIG_CLOCKS_IN_MHZ 145 146 /* 147 * Memory map 148 * 149 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 150 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 151 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 152 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 153 * 154 * Localbus cacheable (TBD) 155 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 156 * 157 * Localbus non-cacheable 158 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 159 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 160 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 161 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 162 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 163 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 164 */ 165 166 /* 167 * Local Bus Definitions 168 */ 169 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 170 #ifdef CONFIG_PHYS_64BIT 171 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 172 #else 173 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 174 #endif 175 176 #define CONFIG_FLASH_BR_PRELIM \ 177 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 178 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 179 180 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 181 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 182 183 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 184 #define CONFIG_SYS_FLASH_QUIET_TEST 185 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 186 187 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 188 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 189 #undef CONFIG_SYS_FLASH_CHECKSUM 190 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 191 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 192 193 #undef CONFIG_SYS_RAMBOOT 194 195 #define CONFIG_FLASH_CFI_DRIVER 196 #define CONFIG_SYS_FLASH_CFI 197 #define CONFIG_SYS_FLASH_EMPTY_INFO 198 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 199 200 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 201 202 #define CONFIG_HWCONFIG /* enable hwconfig */ 203 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 204 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 205 #ifdef CONFIG_PHYS_64BIT 206 #define PIXIS_BASE_PHYS 0xfffdf0000ull 207 #else 208 #define PIXIS_BASE_PHYS PIXIS_BASE 209 #endif 210 211 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 212 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 213 214 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 215 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 216 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 217 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 218 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 219 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 220 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 221 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 222 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 223 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 224 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 225 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 226 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 227 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 228 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 229 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 230 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 231 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 232 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 233 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 234 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 235 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 236 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 237 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 238 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 239 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 240 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 241 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 242 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 243 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 244 #define PIXIS_LED 0x25 /* LED Register */ 245 246 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 247 248 /* old pixis referenced names */ 249 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 250 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 251 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 252 #define PIXIS_VSPEED2_TSEC1SER 0x8 253 #define PIXIS_VSPEED2_TSEC2SER 0x4 254 #define PIXIS_VSPEED2_TSEC3SER 0x2 255 #define PIXIS_VSPEED2_TSEC4SER 0x1 256 #define PIXIS_VCFGEN1_TSEC1SER 0x20 257 #define PIXIS_VCFGEN1_TSEC2SER 0x20 258 #define PIXIS_VCFGEN1_TSEC3SER 0x20 259 #define PIXIS_VCFGEN1_TSEC4SER 0x20 260 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 261 | PIXIS_VSPEED2_TSEC2SER \ 262 | PIXIS_VSPEED2_TSEC3SER \ 263 | PIXIS_VSPEED2_TSEC4SER) 264 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 265 | PIXIS_VCFGEN1_TSEC2SER \ 266 | PIXIS_VCFGEN1_TSEC3SER \ 267 | PIXIS_VCFGEN1_TSEC4SER) 268 269 #define CONFIG_SYS_INIT_RAM_LOCK 1 270 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 271 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 272 273 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 274 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 275 276 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 277 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 278 279 #ifndef CONFIG_NAND_SPL 280 #define CONFIG_SYS_NAND_BASE 0xffa00000 281 #ifdef CONFIG_PHYS_64BIT 282 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 283 #else 284 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 285 #endif 286 #else 287 #define CONFIG_SYS_NAND_BASE 0xfff00000 288 #ifdef CONFIG_PHYS_64BIT 289 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 290 #else 291 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 292 #endif 293 #endif 294 295 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 296 CONFIG_SYS_NAND_BASE + 0x40000, \ 297 CONFIG_SYS_NAND_BASE + 0x80000,\ 298 CONFIG_SYS_NAND_BASE + 0xC0000} 299 #define CONFIG_SYS_MAX_NAND_DEVICE 4 300 #define CONFIG_CMD_NAND 1 301 #define CONFIG_NAND_FSL_ELBC 1 302 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 303 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 304 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 305 306 /* NAND boot: 4K NAND loader config */ 307 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 308 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 309 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 310 #define CONFIG_SYS_NAND_U_BOOT_START \ 311 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 312 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 313 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 314 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 315 316 /* NAND flash config */ 317 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 318 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 319 | BR_PS_8 /* Port Size = 8 bit */ \ 320 | BR_MS_FCM /* MSEL = FCM */ \ 321 | BR_V) /* valid */ 322 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 323 | OR_FCM_PGS /* Large Page*/ \ 324 | OR_FCM_CSCT \ 325 | OR_FCM_CST \ 326 | OR_FCM_CHT \ 327 | OR_FCM_SCY_1 \ 328 | OR_FCM_TRLX \ 329 | OR_FCM_EHTR) 330 331 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 332 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 333 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 334 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 335 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 336 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 337 | BR_PS_8 /* Port Size = 8 bit */ \ 338 | BR_MS_FCM /* MSEL = FCM */ \ 339 | BR_V) /* valid */ 340 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 341 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 342 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 343 | BR_PS_8 /* Port Size = 8 bit */ \ 344 | BR_MS_FCM /* MSEL = FCM */ \ 345 | BR_V) /* valid */ 346 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 347 348 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 349 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 350 | BR_PS_8 /* Port Size = 8 bit */ \ 351 | BR_MS_FCM /* MSEL = FCM */ \ 352 | BR_V) /* valid */ 353 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 354 355 /* Serial Port - controlled on board with jumper J8 356 * open - index 2 357 * shorted - index 1 358 */ 359 #define CONFIG_CONS_INDEX 1 360 #define CONFIG_SYS_NS16550_SERIAL 361 #define CONFIG_SYS_NS16550_REG_SIZE 1 362 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 363 #ifdef CONFIG_NAND_SPL 364 #define CONFIG_NS16550_MIN_FUNCTIONS 365 #endif 366 367 #define CONFIG_SYS_BAUDRATE_TABLE \ 368 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 369 370 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 371 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 372 373 /* I2C */ 374 #define CONFIG_SYS_I2C 375 #define CONFIG_SYS_I2C_FSL 376 #define CONFIG_SYS_FSL_I2C_SPEED 400000 377 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 378 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 379 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 380 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 381 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 382 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 383 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 384 385 /* 386 * I2C2 EEPROM 387 */ 388 #define CONFIG_ID_EEPROM 389 #ifdef CONFIG_ID_EEPROM 390 #define CONFIG_SYS_I2C_EEPROM_NXID 391 #endif 392 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 393 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 394 #define CONFIG_SYS_EEPROM_BUS_NUM 1 395 396 /* 397 * General PCI 398 * Memory space is mapped 1-1, but I/O space must start from 0. 399 */ 400 401 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 402 #define CONFIG_SYS_PCIE3_NAME "ULI" 403 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 404 #ifdef CONFIG_PHYS_64BIT 405 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 406 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 407 #else 408 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 409 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 410 #endif 411 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 412 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 413 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 414 #ifdef CONFIG_PHYS_64BIT 415 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 416 #else 417 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 418 #endif 419 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 420 421 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 422 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 423 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 426 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 427 #else 428 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 429 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 430 #endif 431 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 432 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 433 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 434 #ifdef CONFIG_PHYS_64BIT 435 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 436 #else 437 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 438 #endif 439 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 440 441 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 442 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 443 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 444 #ifdef CONFIG_PHYS_64BIT 445 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 446 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 447 #else 448 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 449 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 450 #endif 451 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 452 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 453 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 454 #ifdef CONFIG_PHYS_64BIT 455 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 456 #else 457 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 458 #endif 459 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 460 461 #if defined(CONFIG_PCI) 462 463 /*PCIE video card used*/ 464 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 465 466 /* video */ 467 #define CONFIG_VIDEO 468 469 #if defined(CONFIG_VIDEO) 470 #define CONFIG_BIOSEMU 471 #define CONFIG_CFB_CONSOLE 472 #define CONFIG_VIDEO_SW_CURSOR 473 #define CONFIG_VGA_AS_SINGLE_DEVICE 474 #define CONFIG_ATI_RADEON_FB 475 #define CONFIG_VIDEO_LOGO 476 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 477 #endif 478 479 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 480 481 #undef CONFIG_EEPRO100 482 #undef CONFIG_TULIP 483 484 #ifndef CONFIG_PCI_PNP 485 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 486 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 487 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 488 #endif 489 490 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 491 #define CONFIG_DOS_PARTITION 492 #define CONFIG_SCSI_AHCI 493 494 #ifdef CONFIG_SCSI_AHCI 495 #define CONFIG_LIBATA 496 #define CONFIG_SATA_ULI5288 497 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 498 #define CONFIG_SYS_SCSI_MAX_LUN 1 499 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 500 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 501 #endif /* SCSI */ 502 503 #endif /* CONFIG_PCI */ 504 505 #if defined(CONFIG_TSEC_ENET) 506 507 #define CONFIG_MII 1 /* MII PHY management */ 508 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 509 #define CONFIG_TSEC1 1 510 #define CONFIG_TSEC1_NAME "eTSEC1" 511 #define CONFIG_TSEC2 1 512 #define CONFIG_TSEC2_NAME "eTSEC2" 513 #define CONFIG_TSEC3 1 514 #define CONFIG_TSEC3_NAME "eTSEC3" 515 #define CONFIG_TSEC4 1 516 #define CONFIG_TSEC4_NAME "eTSEC4" 517 518 #define CONFIG_PIXIS_SGMII_CMD 519 #define CONFIG_FSL_SGMII_RISER 1 520 #define SGMII_RISER_PHY_OFFSET 0x1c 521 522 #ifdef CONFIG_FSL_SGMII_RISER 523 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 524 #endif 525 526 #define TSEC1_PHY_ADDR 0 527 #define TSEC2_PHY_ADDR 1 528 #define TSEC3_PHY_ADDR 2 529 #define TSEC4_PHY_ADDR 3 530 531 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 532 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 533 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 534 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 535 536 #define TSEC1_PHYIDX 0 537 #define TSEC2_PHYIDX 0 538 #define TSEC3_PHYIDX 0 539 #define TSEC4_PHYIDX 0 540 541 #define CONFIG_ETHPRIME "eTSEC1" 542 543 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 544 #endif /* CONFIG_TSEC_ENET */ 545 546 /* 547 * Environment 548 */ 549 550 #if defined(CONFIG_SYS_RAMBOOT) 551 552 #else 553 #define CONFIG_ENV_IS_IN_FLASH 1 554 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 555 #define CONFIG_ENV_ADDR 0xfff80000 556 #else 557 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 558 #endif 559 #define CONFIG_ENV_SIZE 0x2000 560 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 561 #endif 562 563 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 564 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 565 566 /* 567 * Command line configuration. 568 */ 569 #define CONFIG_CMD_ERRATA 570 #define CONFIG_CMD_IRQ 571 #define CONFIG_CMD_REGINFO 572 573 #if defined(CONFIG_PCI) 574 #define CONFIG_CMD_PCI 575 #define CONFIG_SCSI 576 #endif 577 578 /* 579 * USB 580 */ 581 #define CONFIG_USB_EHCI 582 583 #ifdef CONFIG_USB_EHCI 584 #define CONFIG_USB_EHCI_PCI 585 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 586 #define CONFIG_PCI_EHCI_DEVICE 0 587 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 588 #endif 589 590 #undef CONFIG_WATCHDOG /* watchdog disabled */ 591 592 /* 593 * Miscellaneous configurable options 594 */ 595 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 596 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 597 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 598 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 599 #if defined(CONFIG_CMD_KGDB) 600 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 601 #else 602 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 603 #endif 604 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 605 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 606 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 607 608 /* 609 * For booting Linux, the board info and command line data 610 * have to be in the first 64 MB of memory, since this is 611 * the maximum mapped by the Linux kernel during initialization. 612 */ 613 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 614 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 615 616 #if defined(CONFIG_CMD_KGDB) 617 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 618 #endif 619 620 /* 621 * Environment Configuration 622 */ 623 #if defined(CONFIG_TSEC_ENET) 624 #define CONFIG_HAS_ETH0 625 #define CONFIG_HAS_ETH1 626 #define CONFIG_HAS_ETH2 627 #define CONFIG_HAS_ETH3 628 #endif 629 630 #define CONFIG_IPADDR 192.168.1.254 631 632 #define CONFIG_HOSTNAME unknown 633 #define CONFIG_ROOTPATH "/opt/nfsroot" 634 #define CONFIG_BOOTFILE "uImage" 635 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 636 637 #define CONFIG_SERVERIP 192.168.1.1 638 #define CONFIG_GATEWAYIP 192.168.1.1 639 #define CONFIG_NETMASK 255.255.255.0 640 641 /* default location for tftp and bootm */ 642 #define CONFIG_LOADADDR 1000000 643 644 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 645 646 #define CONFIG_BAUDRATE 115200 647 648 #define CONFIG_EXTRA_ENV_SETTINGS \ 649 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 650 "netdev=eth0\0" \ 651 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 652 "tftpflash=tftpboot $loadaddr $uboot; " \ 653 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 654 " +$filesize; " \ 655 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 656 " +$filesize; " \ 657 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 658 " $filesize; " \ 659 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 660 " +$filesize; " \ 661 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 662 " $filesize\0" \ 663 "consoledev=ttyS0\0" \ 664 "ramdiskaddr=2000000\0" \ 665 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 666 "fdtaddr=1e00000\0" \ 667 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 668 "bdev=sda3\0" 669 670 #define CONFIG_HDBOOT \ 671 "setenv bootargs root=/dev/$bdev rw " \ 672 "console=$consoledev,$baudrate $othbootargs;" \ 673 "tftp $loadaddr $bootfile;" \ 674 "tftp $fdtaddr $fdtfile;" \ 675 "bootm $loadaddr - $fdtaddr" 676 677 #define CONFIG_NFSBOOTCOMMAND \ 678 "setenv bootargs root=/dev/nfs rw " \ 679 "nfsroot=$serverip:$rootpath " \ 680 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 681 "console=$consoledev,$baudrate $othbootargs;" \ 682 "tftp $loadaddr $bootfile;" \ 683 "tftp $fdtaddr $fdtfile;" \ 684 "bootm $loadaddr - $fdtaddr" 685 686 #define CONFIG_RAMBOOTCOMMAND \ 687 "setenv bootargs root=/dev/ram rw " \ 688 "console=$consoledev,$baudrate $othbootargs;" \ 689 "tftp $ramdiskaddr $ramdiskfile;" \ 690 "tftp $loadaddr $bootfile;" \ 691 "tftp $fdtaddr $fdtfile;" \ 692 "bootm $loadaddr $ramdiskaddr $fdtaddr" 693 694 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 695 696 #endif /* __CONFIG_H */ 697