xref: /openbmc/u-boot/include/configs/MPC8572DS.h (revision 284170309cab2006e7730c65454458680921b16a)
1 /*
2  * Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 /*
24  * mpc8572ds board configuration file
25  *
26  */
27 #ifndef __CONFIG_H
28 #define __CONFIG_H
29 
30 #include "../board/freescale/common/ics307_clk.h"
31 
32 #ifdef CONFIG_36BIT
33 #define CONFIG_PHYS_64BIT
34 #endif
35 
36 /* High Level Configuration Options */
37 #define CONFIG_BOOKE		1	/* BOOKE */
38 #define CONFIG_E500		1	/* BOOKE e500 family */
39 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
40 #define CONFIG_MPC8572		1
41 #define CONFIG_MPC8572DS	1
42 #define CONFIG_MP		1	/* support multiple processors */
43 
44 #ifndef CONFIG_SYS_TEXT_BASE
45 #define CONFIG_SYS_TEXT_BASE	0xeff80000
46 #endif
47 
48 #define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
49 #define CONFIG_PCI		1	/* Enable PCI/PCIE */
50 #define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
51 #define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
52 #define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
53 #define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
54 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
55 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
56 
57 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
58 
59 #define CONFIG_TSEC_ENET		/* tsec ethernet support */
60 #define CONFIG_ENV_OVERWRITE
61 
62 #define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
63 #define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk() /* ddrclk for MPC85xx */
64 #define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
65 
66 /*
67  * These can be toggled for performance analysis, otherwise use default.
68  */
69 #define CONFIG_L2_CACHE			/* toggle L2 cache */
70 #define CONFIG_BTB			/* toggle branch predition */
71 
72 #define CONFIG_ENABLE_36BIT_PHYS	1
73 
74 #ifdef CONFIG_PHYS_64BIT
75 #define CONFIG_ADDR_MAP			1
76 #define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
77 #endif
78 
79 #define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
80 #define CONFIG_SYS_MEMTEST_END		0x7fffffff
81 #define CONFIG_PANIC_HANG	/* do not reset board on panic */
82 
83 /*
84  * Base addresses -- Note these are effective addresses where the
85  * actual resources get mapped (not physical addresses)
86  */
87 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
88 #define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
89 #ifdef CONFIG_PHYS_64BIT
90 #define CONFIG_SYS_CCSRBAR_PHYS		0xfffe00000ull	/* physical addr of CCSRBAR */
91 #else
92 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
93 #endif
94 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
95 
96 /* DDR Setup */
97 #define CONFIG_VERY_BIG_RAM
98 #define CONFIG_FSL_DDR2
99 #undef CONFIG_FSL_DDR_INTERACTIVE
100 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
101 #define CONFIG_DDR_SPD
102 #undef CONFIG_DDR_DLL
103 
104 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
105 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
106 
107 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
108 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
109 
110 #define CONFIG_NUM_DDR_CONTROLLERS	2
111 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
112 #define CONFIG_CHIP_SELECTS_PER_CTRL	2
113 
114 /* I2C addresses of SPD EEPROMs */
115 #define CONFIG_SYS_SPD_BUS_NUM		1	/* SPD EEPROMS locate on I2C bus 1 */
116 #define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
117 #define SPD_EEPROM_ADDRESS2	0x52	/* CTLR 1 DIMM 0 */
118 
119 /* These are used when DDR doesn't use SPD.  */
120 #define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
121 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000001F
122 #define CONFIG_SYS_DDR_CS0_CONFIG	0x80010202	/* Enable, no interleaving */
123 #define CONFIG_SYS_DDR_TIMING_3		0x00020000
124 #define CONFIG_SYS_DDR_TIMING_0		0x00260802
125 #define CONFIG_SYS_DDR_TIMING_1		0x626b2634
126 #define CONFIG_SYS_DDR_TIMING_2		0x062874cf
127 #define CONFIG_SYS_DDR_MODE_1		0x00440462
128 #define CONFIG_SYS_DDR_MODE_2		0x00000000
129 #define CONFIG_SYS_DDR_INTERVAL		0x0c300100
130 #define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
131 #define CONFIG_SYS_DDR_CLK_CTRL		0x00800000
132 #define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
133 #define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
134 #define CONFIG_SYS_DDR_CONTROL		0xc3000008	/* Type = DDR2 */
135 #define CONFIG_SYS_DDR_CONTROL2		0x24400000
136 
137 #define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
138 #define CONFIG_SYS_DDR_ERR_DIS		0x00000000
139 #define CONFIG_SYS_DDR_SBE		0x00010000
140 
141 /*
142  * Make sure required options are set
143  */
144 #ifndef CONFIG_SPD_EEPROM
145 #error ("CONFIG_SPD_EEPROM is required")
146 #endif
147 
148 #undef CONFIG_CLOCKS_IN_MHZ
149 
150 /*
151  * Memory map
152  *
153  * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
154  * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
155  * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
156  * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
157  *
158  * Localbus cacheable (TBD)
159  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
160  *
161  * Localbus non-cacheable
162  * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
163  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
164  * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
165  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
166  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
167  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
168  */
169 
170 /*
171  * Local Bus Definitions
172  */
173 #define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
174 #ifdef CONFIG_PHYS_64BIT
175 #define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
176 #else
177 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
178 #endif
179 
180 #define CONFIG_SYS_BR0_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
181 #define CONFIG_SYS_OR0_PRELIM	0xf8000ff7
182 
183 #define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
184 #define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
185 
186 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
187 #define CONFIG_SYS_FLASH_QUIET_TEST
188 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
189 
190 #define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
191 #define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
192 #undef	CONFIG_SYS_FLASH_CHECKSUM
193 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
194 #define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
195 
196 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
197 
198 #define CONFIG_FLASH_CFI_DRIVER
199 #define CONFIG_SYS_FLASH_CFI
200 #define CONFIG_SYS_FLASH_EMPTY_INFO
201 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
202 
203 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
204 
205 #define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
206 #define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
207 #ifdef CONFIG_PHYS_64BIT
208 #define PIXIS_BASE_PHYS	0xfffdf0000ull
209 #else
210 #define PIXIS_BASE_PHYS	PIXIS_BASE
211 #endif
212 
213 #define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
214 #define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
215 
216 #define PIXIS_ID		0x0	/* Board ID at offset 0 */
217 #define PIXIS_VER		0x1	/* Board version at offset 1 */
218 #define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
219 #define PIXIS_CSR   		0x3	/* PIXIS General control/status register */
220 #define PIXIS_RST		0x4	/* PIXIS Reset Control register */
221 #define PIXIS_PWR		0x5	/* PIXIS Power status register */
222 #define PIXIS_AUX		0x6	/* Auxiliary 1 register */
223 #define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
224 #define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
225 #define PIXIS_VCTL		0x10	/* VELA Control Register */
226 #define PIXIS_VSTAT		0x11	/* VELA Status Register */
227 #define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
228 #define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
229 #define PIXIS_VCORE0	 	0x14	/* VELA VCORE0 Register */
230 #define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
231 #define PIXIS_VBOOT_LBMAP	0xc0	/* VBOOT - CFG_LBMAP */
232 #define PIXIS_VBOOT_LBMAP_NOR0	0x00	/* cfg_lbmap - boot from NOR 0 */
233 #define PIXIS_VBOOT_LBMAP_PJET	0x01	/* cfg_lbmap - boot from projet */
234 #define PIXIS_VBOOT_LBMAP_NAND	0x02	/* cfg_lbmap - boot from NAND */
235 #define PIXIS_VBOOT_LBMAP_NOR1	0x03	/* cfg_lbmap - boot from NOR 1 */
236 #define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
237 #define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
238 #define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
239 #define PIXIS_VSYSCLK0		0x1C	/* VELA SYSCLK0 Register */
240 #define PIXIS_VSYSCLK1		0x1D	/* VELA SYSCLK1 Register */
241 #define PIXIS_VSYSCLK2		0x1E	/* VELA SYSCLK2 Register */
242 #define PIXIS_VDDRCLK0		0x1F	/* VELA DDRCLK0 Register */
243 #define PIXIS_VDDRCLK1		0x20	/* VELA DDRCLK1 Register */
244 #define PIXIS_VDDRCLK2		0x21	/* VELA DDRCLK2 Register */
245 #define PIXIS_VWATCH		0x24    /* Watchdog Register */
246 #define PIXIS_LED		0x25    /* LED Register */
247 
248 /* old pixis referenced names */
249 #define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
250 #define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
251 #define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
252 #define PIXIS_VSPEED2_TSEC1SER	0x8
253 #define PIXIS_VSPEED2_TSEC2SER	0x4
254 #define PIXIS_VSPEED2_TSEC3SER	0x2
255 #define PIXIS_VSPEED2_TSEC4SER	0x1
256 #define PIXIS_VCFGEN1_TSEC1SER	0x20
257 #define PIXIS_VCFGEN1_TSEC2SER	0x20
258 #define PIXIS_VCFGEN1_TSEC3SER	0x20
259 #define PIXIS_VCFGEN1_TSEC4SER	0x20
260 #define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER \
261 					| PIXIS_VSPEED2_TSEC2SER \
262 					| PIXIS_VSPEED2_TSEC3SER \
263 					| PIXIS_VSPEED2_TSEC4SER)
264 #define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER \
265 					| PIXIS_VCFGEN1_TSEC2SER \
266 					| PIXIS_VCFGEN1_TSEC3SER \
267 					| PIXIS_VCFGEN1_TSEC4SER)
268 
269 #define CONFIG_SYS_INIT_RAM_LOCK	1
270 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
271 #define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
272 
273 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
274 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
275 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
276 
277 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
278 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
279 
280 #define CONFIG_SYS_NAND_BASE		0xffa00000
281 #ifdef CONFIG_PHYS_64BIT
282 #define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
283 #else
284 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
285 #endif
286 #define CONFIG_SYS_NAND_BASE_LIST     { CONFIG_SYS_NAND_BASE,\
287 				CONFIG_SYS_NAND_BASE + 0x40000, \
288 				CONFIG_SYS_NAND_BASE + 0x80000,\
289 				CONFIG_SYS_NAND_BASE + 0xC0000}
290 #define CONFIG_SYS_MAX_NAND_DEVICE    4
291 #define CONFIG_MTD_NAND_VERIFY_WRITE
292 #define CONFIG_CMD_NAND		1
293 #define CONFIG_NAND_FSL_ELBC	1
294 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
295 
296 /* NAND flash config */
297 #define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
298 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
299 			       | BR_PS_8	       /* Port Size = 8 bit */ \
300 			       | BR_MS_FCM	       /* MSEL = FCM */ \
301 			       | BR_V)		       /* valid */
302 #define CONFIG_NAND_OR_PRELIM  (0xFFFC0000	      /* length 256K */ \
303 			       | OR_FCM_PGS	       /* Large Page*/ \
304 			       | OR_FCM_CSCT \
305 			       | OR_FCM_CST \
306 			       | OR_FCM_CHT \
307 			       | OR_FCM_SCY_1 \
308 			       | OR_FCM_TRLX \
309 			       | OR_FCM_EHTR)
310 
311 #define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
312 #define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
313 
314 #define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
315 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
316 			       | BR_PS_8	       /* Port Size = 8 bit */ \
317 			       | BR_MS_FCM	       /* MSEL = FCM */ \
318 			       | BR_V)		       /* valid */
319 #define CONFIG_SYS_OR4_PRELIM  CONFIG_NAND_OR_PRELIM	 /* NAND Options */
320 #define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
321 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
322 			       | BR_PS_8	       /* Port Size = 8 bit */ \
323 			       | BR_MS_FCM	       /* MSEL = FCM */ \
324 			       | BR_V)		       /* valid */
325 #define CONFIG_SYS_OR5_PRELIM  CONFIG_NAND_OR_PRELIM	 /* NAND Options */
326 
327 #define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
328 			       | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
329 			       | BR_PS_8	       /* Port Size = 8 bit */ \
330 			       | BR_MS_FCM	       /* MSEL = FCM */ \
331 			       | BR_V)		       /* valid */
332 #define CONFIG_SYS_OR6_PRELIM  CONFIG_NAND_OR_PRELIM	 /* NAND Options */
333 
334 
335 /* Serial Port - controlled on board with jumper J8
336  * open - index 2
337  * shorted - index 1
338  */
339 #define CONFIG_CONS_INDEX	1
340 #define CONFIG_SYS_NS16550
341 #define CONFIG_SYS_NS16550_SERIAL
342 #define CONFIG_SYS_NS16550_REG_SIZE	1
343 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
344 
345 #define CONFIG_SYS_BAUDRATE_TABLE	\
346 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
347 
348 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
349 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
350 
351 /* Use the HUSH parser */
352 #define CONFIG_SYS_HUSH_PARSER
353 #ifdef	CONFIG_SYS_HUSH_PARSER
354 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
355 #endif
356 
357 /*
358  * Pass open firmware flat tree
359  */
360 #define CONFIG_OF_LIBFDT		1
361 #define CONFIG_OF_BOARD_SETUP		1
362 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
363 
364 /* new uImage format support */
365 #define CONFIG_FIT		1
366 #define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
367 
368 /* I2C */
369 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
370 #define CONFIG_HARD_I2C		/* I2C with hardware support */
371 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
372 #define CONFIG_I2C_MULTI_BUS
373 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
374 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
375 #define CONFIG_SYS_I2C_SLAVE		0x7F
376 #define CONFIG_SYS_I2C_NOPROBES	{{0,0x29}}/* Don't probe these addrs */
377 #define CONFIG_SYS_I2C_OFFSET		0x3000
378 #define CONFIG_SYS_I2C2_OFFSET		0x3100
379 
380 /*
381  * I2C2 EEPROM
382  */
383 #define CONFIG_ID_EEPROM
384 #ifdef CONFIG_ID_EEPROM
385 #define CONFIG_SYS_I2C_EEPROM_NXID
386 #endif
387 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
388 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
389 #define CONFIG_SYS_EEPROM_BUS_NUM	1
390 
391 /*
392  * General PCI
393  * Memory space is mapped 1-1, but I/O space must start from 0.
394  */
395 
396 /* controller 3, direct to uli, tgtid 3, Base address 8000 */
397 #define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
398 #ifdef CONFIG_PHYS_64BIT
399 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
400 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
401 #else
402 #define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
403 #define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
404 #endif
405 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
406 #define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
407 #define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
408 #ifdef CONFIG_PHYS_64BIT
409 #define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
410 #else
411 #define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
412 #endif
413 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
414 
415 /* controller 2, Slot 2, tgtid 2, Base address 9000 */
416 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
417 #ifdef CONFIG_PHYS_64BIT
418 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
419 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
420 #else
421 #define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
422 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
423 #endif
424 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
425 #define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
426 #define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
427 #ifdef CONFIG_PHYS_64BIT
428 #define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
429 #else
430 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
431 #endif
432 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
433 
434 /* controller 1, Slot 1, tgtid 1, Base address a000 */
435 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
436 #ifdef CONFIG_PHYS_64BIT
437 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
438 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
439 #else
440 #define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
441 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
442 #endif
443 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
444 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
445 #define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
446 #ifdef CONFIG_PHYS_64BIT
447 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
448 #else
449 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
450 #endif
451 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
452 
453 #if defined(CONFIG_PCI)
454 
455 /*PCIE video card used*/
456 #define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
457 
458 /* video */
459 #define CONFIG_VIDEO
460 
461 #if defined(CONFIG_VIDEO)
462 #define CONFIG_BIOSEMU
463 #define CONFIG_CFB_CONSOLE
464 #define CONFIG_VIDEO_SW_CURSOR
465 #define CONFIG_VGA_AS_SINGLE_DEVICE
466 #define CONFIG_ATI_RADEON_FB
467 #define CONFIG_VIDEO_LOGO
468 /*#define CONFIG_CONSOLE_CURSOR*/
469 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
470 #endif
471 
472 #define CONFIG_NET_MULTI
473 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
474 
475 #undef CONFIG_EEPRO100
476 #undef CONFIG_TULIP
477 #undef CONFIG_RTL8139
478 
479 #ifndef CONFIG_PCI_PNP
480 	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCIE3_IO_BUS
481 	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCIE3_IO_BUS
482 	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
483 #endif
484 
485 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
486 #define CONFIG_DOS_PARTITION
487 #define CONFIG_SCSI_AHCI
488 
489 #ifdef CONFIG_SCSI_AHCI
490 #define CONFIG_SATA_ULI5288
491 #define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
492 #define CONFIG_SYS_SCSI_MAX_LUN	1
493 #define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
494 #define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
495 #endif /* SCSI */
496 
497 #endif	/* CONFIG_PCI */
498 
499 
500 #if defined(CONFIG_TSEC_ENET)
501 
502 #ifndef CONFIG_NET_MULTI
503 #define CONFIG_NET_MULTI	1
504 #endif
505 
506 #define CONFIG_MII		1	/* MII PHY management */
507 #define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
508 #define CONFIG_TSEC1	1
509 #define CONFIG_TSEC1_NAME	"eTSEC1"
510 #define CONFIG_TSEC2	1
511 #define CONFIG_TSEC2_NAME	"eTSEC2"
512 #define CONFIG_TSEC3	1
513 #define CONFIG_TSEC3_NAME	"eTSEC3"
514 #define CONFIG_TSEC4	1
515 #define CONFIG_TSEC4_NAME	"eTSEC4"
516 
517 #define CONFIG_PIXIS_SGMII_CMD
518 #define CONFIG_FSL_SGMII_RISER	1
519 #define SGMII_RISER_PHY_OFFSET	0x1c
520 
521 #ifdef CONFIG_FSL_SGMII_RISER
522 #define CONFIG_SYS_TBIPA_VALUE		0x10 /* avoid conflict with eTSEC4 paddr */
523 #endif
524 
525 #define TSEC1_PHY_ADDR		0
526 #define TSEC2_PHY_ADDR		1
527 #define TSEC3_PHY_ADDR		2
528 #define TSEC4_PHY_ADDR		3
529 
530 #define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
531 #define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
532 #define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
533 #define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
534 
535 #define TSEC1_PHYIDX		0
536 #define TSEC2_PHYIDX		0
537 #define TSEC3_PHYIDX		0
538 #define TSEC4_PHYIDX		0
539 
540 #define CONFIG_ETHPRIME		"eTSEC1"
541 
542 #define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
543 #endif	/* CONFIG_TSEC_ENET */
544 
545 /*
546  * Environment
547  */
548 #define CONFIG_ENV_IS_IN_FLASH	1
549 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
550 #define CONFIG_ENV_ADDR		0xfff80000
551 #else
552 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
553 #endif
554 #define CONFIG_ENV_SIZE		0x2000
555 #define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
556 
557 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
558 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
559 
560 /*
561  * Command line configuration.
562  */
563 #include <config_cmd_default.h>
564 
565 #define CONFIG_CMD_IRQ
566 #define CONFIG_CMD_PING
567 #define CONFIG_CMD_I2C
568 #define CONFIG_CMD_MII
569 #define CONFIG_CMD_ELF
570 #define CONFIG_CMD_IRQ
571 #define CONFIG_CMD_SETEXPR
572 #define CONFIG_CMD_REGINFO
573 
574 #if defined(CONFIG_PCI)
575 #define CONFIG_CMD_PCI
576 #define CONFIG_CMD_NET
577 #define CONFIG_CMD_SCSI
578 #define CONFIG_CMD_EXT2
579 #endif
580 
581 #undef CONFIG_WATCHDOG			/* watchdog disabled */
582 
583 /*
584  * Miscellaneous configurable options
585  */
586 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
587 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
588 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
589 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
590 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
591 #if defined(CONFIG_CMD_KGDB)
592 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
593 #else
594 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
595 #endif
596 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
597 #define CONFIG_SYS_MAXARGS	16		/* max number of command args */
598 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
599 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
600 
601 /*
602  * For booting Linux, the board info and command line data
603  * have to be in the first 16 MB of memory, since this is
604  * the maximum mapped by the Linux kernel during initialization.
605  */
606 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
607 
608 #if defined(CONFIG_CMD_KGDB)
609 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
610 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
611 #endif
612 
613 /*
614  * Environment Configuration
615  */
616 
617 /* The mac addresses for all ethernet interface */
618 #if defined(CONFIG_TSEC_ENET)
619 #define CONFIG_HAS_ETH0
620 #define CONFIG_ETHADDR	00:E0:0C:02:00:FD
621 #define CONFIG_HAS_ETH1
622 #define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
623 #define CONFIG_HAS_ETH2
624 #define CONFIG_ETH2ADDR	00:E0:0C:02:02:FD
625 #define CONFIG_HAS_ETH3
626 #define CONFIG_ETH3ADDR	00:E0:0C:02:03:FD
627 #endif
628 
629 #define CONFIG_IPADDR		192.168.1.254
630 
631 #define CONFIG_HOSTNAME		unknown
632 #define CONFIG_ROOTPATH		/opt/nfsroot
633 #define CONFIG_BOOTFILE		uImage
634 #define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
635 
636 #define CONFIG_SERVERIP		192.168.1.1
637 #define CONFIG_GATEWAYIP	192.168.1.1
638 #define CONFIG_NETMASK		255.255.255.0
639 
640 /* default location for tftp and bootm */
641 #define CONFIG_LOADADDR		1000000
642 
643 #define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
644 #undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
645 
646 #define CONFIG_BAUDRATE	115200
647 
648 #define	CONFIG_EXTRA_ENV_SETTINGS				\
649  "memctl_intlv_ctl=2\0"						\
650  "netdev=eth0\0"						\
651  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
652  "tftpflash=tftpboot $loadaddr $uboot; "			\
653 	"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
654 	"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
655 	"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "	\
656 	"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
657 	"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"	\
658  "consoledev=ttyS0\0"				\
659  "ramdiskaddr=2000000\0"			\
660  "ramdiskfile=8572ds/ramdisk.uboot\0"		\
661  "fdtaddr=c00000\0"				\
662  "fdtfile=8572ds/mpc8572ds.dtb\0"		\
663  "bdev=sda3\0"
664 
665 #define CONFIG_HDBOOT				\
666  "setenv bootargs root=/dev/$bdev rw "		\
667  "console=$consoledev,$baudrate $othbootargs;"	\
668  "tftp $loadaddr $bootfile;"			\
669  "tftp $fdtaddr $fdtfile;"			\
670  "bootm $loadaddr - $fdtaddr"
671 
672 #define CONFIG_NFSBOOTCOMMAND		\
673  "setenv bootargs root=/dev/nfs rw "	\
674  "nfsroot=$serverip:$rootpath "		\
675  "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
676  "console=$consoledev,$baudrate $othbootargs;"	\
677  "tftp $loadaddr $bootfile;"		\
678  "tftp $fdtaddr $fdtfile;"		\
679  "bootm $loadaddr - $fdtaddr"
680 
681 #define CONFIG_RAMBOOTCOMMAND		\
682  "setenv bootargs root=/dev/ram rw "	\
683  "console=$consoledev,$baudrate $othbootargs;"	\
684  "tftp $ramdiskaddr $ramdiskfile;"	\
685  "tftp $loadaddr $bootfile;"		\
686  "tftp $fdtaddr $fdtfile;"		\
687  "bootm $loadaddr $ramdiskaddr $fdtaddr"
688 
689 #define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
690 
691 #endif	/* __CONFIG_H */
692