1 /* 2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8572ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifndef CONFIG_SYS_TEXT_BASE 17 #define CONFIG_SYS_TEXT_BASE 0xeff40000 18 #endif 19 20 #ifndef CONFIG_RESET_VECTOR_ADDRESS 21 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 22 #endif 23 24 #ifndef CONFIG_SYS_MONITOR_BASE 25 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_BOOKE 1 /* BOOKE */ 30 #define CONFIG_E500 1 /* BOOKE e500 family */ 31 #define CONFIG_MPC8572 1 32 #define CONFIG_MPC8572DS 1 33 #define CONFIG_MP 1 /* support multiple processors */ 34 35 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 36 #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 37 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 38 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 39 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 40 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 41 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 42 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 43 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 44 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 48 #define CONFIG_ENV_OVERWRITE 49 50 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 51 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 52 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 53 54 /* 55 * These can be toggled for performance analysis, otherwise use default. 56 */ 57 #define CONFIG_L2_CACHE /* toggle L2 cache */ 58 #define CONFIG_BTB /* toggle branch predition */ 59 60 #define CONFIG_ENABLE_36BIT_PHYS 1 61 62 #ifdef CONFIG_PHYS_64BIT 63 #define CONFIG_ADDR_MAP 1 64 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 65 #endif 66 67 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 68 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 69 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 70 71 /* 72 * Config the L2 Cache as L2 SRAM 73 */ 74 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 75 #ifdef CONFIG_PHYS_64BIT 76 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 77 #else 78 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 79 #endif 80 #define CONFIG_SYS_L2_SIZE (512 << 10) 81 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 82 83 #define CONFIG_SYS_CCSRBAR 0xffe00000 84 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 85 86 #if defined(CONFIG_NAND_SPL) 87 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 88 #endif 89 90 /* DDR Setup */ 91 #define CONFIG_VERY_BIG_RAM 92 #define CONFIG_SYS_FSL_DDR2 93 #undef CONFIG_FSL_DDR_INTERACTIVE 94 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 95 #define CONFIG_DDR_SPD 96 97 #define CONFIG_DDR_ECC 98 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 99 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 100 101 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 102 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 103 104 #define CONFIG_NUM_DDR_CONTROLLERS 2 105 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 106 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 107 108 /* I2C addresses of SPD EEPROMs */ 109 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 110 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 111 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 112 113 /* These are used when DDR doesn't use SPD. */ 114 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 115 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 116 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 117 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 118 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 119 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 120 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 121 #define CONFIG_SYS_DDR_MODE_1 0x00440462 122 #define CONFIG_SYS_DDR_MODE_2 0x00000000 123 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 124 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 125 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 126 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 127 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 128 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 129 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 130 131 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 132 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 133 #define CONFIG_SYS_DDR_SBE 0x00010000 134 135 /* 136 * Make sure required options are set 137 */ 138 #ifndef CONFIG_SPD_EEPROM 139 #error ("CONFIG_SPD_EEPROM is required") 140 #endif 141 142 #undef CONFIG_CLOCKS_IN_MHZ 143 144 /* 145 * Memory map 146 * 147 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 148 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 149 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 150 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 151 * 152 * Localbus cacheable (TBD) 153 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 154 * 155 * Localbus non-cacheable 156 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 157 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 158 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 159 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 160 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 161 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 162 */ 163 164 /* 165 * Local Bus Definitions 166 */ 167 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 168 #ifdef CONFIG_PHYS_64BIT 169 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 170 #else 171 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 172 #endif 173 174 #define CONFIG_FLASH_BR_PRELIM \ 175 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 176 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 177 178 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 179 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 180 181 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 182 #define CONFIG_SYS_FLASH_QUIET_TEST 183 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 184 185 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 186 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 187 #undef CONFIG_SYS_FLASH_CHECKSUM 188 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 189 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 190 191 #undef CONFIG_SYS_RAMBOOT 192 193 #define CONFIG_FLASH_CFI_DRIVER 194 #define CONFIG_SYS_FLASH_CFI 195 #define CONFIG_SYS_FLASH_EMPTY_INFO 196 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 197 198 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 199 200 #define CONFIG_HWCONFIG /* enable hwconfig */ 201 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 202 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 203 #ifdef CONFIG_PHYS_64BIT 204 #define PIXIS_BASE_PHYS 0xfffdf0000ull 205 #else 206 #define PIXIS_BASE_PHYS PIXIS_BASE 207 #endif 208 209 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 210 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 211 212 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 213 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 214 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 215 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 216 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 217 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 218 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 219 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 220 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 221 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 222 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 223 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 224 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 225 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 226 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 227 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 228 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 229 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 230 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 231 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 232 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 233 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 234 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 235 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 236 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 237 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 238 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 239 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 240 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 241 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 242 #define PIXIS_LED 0x25 /* LED Register */ 243 244 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 245 246 /* old pixis referenced names */ 247 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 248 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 249 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 250 #define PIXIS_VSPEED2_TSEC1SER 0x8 251 #define PIXIS_VSPEED2_TSEC2SER 0x4 252 #define PIXIS_VSPEED2_TSEC3SER 0x2 253 #define PIXIS_VSPEED2_TSEC4SER 0x1 254 #define PIXIS_VCFGEN1_TSEC1SER 0x20 255 #define PIXIS_VCFGEN1_TSEC2SER 0x20 256 #define PIXIS_VCFGEN1_TSEC3SER 0x20 257 #define PIXIS_VCFGEN1_TSEC4SER 0x20 258 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 259 | PIXIS_VSPEED2_TSEC2SER \ 260 | PIXIS_VSPEED2_TSEC3SER \ 261 | PIXIS_VSPEED2_TSEC4SER) 262 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 263 | PIXIS_VCFGEN1_TSEC2SER \ 264 | PIXIS_VCFGEN1_TSEC3SER \ 265 | PIXIS_VCFGEN1_TSEC4SER) 266 267 #define CONFIG_SYS_INIT_RAM_LOCK 1 268 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 269 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 270 271 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 272 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 273 274 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 275 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 276 277 #ifndef CONFIG_NAND_SPL 278 #define CONFIG_SYS_NAND_BASE 0xffa00000 279 #ifdef CONFIG_PHYS_64BIT 280 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 281 #else 282 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 283 #endif 284 #else 285 #define CONFIG_SYS_NAND_BASE 0xfff00000 286 #ifdef CONFIG_PHYS_64BIT 287 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 288 #else 289 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 290 #endif 291 #endif 292 293 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 294 CONFIG_SYS_NAND_BASE + 0x40000, \ 295 CONFIG_SYS_NAND_BASE + 0x80000,\ 296 CONFIG_SYS_NAND_BASE + 0xC0000} 297 #define CONFIG_SYS_MAX_NAND_DEVICE 4 298 #define CONFIG_CMD_NAND 1 299 #define CONFIG_NAND_FSL_ELBC 1 300 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 301 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 302 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 303 304 /* NAND boot: 4K NAND loader config */ 305 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 306 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 307 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 308 #define CONFIG_SYS_NAND_U_BOOT_START \ 309 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 310 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 311 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 312 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 313 314 /* NAND flash config */ 315 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 316 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 317 | BR_PS_8 /* Port Size = 8 bit */ \ 318 | BR_MS_FCM /* MSEL = FCM */ \ 319 | BR_V) /* valid */ 320 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 321 | OR_FCM_PGS /* Large Page*/ \ 322 | OR_FCM_CSCT \ 323 | OR_FCM_CST \ 324 | OR_FCM_CHT \ 325 | OR_FCM_SCY_1 \ 326 | OR_FCM_TRLX \ 327 | OR_FCM_EHTR) 328 329 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 330 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 331 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 332 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 333 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 334 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 335 | BR_PS_8 /* Port Size = 8 bit */ \ 336 | BR_MS_FCM /* MSEL = FCM */ \ 337 | BR_V) /* valid */ 338 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 339 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 340 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 341 | BR_PS_8 /* Port Size = 8 bit */ \ 342 | BR_MS_FCM /* MSEL = FCM */ \ 343 | BR_V) /* valid */ 344 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 345 346 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 347 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 348 | BR_PS_8 /* Port Size = 8 bit */ \ 349 | BR_MS_FCM /* MSEL = FCM */ \ 350 | BR_V) /* valid */ 351 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 352 353 /* Serial Port - controlled on board with jumper J8 354 * open - index 2 355 * shorted - index 1 356 */ 357 #define CONFIG_CONS_INDEX 1 358 #define CONFIG_SYS_NS16550_SERIAL 359 #define CONFIG_SYS_NS16550_REG_SIZE 1 360 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 361 #ifdef CONFIG_NAND_SPL 362 #define CONFIG_NS16550_MIN_FUNCTIONS 363 #endif 364 365 #define CONFIG_SYS_BAUDRATE_TABLE \ 366 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 367 368 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 369 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 370 371 /* I2C */ 372 #define CONFIG_SYS_I2C 373 #define CONFIG_SYS_I2C_FSL 374 #define CONFIG_SYS_FSL_I2C_SPEED 400000 375 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 376 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 377 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 378 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 379 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 380 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 381 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 382 383 /* 384 * I2C2 EEPROM 385 */ 386 #define CONFIG_ID_EEPROM 387 #ifdef CONFIG_ID_EEPROM 388 #define CONFIG_SYS_I2C_EEPROM_NXID 389 #endif 390 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 391 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 392 #define CONFIG_SYS_EEPROM_BUS_NUM 1 393 394 /* 395 * General PCI 396 * Memory space is mapped 1-1, but I/O space must start from 0. 397 */ 398 399 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 400 #define CONFIG_SYS_PCIE3_NAME "ULI" 401 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 402 #ifdef CONFIG_PHYS_64BIT 403 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 404 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 405 #else 406 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 407 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 408 #endif 409 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 410 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 411 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 412 #ifdef CONFIG_PHYS_64BIT 413 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 414 #else 415 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 416 #endif 417 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 418 419 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 420 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 421 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 422 #ifdef CONFIG_PHYS_64BIT 423 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 424 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 425 #else 426 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 427 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 428 #endif 429 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 430 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 431 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 432 #ifdef CONFIG_PHYS_64BIT 433 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 434 #else 435 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 436 #endif 437 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 438 439 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 440 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 441 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 442 #ifdef CONFIG_PHYS_64BIT 443 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 444 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 445 #else 446 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 447 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 448 #endif 449 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 450 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 451 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 452 #ifdef CONFIG_PHYS_64BIT 453 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 454 #else 455 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 456 #endif 457 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 458 459 #if defined(CONFIG_PCI) 460 461 /*PCIE video card used*/ 462 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 463 464 /* video */ 465 466 #if defined(CONFIG_VIDEO) 467 #define CONFIG_BIOSEMU 468 #define CONFIG_ATI_RADEON_FB 469 #define CONFIG_VIDEO_LOGO 470 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 471 #endif 472 473 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 474 475 #undef CONFIG_EEPRO100 476 #undef CONFIG_TULIP 477 478 #ifndef CONFIG_PCI_PNP 479 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 480 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 481 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 482 #endif 483 484 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 485 #define CONFIG_DOS_PARTITION 486 #define CONFIG_SCSI_AHCI 487 488 #ifdef CONFIG_SCSI_AHCI 489 #define CONFIG_LIBATA 490 #define CONFIG_SATA_ULI5288 491 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 492 #define CONFIG_SYS_SCSI_MAX_LUN 1 493 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 494 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 495 #endif /* SCSI */ 496 497 #endif /* CONFIG_PCI */ 498 499 #if defined(CONFIG_TSEC_ENET) 500 501 #define CONFIG_MII 1 /* MII PHY management */ 502 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 503 #define CONFIG_TSEC1 1 504 #define CONFIG_TSEC1_NAME "eTSEC1" 505 #define CONFIG_TSEC2 1 506 #define CONFIG_TSEC2_NAME "eTSEC2" 507 #define CONFIG_TSEC3 1 508 #define CONFIG_TSEC3_NAME "eTSEC3" 509 #define CONFIG_TSEC4 1 510 #define CONFIG_TSEC4_NAME "eTSEC4" 511 512 #define CONFIG_PIXIS_SGMII_CMD 513 #define CONFIG_FSL_SGMII_RISER 1 514 #define SGMII_RISER_PHY_OFFSET 0x1c 515 516 #ifdef CONFIG_FSL_SGMII_RISER 517 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 518 #endif 519 520 #define TSEC1_PHY_ADDR 0 521 #define TSEC2_PHY_ADDR 1 522 #define TSEC3_PHY_ADDR 2 523 #define TSEC4_PHY_ADDR 3 524 525 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 526 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 527 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 528 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 529 530 #define TSEC1_PHYIDX 0 531 #define TSEC2_PHYIDX 0 532 #define TSEC3_PHYIDX 0 533 #define TSEC4_PHYIDX 0 534 535 #define CONFIG_ETHPRIME "eTSEC1" 536 537 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 538 #endif /* CONFIG_TSEC_ENET */ 539 540 /* 541 * Environment 542 */ 543 544 #if defined(CONFIG_SYS_RAMBOOT) 545 546 #else 547 #define CONFIG_ENV_IS_IN_FLASH 1 548 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 549 #define CONFIG_ENV_ADDR 0xfff80000 550 #else 551 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 552 #endif 553 #define CONFIG_ENV_SIZE 0x2000 554 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 555 #endif 556 557 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 558 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 559 560 /* 561 * Command line configuration. 562 */ 563 #define CONFIG_CMD_ERRATA 564 #define CONFIG_CMD_IRQ 565 #define CONFIG_CMD_REGINFO 566 567 #if defined(CONFIG_PCI) 568 #define CONFIG_CMD_PCI 569 #define CONFIG_SCSI 570 #endif 571 572 /* 573 * USB 574 */ 575 #define CONFIG_USB_EHCI 576 577 #ifdef CONFIG_USB_EHCI 578 #define CONFIG_USB_EHCI_PCI 579 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 580 #define CONFIG_PCI_EHCI_DEVICE 0 581 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 582 #endif 583 584 #undef CONFIG_WATCHDOG /* watchdog disabled */ 585 586 /* 587 * Miscellaneous configurable options 588 */ 589 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 590 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 591 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 592 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 593 #if defined(CONFIG_CMD_KGDB) 594 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 595 #else 596 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 597 #endif 598 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 599 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 600 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 601 602 /* 603 * For booting Linux, the board info and command line data 604 * have to be in the first 64 MB of memory, since this is 605 * the maximum mapped by the Linux kernel during initialization. 606 */ 607 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 608 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 609 610 #if defined(CONFIG_CMD_KGDB) 611 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 612 #endif 613 614 /* 615 * Environment Configuration 616 */ 617 #if defined(CONFIG_TSEC_ENET) 618 #define CONFIG_HAS_ETH0 619 #define CONFIG_HAS_ETH1 620 #define CONFIG_HAS_ETH2 621 #define CONFIG_HAS_ETH3 622 #endif 623 624 #define CONFIG_IPADDR 192.168.1.254 625 626 #define CONFIG_HOSTNAME unknown 627 #define CONFIG_ROOTPATH "/opt/nfsroot" 628 #define CONFIG_BOOTFILE "uImage" 629 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 630 631 #define CONFIG_SERVERIP 192.168.1.1 632 #define CONFIG_GATEWAYIP 192.168.1.1 633 #define CONFIG_NETMASK 255.255.255.0 634 635 /* default location for tftp and bootm */ 636 #define CONFIG_LOADADDR 1000000 637 638 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 639 640 #define CONFIG_BAUDRATE 115200 641 642 #define CONFIG_EXTRA_ENV_SETTINGS \ 643 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 644 "netdev=eth0\0" \ 645 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 646 "tftpflash=tftpboot $loadaddr $uboot; " \ 647 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 648 " +$filesize; " \ 649 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 650 " +$filesize; " \ 651 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 652 " $filesize; " \ 653 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 654 " +$filesize; " \ 655 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 656 " $filesize\0" \ 657 "consoledev=ttyS0\0" \ 658 "ramdiskaddr=2000000\0" \ 659 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 660 "fdtaddr=1e00000\0" \ 661 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 662 "bdev=sda3\0" 663 664 #define CONFIG_HDBOOT \ 665 "setenv bootargs root=/dev/$bdev rw " \ 666 "console=$consoledev,$baudrate $othbootargs;" \ 667 "tftp $loadaddr $bootfile;" \ 668 "tftp $fdtaddr $fdtfile;" \ 669 "bootm $loadaddr - $fdtaddr" 670 671 #define CONFIG_NFSBOOTCOMMAND \ 672 "setenv bootargs root=/dev/nfs rw " \ 673 "nfsroot=$serverip:$rootpath " \ 674 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 675 "console=$consoledev,$baudrate $othbootargs;" \ 676 "tftp $loadaddr $bootfile;" \ 677 "tftp $fdtaddr $fdtfile;" \ 678 "bootm $loadaddr - $fdtaddr" 679 680 #define CONFIG_RAMBOOTCOMMAND \ 681 "setenv bootargs root=/dev/ram rw " \ 682 "console=$consoledev,$baudrate $othbootargs;" \ 683 "tftp $ramdiskaddr $ramdiskfile;" \ 684 "tftp $loadaddr $bootfile;" \ 685 "tftp $fdtaddr $fdtfile;" \ 686 "bootm $loadaddr $ramdiskaddr $fdtaddr" 687 688 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 689 690 #endif /* __CONFIG_H */ 691