1 /* 2 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8572ds board configuration file 9 * 10 */ 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include "../board/freescale/common/ics307_clk.h" 15 16 #ifndef CONFIG_SYS_TEXT_BASE 17 #define CONFIG_SYS_TEXT_BASE 0xeff40000 18 #endif 19 20 #ifndef CONFIG_RESET_VECTOR_ADDRESS 21 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 22 #endif 23 24 #ifndef CONFIG_SYS_MONITOR_BASE 25 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 26 #endif 27 28 /* High Level Configuration Options */ 29 #define CONFIG_BOOKE 1 /* BOOKE */ 30 #define CONFIG_E500 1 /* BOOKE e500 family */ 31 #define CONFIG_MP 1 /* support multiple processors */ 32 33 #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 34 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 35 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 36 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 37 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 38 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 39 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 40 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 41 42 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 43 44 #define CONFIG_TSEC_ENET /* tsec ethernet support */ 45 #define CONFIG_ENV_OVERWRITE 46 47 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 48 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 49 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 50 51 /* 52 * These can be toggled for performance analysis, otherwise use default. 53 */ 54 #define CONFIG_L2_CACHE /* toggle L2 cache */ 55 #define CONFIG_BTB /* toggle branch predition */ 56 57 #define CONFIG_ENABLE_36BIT_PHYS 1 58 59 #ifdef CONFIG_PHYS_64BIT 60 #define CONFIG_ADDR_MAP 1 61 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 62 #endif 63 64 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 65 #define CONFIG_SYS_MEMTEST_END 0x7fffffff 66 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 67 68 /* 69 * Config the L2 Cache as L2 SRAM 70 */ 71 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 72 #ifdef CONFIG_PHYS_64BIT 73 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 74 #else 75 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 76 #endif 77 #define CONFIG_SYS_L2_SIZE (512 << 10) 78 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 79 80 #define CONFIG_SYS_CCSRBAR 0xffe00000 81 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 82 83 #if defined(CONFIG_NAND_SPL) 84 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 85 #endif 86 87 /* DDR Setup */ 88 #define CONFIG_VERY_BIG_RAM 89 #define CONFIG_SYS_FSL_DDR2 90 #undef CONFIG_FSL_DDR_INTERACTIVE 91 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 92 #define CONFIG_DDR_SPD 93 94 #define CONFIG_DDR_ECC 95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 96 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 97 98 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 99 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 100 101 #define CONFIG_NUM_DDR_CONTROLLERS 2 102 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 103 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 104 105 /* I2C addresses of SPD EEPROMs */ 106 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 107 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 108 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 109 110 /* These are used when DDR doesn't use SPD. */ 111 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 112 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 113 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 114 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 115 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 116 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 117 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 118 #define CONFIG_SYS_DDR_MODE_1 0x00440462 119 #define CONFIG_SYS_DDR_MODE_2 0x00000000 120 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 121 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 122 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 123 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 124 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 125 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 126 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 127 128 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 129 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 130 #define CONFIG_SYS_DDR_SBE 0x00010000 131 132 /* 133 * Make sure required options are set 134 */ 135 #ifndef CONFIG_SPD_EEPROM 136 #error ("CONFIG_SPD_EEPROM is required") 137 #endif 138 139 #undef CONFIG_CLOCKS_IN_MHZ 140 141 /* 142 * Memory map 143 * 144 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 145 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 146 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 147 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 148 * 149 * Localbus cacheable (TBD) 150 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 151 * 152 * Localbus non-cacheable 153 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 154 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 155 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 156 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 157 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 158 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 159 */ 160 161 /* 162 * Local Bus Definitions 163 */ 164 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 165 #ifdef CONFIG_PHYS_64BIT 166 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 167 #else 168 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 169 #endif 170 171 #define CONFIG_FLASH_BR_PRELIM \ 172 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 173 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 174 175 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 176 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 177 178 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 179 #define CONFIG_SYS_FLASH_QUIET_TEST 180 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 181 182 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 183 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 184 #undef CONFIG_SYS_FLASH_CHECKSUM 185 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 186 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 187 188 #undef CONFIG_SYS_RAMBOOT 189 190 #define CONFIG_FLASH_CFI_DRIVER 191 #define CONFIG_SYS_FLASH_CFI 192 #define CONFIG_SYS_FLASH_EMPTY_INFO 193 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 194 195 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 196 197 #define CONFIG_HWCONFIG /* enable hwconfig */ 198 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 199 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 200 #ifdef CONFIG_PHYS_64BIT 201 #define PIXIS_BASE_PHYS 0xfffdf0000ull 202 #else 203 #define PIXIS_BASE_PHYS PIXIS_BASE 204 #endif 205 206 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 207 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 208 209 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 210 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 211 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 212 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 213 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 214 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 215 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 216 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 217 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 218 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 219 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 220 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 221 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 222 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 223 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 224 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 225 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 226 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 227 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 228 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 229 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 230 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 231 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 232 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 233 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 234 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 235 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 236 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 237 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 238 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 239 #define PIXIS_LED 0x25 /* LED Register */ 240 241 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 242 243 /* old pixis referenced names */ 244 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 245 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 246 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 247 #define PIXIS_VSPEED2_TSEC1SER 0x8 248 #define PIXIS_VSPEED2_TSEC2SER 0x4 249 #define PIXIS_VSPEED2_TSEC3SER 0x2 250 #define PIXIS_VSPEED2_TSEC4SER 0x1 251 #define PIXIS_VCFGEN1_TSEC1SER 0x20 252 #define PIXIS_VCFGEN1_TSEC2SER 0x20 253 #define PIXIS_VCFGEN1_TSEC3SER 0x20 254 #define PIXIS_VCFGEN1_TSEC4SER 0x20 255 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 256 | PIXIS_VSPEED2_TSEC2SER \ 257 | PIXIS_VSPEED2_TSEC3SER \ 258 | PIXIS_VSPEED2_TSEC4SER) 259 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 260 | PIXIS_VCFGEN1_TSEC2SER \ 261 | PIXIS_VCFGEN1_TSEC3SER \ 262 | PIXIS_VCFGEN1_TSEC4SER) 263 264 #define CONFIG_SYS_INIT_RAM_LOCK 1 265 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 266 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 267 268 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 269 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 270 271 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 272 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 273 274 #ifndef CONFIG_NAND_SPL 275 #define CONFIG_SYS_NAND_BASE 0xffa00000 276 #ifdef CONFIG_PHYS_64BIT 277 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 278 #else 279 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 280 #endif 281 #else 282 #define CONFIG_SYS_NAND_BASE 0xfff00000 283 #ifdef CONFIG_PHYS_64BIT 284 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 285 #else 286 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 287 #endif 288 #endif 289 290 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 291 CONFIG_SYS_NAND_BASE + 0x40000, \ 292 CONFIG_SYS_NAND_BASE + 0x80000,\ 293 CONFIG_SYS_NAND_BASE + 0xC0000} 294 #define CONFIG_SYS_MAX_NAND_DEVICE 4 295 #define CONFIG_CMD_NAND 1 296 #define CONFIG_NAND_FSL_ELBC 1 297 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 298 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 299 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 300 301 /* NAND boot: 4K NAND loader config */ 302 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 303 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 304 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 305 #define CONFIG_SYS_NAND_U_BOOT_START \ 306 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 307 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 308 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 309 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 310 311 /* NAND flash config */ 312 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 313 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 314 | BR_PS_8 /* Port Size = 8 bit */ \ 315 | BR_MS_FCM /* MSEL = FCM */ \ 316 | BR_V) /* valid */ 317 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 318 | OR_FCM_PGS /* Large Page*/ \ 319 | OR_FCM_CSCT \ 320 | OR_FCM_CST \ 321 | OR_FCM_CHT \ 322 | OR_FCM_SCY_1 \ 323 | OR_FCM_TRLX \ 324 | OR_FCM_EHTR) 325 326 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 327 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 328 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 329 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 330 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 331 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 332 | BR_PS_8 /* Port Size = 8 bit */ \ 333 | BR_MS_FCM /* MSEL = FCM */ \ 334 | BR_V) /* valid */ 335 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 336 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 337 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 338 | BR_PS_8 /* Port Size = 8 bit */ \ 339 | BR_MS_FCM /* MSEL = FCM */ \ 340 | BR_V) /* valid */ 341 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 342 343 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 344 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 345 | BR_PS_8 /* Port Size = 8 bit */ \ 346 | BR_MS_FCM /* MSEL = FCM */ \ 347 | BR_V) /* valid */ 348 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 349 350 /* Serial Port - controlled on board with jumper J8 351 * open - index 2 352 * shorted - index 1 353 */ 354 #define CONFIG_CONS_INDEX 1 355 #define CONFIG_SYS_NS16550_SERIAL 356 #define CONFIG_SYS_NS16550_REG_SIZE 1 357 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 358 #ifdef CONFIG_NAND_SPL 359 #define CONFIG_NS16550_MIN_FUNCTIONS 360 #endif 361 362 #define CONFIG_SYS_BAUDRATE_TABLE \ 363 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 364 365 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 366 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 367 368 /* I2C */ 369 #define CONFIG_SYS_I2C 370 #define CONFIG_SYS_I2C_FSL 371 #define CONFIG_SYS_FSL_I2C_SPEED 400000 372 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 373 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 374 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 375 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 376 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 377 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 378 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 379 380 /* 381 * I2C2 EEPROM 382 */ 383 #define CONFIG_ID_EEPROM 384 #ifdef CONFIG_ID_EEPROM 385 #define CONFIG_SYS_I2C_EEPROM_NXID 386 #endif 387 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 388 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 389 #define CONFIG_SYS_EEPROM_BUS_NUM 1 390 391 /* 392 * General PCI 393 * Memory space is mapped 1-1, but I/O space must start from 0. 394 */ 395 396 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 397 #define CONFIG_SYS_PCIE3_NAME "ULI" 398 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 399 #ifdef CONFIG_PHYS_64BIT 400 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 401 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 402 #else 403 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 404 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 405 #endif 406 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 407 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 408 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 409 #ifdef CONFIG_PHYS_64BIT 410 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 411 #else 412 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 413 #endif 414 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 415 416 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 417 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 418 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 419 #ifdef CONFIG_PHYS_64BIT 420 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 421 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 422 #else 423 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 424 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 425 #endif 426 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 427 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 428 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 429 #ifdef CONFIG_PHYS_64BIT 430 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 431 #else 432 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 433 #endif 434 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 435 436 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 437 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 438 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 439 #ifdef CONFIG_PHYS_64BIT 440 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 441 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 442 #else 443 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 444 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 445 #endif 446 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 447 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 448 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 449 #ifdef CONFIG_PHYS_64BIT 450 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 451 #else 452 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 453 #endif 454 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 455 456 #if defined(CONFIG_PCI) 457 458 /*PCIE video card used*/ 459 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 460 461 /* video */ 462 463 #if defined(CONFIG_VIDEO) 464 #define CONFIG_BIOSEMU 465 #define CONFIG_ATI_RADEON_FB 466 #define CONFIG_VIDEO_LOGO 467 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 468 #endif 469 470 #undef CONFIG_EEPRO100 471 #undef CONFIG_TULIP 472 473 #ifndef CONFIG_PCI_PNP 474 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 475 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 476 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 477 #endif 478 479 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 480 #define CONFIG_DOS_PARTITION 481 #define CONFIG_SCSI_AHCI 482 483 #ifdef CONFIG_SCSI_AHCI 484 #define CONFIG_LIBATA 485 #define CONFIG_SATA_ULI5288 486 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 487 #define CONFIG_SYS_SCSI_MAX_LUN 1 488 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 489 #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 490 #endif /* SCSI */ 491 492 #endif /* CONFIG_PCI */ 493 494 #if defined(CONFIG_TSEC_ENET) 495 496 #define CONFIG_MII 1 /* MII PHY management */ 497 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 498 #define CONFIG_TSEC1 1 499 #define CONFIG_TSEC1_NAME "eTSEC1" 500 #define CONFIG_TSEC2 1 501 #define CONFIG_TSEC2_NAME "eTSEC2" 502 #define CONFIG_TSEC3 1 503 #define CONFIG_TSEC3_NAME "eTSEC3" 504 #define CONFIG_TSEC4 1 505 #define CONFIG_TSEC4_NAME "eTSEC4" 506 507 #define CONFIG_PIXIS_SGMII_CMD 508 #define CONFIG_FSL_SGMII_RISER 1 509 #define SGMII_RISER_PHY_OFFSET 0x1c 510 511 #ifdef CONFIG_FSL_SGMII_RISER 512 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 513 #endif 514 515 #define TSEC1_PHY_ADDR 0 516 #define TSEC2_PHY_ADDR 1 517 #define TSEC3_PHY_ADDR 2 518 #define TSEC4_PHY_ADDR 3 519 520 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 521 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 522 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 523 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 524 525 #define TSEC1_PHYIDX 0 526 #define TSEC2_PHYIDX 0 527 #define TSEC3_PHYIDX 0 528 #define TSEC4_PHYIDX 0 529 530 #define CONFIG_ETHPRIME "eTSEC1" 531 532 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 533 #endif /* CONFIG_TSEC_ENET */ 534 535 /* 536 * Environment 537 */ 538 539 #if defined(CONFIG_SYS_RAMBOOT) 540 541 #else 542 #define CONFIG_ENV_IS_IN_FLASH 1 543 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 544 #define CONFIG_ENV_ADDR 0xfff80000 545 #else 546 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 547 #endif 548 #define CONFIG_ENV_SIZE 0x2000 549 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 550 #endif 551 552 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 553 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 554 555 /* 556 * Command line configuration. 557 */ 558 #define CONFIG_CMD_ERRATA 559 #define CONFIG_CMD_IRQ 560 #define CONFIG_CMD_REGINFO 561 562 #if defined(CONFIG_PCI) 563 #define CONFIG_CMD_PCI 564 #define CONFIG_SCSI 565 #endif 566 567 /* 568 * USB 569 */ 570 #define CONFIG_USB_EHCI 571 572 #ifdef CONFIG_USB_EHCI 573 #define CONFIG_USB_EHCI_PCI 574 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 575 #define CONFIG_PCI_EHCI_DEVICE 0 576 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 577 #endif 578 579 #undef CONFIG_WATCHDOG /* watchdog disabled */ 580 581 /* 582 * Miscellaneous configurable options 583 */ 584 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 585 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 586 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 587 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 588 #if defined(CONFIG_CMD_KGDB) 589 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 590 #else 591 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 592 #endif 593 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 594 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 595 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 596 597 /* 598 * For booting Linux, the board info and command line data 599 * have to be in the first 64 MB of memory, since this is 600 * the maximum mapped by the Linux kernel during initialization. 601 */ 602 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 603 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 604 605 #if defined(CONFIG_CMD_KGDB) 606 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 607 #endif 608 609 /* 610 * Environment Configuration 611 */ 612 #if defined(CONFIG_TSEC_ENET) 613 #define CONFIG_HAS_ETH0 614 #define CONFIG_HAS_ETH1 615 #define CONFIG_HAS_ETH2 616 #define CONFIG_HAS_ETH3 617 #endif 618 619 #define CONFIG_IPADDR 192.168.1.254 620 621 #define CONFIG_HOSTNAME unknown 622 #define CONFIG_ROOTPATH "/opt/nfsroot" 623 #define CONFIG_BOOTFILE "uImage" 624 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 625 626 #define CONFIG_SERVERIP 192.168.1.1 627 #define CONFIG_GATEWAYIP 192.168.1.1 628 #define CONFIG_NETMASK 255.255.255.0 629 630 /* default location for tftp and bootm */ 631 #define CONFIG_LOADADDR 1000000 632 633 #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 634 635 #define CONFIG_BAUDRATE 115200 636 637 #define CONFIG_EXTRA_ENV_SETTINGS \ 638 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 639 "netdev=eth0\0" \ 640 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 641 "tftpflash=tftpboot $loadaddr $uboot; " \ 642 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 643 " +$filesize; " \ 644 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 645 " +$filesize; " \ 646 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 647 " $filesize; " \ 648 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 649 " +$filesize; " \ 650 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 651 " $filesize\0" \ 652 "consoledev=ttyS0\0" \ 653 "ramdiskaddr=2000000\0" \ 654 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 655 "fdtaddr=1e00000\0" \ 656 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 657 "bdev=sda3\0" 658 659 #define CONFIG_HDBOOT \ 660 "setenv bootargs root=/dev/$bdev rw " \ 661 "console=$consoledev,$baudrate $othbootargs;" \ 662 "tftp $loadaddr $bootfile;" \ 663 "tftp $fdtaddr $fdtfile;" \ 664 "bootm $loadaddr - $fdtaddr" 665 666 #define CONFIG_NFSBOOTCOMMAND \ 667 "setenv bootargs root=/dev/nfs rw " \ 668 "nfsroot=$serverip:$rootpath " \ 669 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 670 "console=$consoledev,$baudrate $othbootargs;" \ 671 "tftp $loadaddr $bootfile;" \ 672 "tftp $fdtaddr $fdtfile;" \ 673 "bootm $loadaddr - $fdtaddr" 674 675 #define CONFIG_RAMBOOTCOMMAND \ 676 "setenv bootargs root=/dev/ram rw " \ 677 "console=$consoledev,$baudrate $othbootargs;" \ 678 "tftp $ramdiskaddr $ramdiskfile;" \ 679 "tftp $loadaddr $bootfile;" \ 680 "tftp $fdtaddr $fdtfile;" \ 681 "bootm $loadaddr $ramdiskaddr $fdtaddr" 682 683 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 684 685 #endif /* __CONFIG_H */ 686