1129ba616SKumar Gala /* 2509c4c4cSKumar Gala * Copyright 2007-2008,2010 Freescale Semiconductor, Inc. 3129ba616SKumar Gala * 4129ba616SKumar Gala * See file CREDITS for list of people who contributed to this 5129ba616SKumar Gala * project. 6129ba616SKumar Gala * 7129ba616SKumar Gala * This program is free software; you can redistribute it and/or 8129ba616SKumar Gala * modify it under the terms of the GNU General Public License as 9129ba616SKumar Gala * published by the Free Software Foundation; either version 2 of 10129ba616SKumar Gala * the License, or (at your option) any later version. 11129ba616SKumar Gala * 12129ba616SKumar Gala * This program is distributed in the hope that it will be useful, 13129ba616SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 14129ba616SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15129ba616SKumar Gala * GNU General Public License for more details. 16129ba616SKumar Gala * 17129ba616SKumar Gala * You should have received a copy of the GNU General Public License 18129ba616SKumar Gala * along with this program; if not, write to the Free Software 19129ba616SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20129ba616SKumar Gala * MA 02111-1307 USA 21129ba616SKumar Gala */ 22129ba616SKumar Gala 23129ba616SKumar Gala /* 24129ba616SKumar Gala * mpc8572ds board configuration file 25129ba616SKumar Gala * 26129ba616SKumar Gala */ 27129ba616SKumar Gala #ifndef __CONFIG_H 28129ba616SKumar Gala #define __CONFIG_H 29129ba616SKumar Gala 30509c4c4cSKumar Gala #include "../board/freescale/common/ics307_clk.h" 31509c4c4cSKumar Gala 32*d24f2d32SWolfgang Denk #ifdef CONFIG_36BIT 33f9edcc10SKumar Gala #define CONFIG_PHYS_64BIT 34f9edcc10SKumar Gala #endif 35f9edcc10SKumar Gala 36129ba616SKumar Gala /* High Level Configuration Options */ 37129ba616SKumar Gala #define CONFIG_BOOKE 1 /* BOOKE */ 38129ba616SKumar Gala #define CONFIG_E500 1 /* BOOKE e500 family */ 39129ba616SKumar Gala #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 40129ba616SKumar Gala #define CONFIG_MPC8572 1 41129ba616SKumar Gala #define CONFIG_MPC8572DS 1 42129ba616SKumar Gala #define CONFIG_MP 1 /* support multiple processors */ 43129ba616SKumar Gala 44c51fc5d5SKumar Gala #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 45129ba616SKumar Gala #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 46129ba616SKumar Gala #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 47129ba616SKumar Gala #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 48129ba616SKumar Gala #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 49129ba616SKumar Gala #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 50129ba616SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 510151cbacSKumar Gala #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 52129ba616SKumar Gala 53129ba616SKumar Gala #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 54129ba616SKumar Gala 55129ba616SKumar Gala #define CONFIG_TSEC_ENET /* tsec ethernet support */ 56129ba616SKumar Gala #define CONFIG_ENV_OVERWRITE 57129ba616SKumar Gala 58509c4c4cSKumar Gala #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 59509c4c4cSKumar Gala #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 604ca06607SHaiying Wang #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 61129ba616SKumar Gala 62129ba616SKumar Gala /* 63129ba616SKumar Gala * These can be toggled for performance analysis, otherwise use default. 64129ba616SKumar Gala */ 65129ba616SKumar Gala #define CONFIG_L2_CACHE /* toggle L2 cache */ 66129ba616SKumar Gala #define CONFIG_BTB /* toggle branch predition */ 67129ba616SKumar Gala 68129ba616SKumar Gala #define CONFIG_ENABLE_36BIT_PHYS 1 69129ba616SKumar Gala 7018af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 7118af1c5fSKumar Gala #define CONFIG_ADDR_MAP 1 7218af1c5fSKumar Gala #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 7318af1c5fSKumar Gala #endif 7418af1c5fSKumar Gala 756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x7fffffff 77129ba616SKumar Gala #define CONFIG_PANIC_HANG /* do not reset board on panic */ 78129ba616SKumar Gala 79129ba616SKumar Gala /* 80129ba616SKumar Gala * Base addresses -- Note these are effective addresses where the 81129ba616SKumar Gala * actual resources get mapped (not physical addresses) 82129ba616SKumar Gala */ 836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 8518af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 8618af1c5fSKumar Gala #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 8718af1c5fSKumar Gala #else 886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 8918af1c5fSKumar Gala #endif 906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 91129ba616SKumar Gala 92129ba616SKumar Gala /* DDR Setup */ 93f8523cb0SKumar Gala #define CONFIG_VERY_BIG_RAM 94129ba616SKumar Gala #define CONFIG_FSL_DDR2 95129ba616SKumar Gala #undef CONFIG_FSL_DDR_INTERACTIVE 96129ba616SKumar Gala #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 97129ba616SKumar Gala #define CONFIG_DDR_SPD 98129ba616SKumar Gala #undef CONFIG_DDR_DLL 99129ba616SKumar Gala 1009b0ad1b1SDave Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 101129ba616SKumar Gala #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 102129ba616SKumar Gala 1036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 1046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 105129ba616SKumar Gala 106129ba616SKumar Gala #define CONFIG_NUM_DDR_CONTROLLERS 2 107129ba616SKumar Gala #define CONFIG_DIMM_SLOTS_PER_CTLR 1 108129ba616SKumar Gala #define CONFIG_CHIP_SELECTS_PER_CTRL 2 109129ba616SKumar Gala 110129ba616SKumar Gala /* I2C addresses of SPD EEPROMs */ 1116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 112129ba616SKumar Gala #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 113129ba616SKumar Gala #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 114129ba616SKumar Gala 115129ba616SKumar Gala /* These are used when DDR doesn't use SPD. */ 116dc889e86SDave Liu #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 1176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 118dc889e86SDave Liu #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 119dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_3 0x00020000 1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 0x00260802 121dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 122dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 123dc889e86SDave Liu #define CONFIG_SYS_DDR_MODE_1 0x00440462 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x00000000 125dc889e86SDave Liu #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 127dc889e86SDave Liu #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 1286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 1296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 130dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 131dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL2 0x24400000 132129ba616SKumar Gala 1336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 1346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 1356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SBE 0x00010000 136129ba616SKumar Gala 137129ba616SKumar Gala /* 138129ba616SKumar Gala * Make sure required options are set 139129ba616SKumar Gala */ 140129ba616SKumar Gala #ifndef CONFIG_SPD_EEPROM 141129ba616SKumar Gala #error ("CONFIG_SPD_EEPROM is required") 142129ba616SKumar Gala #endif 143129ba616SKumar Gala 144129ba616SKumar Gala #undef CONFIG_CLOCKS_IN_MHZ 145129ba616SKumar Gala 146129ba616SKumar Gala /* 147129ba616SKumar Gala * Memory map 148129ba616SKumar Gala * 149129ba616SKumar Gala * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 150129ba616SKumar Gala * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 151129ba616SKumar Gala * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 152129ba616SKumar Gala * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 153129ba616SKumar Gala * 154129ba616SKumar Gala * Localbus cacheable (TBD) 155129ba616SKumar Gala * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 156129ba616SKumar Gala * 157129ba616SKumar Gala * Localbus non-cacheable 158129ba616SKumar Gala * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 159129ba616SKumar Gala * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 160c013b749SHaiying Wang * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 161129ba616SKumar Gala * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 162129ba616SKumar Gala * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 163129ba616SKumar Gala * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 164129ba616SKumar Gala */ 165129ba616SKumar Gala 166129ba616SKumar Gala /* 167129ba616SKumar Gala * Local Bus Definitions 168129ba616SKumar Gala */ 1696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 17018af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 17118af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 17218af1c5fSKumar Gala #else 173c953ddfdSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 17418af1c5fSKumar Gala #endif 175129ba616SKumar Gala 176c953ddfdSKumar Gala #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 178129ba616SKumar Gala 179c953ddfdSKumar Gala #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 1806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 181129ba616SKumar Gala 18218af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 1836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 184129ba616SKumar Gala #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 185129ba616SKumar Gala 1866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 1876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 1886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CHECKSUM 1896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 191129ba616SKumar Gala 1926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 193129ba616SKumar Gala 194129ba616SKumar Gala #define CONFIG_FLASH_CFI_DRIVER 1956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 1966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 1976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 198129ba616SKumar Gala 199129ba616SKumar Gala #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 200129ba616SKumar Gala 201129ba616SKumar Gala #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 202129ba616SKumar Gala #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 20318af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 20418af1c5fSKumar Gala #define PIXIS_BASE_PHYS 0xfffdf0000ull 20518af1c5fSKumar Gala #else 20652b565f5SKumar Gala #define PIXIS_BASE_PHYS PIXIS_BASE 20718af1c5fSKumar Gala #endif 208129ba616SKumar Gala 20952b565f5SKumar Gala #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 2106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 211129ba616SKumar Gala 212129ba616SKumar Gala #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 213129ba616SKumar Gala #define PIXIS_VER 0x1 /* Board version at offset 1 */ 214129ba616SKumar Gala #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 215129ba616SKumar Gala #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 216129ba616SKumar Gala #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 217129ba616SKumar Gala #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 218129ba616SKumar Gala #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 219129ba616SKumar Gala #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 220129ba616SKumar Gala #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 221129ba616SKumar Gala #define PIXIS_VCTL 0x10 /* VELA Control Register */ 222129ba616SKumar Gala #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 223129ba616SKumar Gala #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 224129ba616SKumar Gala #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 225129ba616SKumar Gala #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 226129ba616SKumar Gala #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 2276bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 2286bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 2296bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 2306bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 2316bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 232129ba616SKumar Gala #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 233129ba616SKumar Gala #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 234129ba616SKumar Gala #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 235129ba616SKumar Gala #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 236129ba616SKumar Gala #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 237129ba616SKumar Gala #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 238129ba616SKumar Gala #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 239129ba616SKumar Gala #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 240129ba616SKumar Gala #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 241129ba616SKumar Gala #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 242129ba616SKumar Gala #define PIXIS_LED 0x25 /* LED Register */ 243129ba616SKumar Gala 244129ba616SKumar Gala /* old pixis referenced names */ 245129ba616SKumar Gala #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 246129ba616SKumar Gala #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 2476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 2487e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC1SER 0x8 2497e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC2SER 0x4 2507e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC3SER 0x2 2517e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC4SER 0x1 2527e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC1SER 0x20 2537e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC2SER 0x20 2547e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC3SER 0x20 2557e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC4SER 0x20 2567e183cadSLiu Yu #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 2577e183cadSLiu Yu | PIXIS_VSPEED2_TSEC2SER \ 2587e183cadSLiu Yu | PIXIS_VSPEED2_TSEC3SER \ 2597e183cadSLiu Yu | PIXIS_VSPEED2_TSEC4SER) 2607e183cadSLiu Yu #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 2617e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC2SER \ 2627e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC3SER \ 2637e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC4SER) 264129ba616SKumar Gala 2656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 2666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 2676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 268129ba616SKumar Gala 2696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 2706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 2716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 272129ba616SKumar Gala 2736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 2746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 275129ba616SKumar Gala 276c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE 0xffa00000 27718af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 27818af1c5fSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 27918af1c5fSKumar Gala #else 280c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 28118af1c5fSKumar Gala #endif 282c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 283c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x40000, \ 284c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x80000,\ 285c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0xC0000} 286c013b749SHaiying Wang #define CONFIG_SYS_MAX_NAND_DEVICE 4 287c013b749SHaiying Wang #define CONFIG_MTD_NAND_VERIFY_WRITE 288c013b749SHaiying Wang #define CONFIG_CMD_NAND 1 289c013b749SHaiying Wang #define CONFIG_NAND_FSL_ELBC 1 290c013b749SHaiying Wang #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 291c013b749SHaiying Wang 292c013b749SHaiying Wang /* NAND flash config */ 29372a9414aSKumar Gala #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 294c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 295c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 296c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 297c013b749SHaiying Wang | BR_V) /* valid */ 298c013b749SHaiying Wang #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 299c013b749SHaiying Wang | OR_FCM_PGS /* Large Page*/ \ 300c013b749SHaiying Wang | OR_FCM_CSCT \ 301c013b749SHaiying Wang | OR_FCM_CST \ 302c013b749SHaiying Wang | OR_FCM_CHT \ 303c013b749SHaiying Wang | OR_FCM_SCY_1 \ 304c013b749SHaiying Wang | OR_FCM_TRLX \ 305c013b749SHaiying Wang | OR_FCM_EHTR) 306c013b749SHaiying Wang 307c013b749SHaiying Wang #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 308c013b749SHaiying Wang #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 309c013b749SHaiying Wang 31072a9414aSKumar Gala #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 311c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 312c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 313c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 314c013b749SHaiying Wang | BR_V) /* valid */ 315c013b749SHaiying Wang #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 31672a9414aSKumar Gala #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 317c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 318c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 319c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 320c013b749SHaiying Wang | BR_V) /* valid */ 321c013b749SHaiying Wang #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 322c013b749SHaiying Wang 32372a9414aSKumar Gala #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 324c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 325c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 326c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 327c013b749SHaiying Wang | BR_V) /* valid */ 328c013b749SHaiying Wang #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 329c013b749SHaiying Wang 330c013b749SHaiying Wang 331129ba616SKumar Gala /* Serial Port - controlled on board with jumper J8 332129ba616SKumar Gala * open - index 2 333129ba616SKumar Gala * shorted - index 1 334129ba616SKumar Gala */ 335129ba616SKumar Gala #define CONFIG_CONS_INDEX 1 3366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 340129ba616SKumar Gala 3416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 342129ba616SKumar Gala {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 343129ba616SKumar Gala 3446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 3456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 346129ba616SKumar Gala 347129ba616SKumar Gala /* Use the HUSH parser */ 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 3496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_HUSH_PARSER 3506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 351129ba616SKumar Gala #endif 352129ba616SKumar Gala 353129ba616SKumar Gala /* 354129ba616SKumar Gala * Pass open firmware flat tree 355129ba616SKumar Gala */ 356129ba616SKumar Gala #define CONFIG_OF_LIBFDT 1 357129ba616SKumar Gala #define CONFIG_OF_BOARD_SETUP 1 358129ba616SKumar Gala #define CONFIG_OF_STDOUT_VIA_ALIAS 1 359129ba616SKumar Gala 360129ba616SKumar Gala /* new uImage format support */ 361129ba616SKumar Gala #define CONFIG_FIT 1 362129ba616SKumar Gala #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 363129ba616SKumar Gala 364129ba616SKumar Gala /* I2C */ 365129ba616SKumar Gala #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 366129ba616SKumar Gala #define CONFIG_HARD_I2C /* I2C with hardware support */ 367129ba616SKumar Gala #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 3681f3ba317SHaiying Wang #define CONFIG_I2C_MULTI_BUS 3696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 3716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 3726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 3736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 375129ba616SKumar Gala 376129ba616SKumar Gala /* 377445a7b38SHaiying Wang * I2C2 EEPROM 378445a7b38SHaiying Wang */ 379445a7b38SHaiying Wang #define CONFIG_ID_EEPROM 380445a7b38SHaiying Wang #ifdef CONFIG_ID_EEPROM 3816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_NXID 382445a7b38SHaiying Wang #endif 3836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 3846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 3856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_EEPROM_BUS_NUM 1 386445a7b38SHaiying Wang 387445a7b38SHaiying Wang /* 388129ba616SKumar Gala * General PCI 389129ba616SKumar Gala * Memory space is mapped 1-1, but I/O space must start from 0. 390129ba616SKumar Gala */ 391129ba616SKumar Gala 392129ba616SKumar Gala /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 3935af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 39418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 395156984a3SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 39618af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 39718af1c5fSKumar Gala #else 398ad97dce1SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 3995af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 40018af1c5fSKumar Gala #endif 4016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 402aca5f018SKumar Gala #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 4035f91ef6aSKumar Gala #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 40418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 40518af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 40618af1c5fSKumar Gala #else 4076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 40818af1c5fSKumar Gala #endif 4096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 410129ba616SKumar Gala 411129ba616SKumar Gala /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 4125af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 41318af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 414156984a3SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 41518af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 41618af1c5fSKumar Gala #else 417ad97dce1SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 4185af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 41918af1c5fSKumar Gala #endif 4206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 421aca5f018SKumar Gala #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 4225f91ef6aSKumar Gala #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 42318af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 42418af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 42518af1c5fSKumar Gala #else 4266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 42718af1c5fSKumar Gala #endif 4286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 429129ba616SKumar Gala 430129ba616SKumar Gala /* controller 1, Slot 1, tgtid 1, Base address a000 */ 4315af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 43218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 433156984a3SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 43418af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 43518af1c5fSKumar Gala #else 436ad97dce1SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 4375af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 43818af1c5fSKumar Gala #endif 4396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 440aca5f018SKumar Gala #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 4415f91ef6aSKumar Gala #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 44218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 44318af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 44418af1c5fSKumar Gala #else 4456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 44618af1c5fSKumar Gala #endif 4476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 448129ba616SKumar Gala 449129ba616SKumar Gala #if defined(CONFIG_PCI) 450129ba616SKumar Gala 451129ba616SKumar Gala /*PCIE video card used*/ 452aca5f018SKumar Gala #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 453129ba616SKumar Gala 454129ba616SKumar Gala /* video */ 455129ba616SKumar Gala #define CONFIG_VIDEO 456129ba616SKumar Gala 457129ba616SKumar Gala #if defined(CONFIG_VIDEO) 458129ba616SKumar Gala #define CONFIG_BIOSEMU 459129ba616SKumar Gala #define CONFIG_CFB_CONSOLE 460129ba616SKumar Gala #define CONFIG_VIDEO_SW_CURSOR 461129ba616SKumar Gala #define CONFIG_VGA_AS_SINGLE_DEVICE 462129ba616SKumar Gala #define CONFIG_ATI_RADEON_FB 463129ba616SKumar Gala #define CONFIG_VIDEO_LOGO 464129ba616SKumar Gala /*#define CONFIG_CONSOLE_CURSOR*/ 4656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 466129ba616SKumar Gala #endif 467129ba616SKumar Gala 468129ba616SKumar Gala #define CONFIG_NET_MULTI 469129ba616SKumar Gala #define CONFIG_PCI_PNP /* do pci plug-and-play */ 470129ba616SKumar Gala 471129ba616SKumar Gala #undef CONFIG_EEPRO100 472129ba616SKumar Gala #undef CONFIG_TULIP 473129ba616SKumar Gala #undef CONFIG_RTL8139 474129ba616SKumar Gala 475129ba616SKumar Gala #ifndef CONFIG_PCI_PNP 4765f91ef6aSKumar Gala #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 4775f91ef6aSKumar Gala #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 478129ba616SKumar Gala #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 479129ba616SKumar Gala #endif 480129ba616SKumar Gala 481129ba616SKumar Gala #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 482129ba616SKumar Gala #define CONFIG_DOS_PARTITION 483129ba616SKumar Gala #define CONFIG_SCSI_AHCI 484129ba616SKumar Gala 485129ba616SKumar Gala #ifdef CONFIG_SCSI_AHCI 486129ba616SKumar Gala #define CONFIG_SATA_ULI5288 4876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 4886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_LUN 1 4896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 4906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 491129ba616SKumar Gala #endif /* SCSI */ 492129ba616SKumar Gala 493129ba616SKumar Gala #endif /* CONFIG_PCI */ 494129ba616SKumar Gala 495129ba616SKumar Gala 496129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 497129ba616SKumar Gala 498129ba616SKumar Gala #ifndef CONFIG_NET_MULTI 499129ba616SKumar Gala #define CONFIG_NET_MULTI 1 500129ba616SKumar Gala #endif 501129ba616SKumar Gala 502129ba616SKumar Gala #define CONFIG_MII 1 /* MII PHY management */ 503129ba616SKumar Gala #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 504129ba616SKumar Gala #define CONFIG_TSEC1 1 505129ba616SKumar Gala #define CONFIG_TSEC1_NAME "eTSEC1" 506129ba616SKumar Gala #define CONFIG_TSEC2 1 507129ba616SKumar Gala #define CONFIG_TSEC2_NAME "eTSEC2" 508129ba616SKumar Gala #define CONFIG_TSEC3 1 509129ba616SKumar Gala #define CONFIG_TSEC3_NAME "eTSEC3" 510129ba616SKumar Gala #define CONFIG_TSEC4 1 511129ba616SKumar Gala #define CONFIG_TSEC4_NAME "eTSEC4" 512129ba616SKumar Gala 5137e183cadSLiu Yu #define CONFIG_PIXIS_SGMII_CMD 5147e183cadSLiu Yu #define CONFIG_FSL_SGMII_RISER 1 5157e183cadSLiu Yu #define SGMII_RISER_PHY_OFFSET 0x1c 5167e183cadSLiu Yu 5177e183cadSLiu Yu #ifdef CONFIG_FSL_SGMII_RISER 5187e183cadSLiu Yu #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 5197e183cadSLiu Yu #endif 5207e183cadSLiu Yu 521129ba616SKumar Gala #define TSEC1_PHY_ADDR 0 522129ba616SKumar Gala #define TSEC2_PHY_ADDR 1 523129ba616SKumar Gala #define TSEC3_PHY_ADDR 2 524129ba616SKumar Gala #define TSEC4_PHY_ADDR 3 525129ba616SKumar Gala 526129ba616SKumar Gala #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 527129ba616SKumar Gala #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 528129ba616SKumar Gala #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 529129ba616SKumar Gala #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 530129ba616SKumar Gala 531129ba616SKumar Gala #define TSEC1_PHYIDX 0 532129ba616SKumar Gala #define TSEC2_PHYIDX 0 533129ba616SKumar Gala #define TSEC3_PHYIDX 0 534129ba616SKumar Gala #define TSEC4_PHYIDX 0 535129ba616SKumar Gala 536129ba616SKumar Gala #define CONFIG_ETHPRIME "eTSEC1" 537129ba616SKumar Gala 538129ba616SKumar Gala #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 539129ba616SKumar Gala #endif /* CONFIG_TSEC_ENET */ 540129ba616SKumar Gala 541129ba616SKumar Gala /* 542129ba616SKumar Gala * Environment 543129ba616SKumar Gala */ 5445a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 5456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 5460e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR 0xfff80000 547129ba616SKumar Gala #else 5486fc110bdSHaiying Wang #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 549129ba616SKumar Gala #endif 5500e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 5510e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 552129ba616SKumar Gala 553129ba616SKumar Gala #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 5546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 555129ba616SKumar Gala 556129ba616SKumar Gala /* 557129ba616SKumar Gala * Command line configuration. 558129ba616SKumar Gala */ 559129ba616SKumar Gala #include <config_cmd_default.h> 560129ba616SKumar Gala 561129ba616SKumar Gala #define CONFIG_CMD_IRQ 562129ba616SKumar Gala #define CONFIG_CMD_PING 563129ba616SKumar Gala #define CONFIG_CMD_I2C 564129ba616SKumar Gala #define CONFIG_CMD_MII 565129ba616SKumar Gala #define CONFIG_CMD_ELF 5661c9aa76bSKumar Gala #define CONFIG_CMD_IRQ 5671c9aa76bSKumar Gala #define CONFIG_CMD_SETEXPR 568199e262eSBecky Bruce #define CONFIG_CMD_REGINFO 569129ba616SKumar Gala 570129ba616SKumar Gala #if defined(CONFIG_PCI) 571129ba616SKumar Gala #define CONFIG_CMD_PCI 572129ba616SKumar Gala #define CONFIG_CMD_NET 573129ba616SKumar Gala #define CONFIG_CMD_SCSI 574129ba616SKumar Gala #define CONFIG_CMD_EXT2 575129ba616SKumar Gala #endif 576129ba616SKumar Gala 577129ba616SKumar Gala #undef CONFIG_WATCHDOG /* watchdog disabled */ 578129ba616SKumar Gala 579129ba616SKumar Gala /* 580129ba616SKumar Gala * Miscellaneous configurable options 581129ba616SKumar Gala */ 5826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 583129ba616SKumar Gala #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 5845be58f5fSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 5856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 5866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 587129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 5886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 589129ba616SKumar Gala #else 5906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 591129ba616SKumar Gala #endif 5926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 5936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 5946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 5956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 596129ba616SKumar Gala 597129ba616SKumar Gala /* 598129ba616SKumar Gala * For booting Linux, the board info and command line data 59989188a62SKumar Gala * have to be in the first 16 MB of memory, since this is 600129ba616SKumar Gala * the maximum mapped by the Linux kernel during initialization. 601129ba616SKumar Gala */ 60289188a62SKumar Gala #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 603129ba616SKumar Gala 604129ba616SKumar Gala /* 605129ba616SKumar Gala * Internal Definitions 606129ba616SKumar Gala * 607129ba616SKumar Gala * Boot Flags 608129ba616SKumar Gala */ 609129ba616SKumar Gala #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 610129ba616SKumar Gala #define BOOTFLAG_WARM 0x02 /* Software reboot */ 611129ba616SKumar Gala 612129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 613129ba616SKumar Gala #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 614129ba616SKumar Gala #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 615129ba616SKumar Gala #endif 616129ba616SKumar Gala 617129ba616SKumar Gala /* 618129ba616SKumar Gala * Environment Configuration 619129ba616SKumar Gala */ 620129ba616SKumar Gala 621129ba616SKumar Gala /* The mac addresses for all ethernet interface */ 622129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 623129ba616SKumar Gala #define CONFIG_HAS_ETH0 624129ba616SKumar Gala #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 625129ba616SKumar Gala #define CONFIG_HAS_ETH1 626129ba616SKumar Gala #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 627129ba616SKumar Gala #define CONFIG_HAS_ETH2 628129ba616SKumar Gala #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 629129ba616SKumar Gala #define CONFIG_HAS_ETH3 630129ba616SKumar Gala #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 631129ba616SKumar Gala #endif 632129ba616SKumar Gala 633129ba616SKumar Gala #define CONFIG_IPADDR 192.168.1.254 634129ba616SKumar Gala 635129ba616SKumar Gala #define CONFIG_HOSTNAME unknown 636129ba616SKumar Gala #define CONFIG_ROOTPATH /opt/nfsroot 637129ba616SKumar Gala #define CONFIG_BOOTFILE uImage 638129ba616SKumar Gala #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 639129ba616SKumar Gala 640129ba616SKumar Gala #define CONFIG_SERVERIP 192.168.1.1 641129ba616SKumar Gala #define CONFIG_GATEWAYIP 192.168.1.1 642129ba616SKumar Gala #define CONFIG_NETMASK 255.255.255.0 643129ba616SKumar Gala 644129ba616SKumar Gala /* default location for tftp and bootm */ 645129ba616SKumar Gala #define CONFIG_LOADADDR 1000000 646129ba616SKumar Gala 647129ba616SKumar Gala #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 648129ba616SKumar Gala #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 649129ba616SKumar Gala 650129ba616SKumar Gala #define CONFIG_BAUDRATE 115200 651129ba616SKumar Gala 652129ba616SKumar Gala #define CONFIG_EXTRA_ENV_SETTINGS \ 6534ca06607SHaiying Wang "memctl_intlv_ctl=2\0" \ 654129ba616SKumar Gala "netdev=eth0\0" \ 655129ba616SKumar Gala "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 656129ba616SKumar Gala "tftpflash=tftpboot $loadaddr $uboot; " \ 657129ba616SKumar Gala "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 658129ba616SKumar Gala "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 659129ba616SKumar Gala "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 660129ba616SKumar Gala "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 661129ba616SKumar Gala "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 662129ba616SKumar Gala "consoledev=ttyS0\0" \ 663129ba616SKumar Gala "ramdiskaddr=2000000\0" \ 664129ba616SKumar Gala "ramdiskfile=8572ds/ramdisk.uboot\0" \ 665129ba616SKumar Gala "fdtaddr=c00000\0" \ 666129ba616SKumar Gala "fdtfile=8572ds/mpc8572ds.dtb\0" \ 667129ba616SKumar Gala "bdev=sda3\0" 668129ba616SKumar Gala 669129ba616SKumar Gala #define CONFIG_HDBOOT \ 670129ba616SKumar Gala "setenv bootargs root=/dev/$bdev rw " \ 671129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 672129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 673129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 674129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 675129ba616SKumar Gala 676129ba616SKumar Gala #define CONFIG_NFSBOOTCOMMAND \ 677129ba616SKumar Gala "setenv bootargs root=/dev/nfs rw " \ 678129ba616SKumar Gala "nfsroot=$serverip:$rootpath " \ 679129ba616SKumar Gala "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 680129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 681129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 682129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 683129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 684129ba616SKumar Gala 685129ba616SKumar Gala #define CONFIG_RAMBOOTCOMMAND \ 686129ba616SKumar Gala "setenv bootargs root=/dev/ram rw " \ 687129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 688129ba616SKumar Gala "tftp $ramdiskaddr $ramdiskfile;" \ 689129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 690129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 691129ba616SKumar Gala "bootm $loadaddr $ramdiskaddr $fdtaddr" 692129ba616SKumar Gala 693129ba616SKumar Gala #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 694129ba616SKumar Gala 695129ba616SKumar Gala #endif /* __CONFIG_H */ 696