1129ba616SKumar Gala /* 2129ba616SKumar Gala * Copyright 2007-2008 Freescale Semiconductor, Inc. 3129ba616SKumar Gala * 4129ba616SKumar Gala * See file CREDITS for list of people who contributed to this 5129ba616SKumar Gala * project. 6129ba616SKumar Gala * 7129ba616SKumar Gala * This program is free software; you can redistribute it and/or 8129ba616SKumar Gala * modify it under the terms of the GNU General Public License as 9129ba616SKumar Gala * published by the Free Software Foundation; either version 2 of 10129ba616SKumar Gala * the License, or (at your option) any later version. 11129ba616SKumar Gala * 12129ba616SKumar Gala * This program is distributed in the hope that it will be useful, 13129ba616SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 14129ba616SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15129ba616SKumar Gala * GNU General Public License for more details. 16129ba616SKumar Gala * 17129ba616SKumar Gala * You should have received a copy of the GNU General Public License 18129ba616SKumar Gala * along with this program; if not, write to the Free Software 19129ba616SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20129ba616SKumar Gala * MA 02111-1307 USA 21129ba616SKumar Gala */ 22129ba616SKumar Gala 23129ba616SKumar Gala /* 24129ba616SKumar Gala * mpc8572ds board configuration file 25129ba616SKumar Gala * 26129ba616SKumar Gala */ 27129ba616SKumar Gala #ifndef __CONFIG_H 28129ba616SKumar Gala #define __CONFIG_H 29129ba616SKumar Gala 30129ba616SKumar Gala /* High Level Configuration Options */ 31129ba616SKumar Gala #define CONFIG_BOOKE 1 /* BOOKE */ 32129ba616SKumar Gala #define CONFIG_E500 1 /* BOOKE e500 family */ 33129ba616SKumar Gala #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34129ba616SKumar Gala #define CONFIG_MPC8572 1 35129ba616SKumar Gala #define CONFIG_MPC8572DS 1 36129ba616SKumar Gala #define CONFIG_MP 1 /* support multiple processors */ 37129ba616SKumar Gala #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 38129ba616SKumar Gala 39*c51fc5d5SKumar Gala #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 40129ba616SKumar Gala #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 41129ba616SKumar Gala #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 42129ba616SKumar Gala #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 43129ba616SKumar Gala #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 44129ba616SKumar Gala #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45129ba616SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 460151cbacSKumar Gala #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 47129ba616SKumar Gala 48129ba616SKumar Gala #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 49129ba616SKumar Gala 50129ba616SKumar Gala #define CONFIG_TSEC_ENET /* tsec ethernet support */ 51129ba616SKumar Gala #define CONFIG_ENV_OVERWRITE 52129ba616SKumar Gala 53129ba616SKumar Gala /* 54129ba616SKumar Gala * When initializing flash, if we cannot find the manufacturer ID, 55129ba616SKumar Gala * assume this is the AMD flash associated with the CDS board. 56129ba616SKumar Gala * This allows booting from a promjet. 57129ba616SKumar Gala */ 58129ba616SKumar Gala #define CONFIG_ASSUME_AMD_FLASH 59129ba616SKumar Gala 60129ba616SKumar Gala #ifndef __ASSEMBLY__ 61129ba616SKumar Gala extern unsigned long get_board_sys_clk(unsigned long dummy); 62129ba616SKumar Gala extern unsigned long get_board_ddr_clk(unsigned long dummy); 63129ba616SKumar Gala #endif 64129ba616SKumar Gala #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 65129ba616SKumar Gala #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 664ca06607SHaiying Wang #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 67129ba616SKumar Gala #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 68129ba616SKumar Gala from ICS307 instead of switches */ 69129ba616SKumar Gala 70129ba616SKumar Gala /* 71129ba616SKumar Gala * These can be toggled for performance analysis, otherwise use default. 72129ba616SKumar Gala */ 73129ba616SKumar Gala #define CONFIG_L2_CACHE /* toggle L2 cache */ 74129ba616SKumar Gala #define CONFIG_BTB /* toggle branch predition */ 75129ba616SKumar Gala 76129ba616SKumar Gala #define CONFIG_ENABLE_36BIT_PHYS 1 77129ba616SKumar Gala 786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x7fffffff 80129ba616SKumar Gala #define CONFIG_PANIC_HANG /* do not reset board on panic */ 81129ba616SKumar Gala 82129ba616SKumar Gala /* 83129ba616SKumar Gala * Base addresses -- Note these are effective addresses where the 84129ba616SKumar Gala * actual resources get mapped (not physical addresses) 85129ba616SKumar Gala */ 866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 90129ba616SKumar Gala 916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 94129ba616SKumar Gala 95129ba616SKumar Gala /* DDR Setup */ 96b5f65dfaSHaiying Wang #define CONFIG_SYS_DDR_TLB_START 9 97129ba616SKumar Gala #define CONFIG_FSL_DDR2 98129ba616SKumar Gala #undef CONFIG_FSL_DDR_INTERACTIVE 99129ba616SKumar Gala #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 100129ba616SKumar Gala #define CONFIG_DDR_SPD 101129ba616SKumar Gala #undef CONFIG_DDR_DLL 102129ba616SKumar Gala 1039b0ad1b1SDave Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 104129ba616SKumar Gala #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 105129ba616SKumar Gala 1066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 108129ba616SKumar Gala 109129ba616SKumar Gala #define CONFIG_NUM_DDR_CONTROLLERS 2 110129ba616SKumar Gala #define CONFIG_DIMM_SLOTS_PER_CTLR 1 111129ba616SKumar Gala #define CONFIG_CHIP_SELECTS_PER_CTRL 2 112129ba616SKumar Gala 113129ba616SKumar Gala /* I2C addresses of SPD EEPROMs */ 1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 115129ba616SKumar Gala #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 116129ba616SKumar Gala #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 117129ba616SKumar Gala 118129ba616SKumar Gala /* These are used when DDR doesn't use SPD. */ 119dc889e86SDave Liu #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 121dc889e86SDave Liu #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 122dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_3 0x00020000 1236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 0x00260802 124dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 125dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 126dc889e86SDave Liu #define CONFIG_SYS_DDR_MODE_1 0x00440462 1276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x00000000 128dc889e86SDave Liu #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 1296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 130dc889e86SDave Liu #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 1316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 1326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 133dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 134dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL2 0x24400000 135129ba616SKumar Gala 1366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 1376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 1386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SBE 0x00010000 139129ba616SKumar Gala 140129ba616SKumar Gala /* 141129ba616SKumar Gala * Make sure required options are set 142129ba616SKumar Gala */ 143129ba616SKumar Gala #ifndef CONFIG_SPD_EEPROM 144129ba616SKumar Gala #error ("CONFIG_SPD_EEPROM is required") 145129ba616SKumar Gala #endif 146129ba616SKumar Gala 147129ba616SKumar Gala #undef CONFIG_CLOCKS_IN_MHZ 148129ba616SKumar Gala 149129ba616SKumar Gala /* 150129ba616SKumar Gala * Memory map 151129ba616SKumar Gala * 152129ba616SKumar Gala * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 153129ba616SKumar Gala * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 154129ba616SKumar Gala * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 155129ba616SKumar Gala * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 156129ba616SKumar Gala * 157129ba616SKumar Gala * Localbus cacheable (TBD) 158129ba616SKumar Gala * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 159129ba616SKumar Gala * 160129ba616SKumar Gala * Localbus non-cacheable 161129ba616SKumar Gala * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 162129ba616SKumar Gala * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 163c013b749SHaiying Wang * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 164129ba616SKumar Gala * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 165129ba616SKumar Gala * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 166129ba616SKumar Gala * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 167129ba616SKumar Gala */ 168129ba616SKumar Gala 169129ba616SKumar Gala /* 170129ba616SKumar Gala * Local Bus Definitions 171129ba616SKumar Gala */ 1726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 173c953ddfdSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 174129ba616SKumar Gala 175c953ddfdSKumar Gala #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 1766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 177129ba616SKumar Gala 178c953ddfdSKumar Gala #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 1796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 180129ba616SKumar Gala 1816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} 1826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 183129ba616SKumar Gala #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 184129ba616SKumar Gala 1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 1866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 1876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CHECKSUM 1886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 1896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 190129ba616SKumar Gala 1916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 192129ba616SKumar Gala 193129ba616SKumar Gala #define CONFIG_FLASH_CFI_DRIVER 1946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 1956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 1966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 197129ba616SKumar Gala 198129ba616SKumar Gala #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 199129ba616SKumar Gala 200129ba616SKumar Gala #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 201129ba616SKumar Gala #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 20252b565f5SKumar Gala #define PIXIS_BASE_PHYS PIXIS_BASE 203129ba616SKumar Gala 20452b565f5SKumar Gala #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 206129ba616SKumar Gala 207129ba616SKumar Gala #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 208129ba616SKumar Gala #define PIXIS_VER 0x1 /* Board version at offset 1 */ 209129ba616SKumar Gala #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 210129ba616SKumar Gala #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 211129ba616SKumar Gala #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 212129ba616SKumar Gala #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 213129ba616SKumar Gala #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 214129ba616SKumar Gala #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 215129ba616SKumar Gala #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 216129ba616SKumar Gala #define PIXIS_VCTL 0x10 /* VELA Control Register */ 217129ba616SKumar Gala #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 218129ba616SKumar Gala #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 219129ba616SKumar Gala #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 220129ba616SKumar Gala #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 221129ba616SKumar Gala #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 222129ba616SKumar Gala #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 223129ba616SKumar Gala #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 224129ba616SKumar Gala #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 225129ba616SKumar Gala #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 226129ba616SKumar Gala #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 227129ba616SKumar Gala #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 228129ba616SKumar Gala #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 229129ba616SKumar Gala #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 230129ba616SKumar Gala #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 231129ba616SKumar Gala #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 232129ba616SKumar Gala #define PIXIS_LED 0x25 /* LED Register */ 233129ba616SKumar Gala 234129ba616SKumar Gala /* old pixis referenced names */ 235129ba616SKumar Gala #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 236129ba616SKumar Gala #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 2376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 2387e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC1SER 0x8 2397e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC2SER 0x4 2407e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC3SER 0x2 2417e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC4SER 0x1 2427e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC1SER 0x20 2437e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC2SER 0x20 2447e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC3SER 0x20 2457e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC4SER 0x20 2467e183cadSLiu Yu #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 2477e183cadSLiu Yu | PIXIS_VSPEED2_TSEC2SER \ 2487e183cadSLiu Yu | PIXIS_VSPEED2_TSEC3SER \ 2497e183cadSLiu Yu | PIXIS_VSPEED2_TSEC4SER) 2507e183cadSLiu Yu #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 2517e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC2SER \ 2527e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC3SER \ 2537e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC4SER) 254129ba616SKumar Gala 2556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 2566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 2576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 258129ba616SKumar Gala 2596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 2606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 2616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 262129ba616SKumar Gala 2636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 2646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 265129ba616SKumar Gala 266c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE 0xffa00000 267c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 268c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 269c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x40000, \ 270c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x80000,\ 271c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0xC0000} 272c013b749SHaiying Wang #define CONFIG_SYS_MAX_NAND_DEVICE 4 273c013b749SHaiying Wang #define CONFIG_MTD_NAND_VERIFY_WRITE 274c013b749SHaiying Wang #define CONFIG_CMD_NAND 1 275c013b749SHaiying Wang #define CONFIG_NAND_FSL_ELBC 1 276c013b749SHaiying Wang #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 277c013b749SHaiying Wang 278c013b749SHaiying Wang /* NAND flash config */ 27972a9414aSKumar Gala #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 280c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 281c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 282c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 283c013b749SHaiying Wang | BR_V) /* valid */ 284c013b749SHaiying Wang #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 285c013b749SHaiying Wang | OR_FCM_PGS /* Large Page*/ \ 286c013b749SHaiying Wang | OR_FCM_CSCT \ 287c013b749SHaiying Wang | OR_FCM_CST \ 288c013b749SHaiying Wang | OR_FCM_CHT \ 289c013b749SHaiying Wang | OR_FCM_SCY_1 \ 290c013b749SHaiying Wang | OR_FCM_TRLX \ 291c013b749SHaiying Wang | OR_FCM_EHTR) 292c013b749SHaiying Wang 293c013b749SHaiying Wang #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 294c013b749SHaiying Wang #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 295c013b749SHaiying Wang 29672a9414aSKumar Gala #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 297c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 298c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 299c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 300c013b749SHaiying Wang | BR_V) /* valid */ 301c013b749SHaiying Wang #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 30272a9414aSKumar Gala #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 303c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 304c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 305c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 306c013b749SHaiying Wang | BR_V) /* valid */ 307c013b749SHaiying Wang #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 308c013b749SHaiying Wang 30972a9414aSKumar Gala #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 310c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 311c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 312c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 313c013b749SHaiying Wang | BR_V) /* valid */ 314c013b749SHaiying Wang #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 315c013b749SHaiying Wang 316c013b749SHaiying Wang 317129ba616SKumar Gala /* Serial Port - controlled on board with jumper J8 318129ba616SKumar Gala * open - index 2 319129ba616SKumar Gala * shorted - index 1 320129ba616SKumar Gala */ 321129ba616SKumar Gala #define CONFIG_CONS_INDEX 1 322129ba616SKumar Gala #undef CONFIG_SERIAL_SOFTWARE_FIFO 3236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 327129ba616SKumar Gala 3286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 329129ba616SKumar Gala {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 330129ba616SKumar Gala 3316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 3326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 333129ba616SKumar Gala 334129ba616SKumar Gala /* Use the HUSH parser */ 3356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 3366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_HUSH_PARSER 3376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 338129ba616SKumar Gala #endif 339129ba616SKumar Gala 340129ba616SKumar Gala /* 341129ba616SKumar Gala * Pass open firmware flat tree 342129ba616SKumar Gala */ 343129ba616SKumar Gala #define CONFIG_OF_LIBFDT 1 344129ba616SKumar Gala #define CONFIG_OF_BOARD_SETUP 1 345129ba616SKumar Gala #define CONFIG_OF_STDOUT_VIA_ALIAS 1 346129ba616SKumar Gala 3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_64BIT_VSPRINTF 1 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_64BIT_STRTOUL 1 349129ba616SKumar Gala 350129ba616SKumar Gala /* new uImage format support */ 351129ba616SKumar Gala #define CONFIG_FIT 1 352129ba616SKumar Gala #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 353129ba616SKumar Gala 354129ba616SKumar Gala /* I2C */ 355129ba616SKumar Gala #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 356129ba616SKumar Gala #define CONFIG_HARD_I2C /* I2C with hardware support */ 357129ba616SKumar Gala #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 3581f3ba317SHaiying Wang #define CONFIG_I2C_MULTI_BUS 3591f3ba317SHaiying Wang #define CONFIG_I2C_CMD_TREE 3606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 3616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 3626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 3636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 3646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 3656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 366129ba616SKumar Gala 367129ba616SKumar Gala /* 368445a7b38SHaiying Wang * I2C2 EEPROM 369445a7b38SHaiying Wang */ 370445a7b38SHaiying Wang #define CONFIG_ID_EEPROM 371445a7b38SHaiying Wang #ifdef CONFIG_ID_EEPROM 3726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_NXID 373445a7b38SHaiying Wang #endif 3746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 3756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 3766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_EEPROM_BUS_NUM 1 377445a7b38SHaiying Wang 378445a7b38SHaiying Wang /* 379129ba616SKumar Gala * General PCI 380129ba616SKumar Gala * Memory space is mapped 1-1, but I/O space must start from 0. 381129ba616SKumar Gala */ 382129ba616SKumar Gala 383129ba616SKumar Gala /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 3845af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 38510795f42SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 3865af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 3876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 388aca5f018SKumar Gala #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 3895f91ef6aSKumar Gala #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 3906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 3916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 392129ba616SKumar Gala 393129ba616SKumar Gala /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 3945af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 39510795f42SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 3965af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 3976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 398aca5f018SKumar Gala #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 3995f91ef6aSKumar Gala #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 4006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 4016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 402129ba616SKumar Gala 403129ba616SKumar Gala /* controller 1, Slot 1, tgtid 1, Base address a000 */ 4045af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 40510795f42SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 4065af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 4076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 408aca5f018SKumar Gala #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 4095f91ef6aSKumar Gala #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 4106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 4116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 412129ba616SKumar Gala 413129ba616SKumar Gala #if defined(CONFIG_PCI) 414129ba616SKumar Gala 415129ba616SKumar Gala /*PCIE video card used*/ 416aca5f018SKumar Gala #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 417129ba616SKumar Gala 418129ba616SKumar Gala /* video */ 419129ba616SKumar Gala #define CONFIG_VIDEO 420129ba616SKumar Gala 421129ba616SKumar Gala #if defined(CONFIG_VIDEO) 422129ba616SKumar Gala #define CONFIG_BIOSEMU 423129ba616SKumar Gala #define CONFIG_CFB_CONSOLE 424129ba616SKumar Gala #define CONFIG_VIDEO_SW_CURSOR 425129ba616SKumar Gala #define CONFIG_VGA_AS_SINGLE_DEVICE 426129ba616SKumar Gala #define CONFIG_ATI_RADEON_FB 427129ba616SKumar Gala #define CONFIG_VIDEO_LOGO 428129ba616SKumar Gala /*#define CONFIG_CONSOLE_CURSOR*/ 4296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 430129ba616SKumar Gala #endif 431129ba616SKumar Gala 432129ba616SKumar Gala #define CONFIG_NET_MULTI 433129ba616SKumar Gala #define CONFIG_PCI_PNP /* do pci plug-and-play */ 434129ba616SKumar Gala 435129ba616SKumar Gala #undef CONFIG_EEPRO100 436129ba616SKumar Gala #undef CONFIG_TULIP 437129ba616SKumar Gala #undef CONFIG_RTL8139 438129ba616SKumar Gala 439129ba616SKumar Gala #ifdef CONFIG_RTL8139 440129ba616SKumar Gala /* This macro is used by RTL8139 but not defined in PPC architecture */ 441129ba616SKumar Gala #define KSEG1ADDR(x) (x) 442129ba616SKumar Gala #define _IO_BASE 0x00000000 443129ba616SKumar Gala #endif 444129ba616SKumar Gala 445129ba616SKumar Gala #ifndef CONFIG_PCI_PNP 4465f91ef6aSKumar Gala #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 4475f91ef6aSKumar Gala #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 448129ba616SKumar Gala #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 449129ba616SKumar Gala #endif 450129ba616SKumar Gala 451129ba616SKumar Gala #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 452129ba616SKumar Gala #define CONFIG_DOS_PARTITION 453129ba616SKumar Gala #define CONFIG_SCSI_AHCI 454129ba616SKumar Gala 455129ba616SKumar Gala #ifdef CONFIG_SCSI_AHCI 456129ba616SKumar Gala #define CONFIG_SATA_ULI5288 4576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 4586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_LUN 1 4596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 4606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 461129ba616SKumar Gala #endif /* SCSI */ 462129ba616SKumar Gala 463129ba616SKumar Gala #endif /* CONFIG_PCI */ 464129ba616SKumar Gala 465129ba616SKumar Gala 466129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 467129ba616SKumar Gala 468129ba616SKumar Gala #ifndef CONFIG_NET_MULTI 469129ba616SKumar Gala #define CONFIG_NET_MULTI 1 470129ba616SKumar Gala #endif 471129ba616SKumar Gala 472129ba616SKumar Gala #define CONFIG_MII 1 /* MII PHY management */ 473129ba616SKumar Gala #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 474129ba616SKumar Gala #define CONFIG_TSEC1 1 475129ba616SKumar Gala #define CONFIG_TSEC1_NAME "eTSEC1" 476129ba616SKumar Gala #define CONFIG_TSEC2 1 477129ba616SKumar Gala #define CONFIG_TSEC2_NAME "eTSEC2" 478129ba616SKumar Gala #define CONFIG_TSEC3 1 479129ba616SKumar Gala #define CONFIG_TSEC3_NAME "eTSEC3" 480129ba616SKumar Gala #define CONFIG_TSEC4 1 481129ba616SKumar Gala #define CONFIG_TSEC4_NAME "eTSEC4" 482129ba616SKumar Gala 4837e183cadSLiu Yu #define CONFIG_PIXIS_SGMII_CMD 4847e183cadSLiu Yu #define CONFIG_FSL_SGMII_RISER 1 4857e183cadSLiu Yu #define SGMII_RISER_PHY_OFFSET 0x1c 4867e183cadSLiu Yu 4877e183cadSLiu Yu #ifdef CONFIG_FSL_SGMII_RISER 4887e183cadSLiu Yu #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 4897e183cadSLiu Yu #endif 4907e183cadSLiu Yu 491129ba616SKumar Gala #define TSEC1_PHY_ADDR 0 492129ba616SKumar Gala #define TSEC2_PHY_ADDR 1 493129ba616SKumar Gala #define TSEC3_PHY_ADDR 2 494129ba616SKumar Gala #define TSEC4_PHY_ADDR 3 495129ba616SKumar Gala 496129ba616SKumar Gala #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 497129ba616SKumar Gala #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 498129ba616SKumar Gala #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 499129ba616SKumar Gala #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 500129ba616SKumar Gala 501129ba616SKumar Gala #define TSEC1_PHYIDX 0 502129ba616SKumar Gala #define TSEC2_PHYIDX 0 503129ba616SKumar Gala #define TSEC3_PHYIDX 0 504129ba616SKumar Gala #define TSEC4_PHYIDX 0 505129ba616SKumar Gala 506129ba616SKumar Gala #define CONFIG_ETHPRIME "eTSEC1" 507129ba616SKumar Gala 508129ba616SKumar Gala #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 509129ba616SKumar Gala #endif /* CONFIG_TSEC_ENET */ 510129ba616SKumar Gala 511129ba616SKumar Gala /* 512129ba616SKumar Gala * Environment 513129ba616SKumar Gala */ 5145a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 5156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 5160e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR 0xfff80000 517129ba616SKumar Gala #else 5186fc110bdSHaiying Wang #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 519129ba616SKumar Gala #endif 5200e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 5210e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 522129ba616SKumar Gala 523129ba616SKumar Gala #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 5246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 525129ba616SKumar Gala 526129ba616SKumar Gala /* 527129ba616SKumar Gala * Command line configuration. 528129ba616SKumar Gala */ 529129ba616SKumar Gala #include <config_cmd_default.h> 530129ba616SKumar Gala 531129ba616SKumar Gala #define CONFIG_CMD_IRQ 532129ba616SKumar Gala #define CONFIG_CMD_PING 533129ba616SKumar Gala #define CONFIG_CMD_I2C 534129ba616SKumar Gala #define CONFIG_CMD_MII 535129ba616SKumar Gala #define CONFIG_CMD_ELF 5361c9aa76bSKumar Gala #define CONFIG_CMD_IRQ 5371c9aa76bSKumar Gala #define CONFIG_CMD_SETEXPR 538129ba616SKumar Gala 539129ba616SKumar Gala #if defined(CONFIG_PCI) 540129ba616SKumar Gala #define CONFIG_CMD_PCI 541129ba616SKumar Gala #define CONFIG_CMD_BEDBUG 542129ba616SKumar Gala #define CONFIG_CMD_NET 543129ba616SKumar Gala #define CONFIG_CMD_SCSI 544129ba616SKumar Gala #define CONFIG_CMD_EXT2 545129ba616SKumar Gala #endif 546129ba616SKumar Gala 547129ba616SKumar Gala #undef CONFIG_WATCHDOG /* watchdog disabled */ 548129ba616SKumar Gala 549129ba616SKumar Gala /* 550129ba616SKumar Gala * Miscellaneous configurable options 551129ba616SKumar Gala */ 5526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 553129ba616SKumar Gala #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 5546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 5556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 556129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 5576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 558129ba616SKumar Gala #else 5596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 560129ba616SKumar Gala #endif 5616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 5626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 5636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 5646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 565129ba616SKumar Gala 566129ba616SKumar Gala /* 567129ba616SKumar Gala * For booting Linux, the board info and command line data 568129ba616SKumar Gala * have to be in the first 8 MB of memory, since this is 569129ba616SKumar Gala * the maximum mapped by the Linux kernel during initialization. 570129ba616SKumar Gala */ 5716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 572129ba616SKumar Gala 573129ba616SKumar Gala /* 574129ba616SKumar Gala * Internal Definitions 575129ba616SKumar Gala * 576129ba616SKumar Gala * Boot Flags 577129ba616SKumar Gala */ 578129ba616SKumar Gala #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 579129ba616SKumar Gala #define BOOTFLAG_WARM 0x02 /* Software reboot */ 580129ba616SKumar Gala 581129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 582129ba616SKumar Gala #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 583129ba616SKumar Gala #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 584129ba616SKumar Gala #endif 585129ba616SKumar Gala 586129ba616SKumar Gala /* 587129ba616SKumar Gala * Environment Configuration 588129ba616SKumar Gala */ 589129ba616SKumar Gala 590129ba616SKumar Gala /* The mac addresses for all ethernet interface */ 591129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 592129ba616SKumar Gala #define CONFIG_HAS_ETH0 593129ba616SKumar Gala #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 594129ba616SKumar Gala #define CONFIG_HAS_ETH1 595129ba616SKumar Gala #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 596129ba616SKumar Gala #define CONFIG_HAS_ETH2 597129ba616SKumar Gala #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 598129ba616SKumar Gala #define CONFIG_HAS_ETH3 599129ba616SKumar Gala #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 600129ba616SKumar Gala #endif 601129ba616SKumar Gala 602129ba616SKumar Gala #define CONFIG_IPADDR 192.168.1.254 603129ba616SKumar Gala 604129ba616SKumar Gala #define CONFIG_HOSTNAME unknown 605129ba616SKumar Gala #define CONFIG_ROOTPATH /opt/nfsroot 606129ba616SKumar Gala #define CONFIG_BOOTFILE uImage 607129ba616SKumar Gala #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 608129ba616SKumar Gala 609129ba616SKumar Gala #define CONFIG_SERVERIP 192.168.1.1 610129ba616SKumar Gala #define CONFIG_GATEWAYIP 192.168.1.1 611129ba616SKumar Gala #define CONFIG_NETMASK 255.255.255.0 612129ba616SKumar Gala 613129ba616SKumar Gala /* default location for tftp and bootm */ 614129ba616SKumar Gala #define CONFIG_LOADADDR 1000000 615129ba616SKumar Gala 616129ba616SKumar Gala #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 617129ba616SKumar Gala #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 618129ba616SKumar Gala 619129ba616SKumar Gala #define CONFIG_BAUDRATE 115200 620129ba616SKumar Gala 621129ba616SKumar Gala #define CONFIG_EXTRA_ENV_SETTINGS \ 6224ca06607SHaiying Wang "memctl_intlv_ctl=2\0" \ 623129ba616SKumar Gala "netdev=eth0\0" \ 624129ba616SKumar Gala "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 625129ba616SKumar Gala "tftpflash=tftpboot $loadaddr $uboot; " \ 626129ba616SKumar Gala "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 627129ba616SKumar Gala "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 628129ba616SKumar Gala "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 629129ba616SKumar Gala "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 630129ba616SKumar Gala "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 631129ba616SKumar Gala "consoledev=ttyS0\0" \ 632129ba616SKumar Gala "ramdiskaddr=2000000\0" \ 633129ba616SKumar Gala "ramdiskfile=8572ds/ramdisk.uboot\0" \ 634129ba616SKumar Gala "fdtaddr=c00000\0" \ 635129ba616SKumar Gala "fdtfile=8572ds/mpc8572ds.dtb\0" \ 636129ba616SKumar Gala "bdev=sda3\0" 637129ba616SKumar Gala 638129ba616SKumar Gala #define CONFIG_HDBOOT \ 639129ba616SKumar Gala "setenv bootargs root=/dev/$bdev rw " \ 640129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 641129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 642129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 643129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 644129ba616SKumar Gala 645129ba616SKumar Gala #define CONFIG_NFSBOOTCOMMAND \ 646129ba616SKumar Gala "setenv bootargs root=/dev/nfs rw " \ 647129ba616SKumar Gala "nfsroot=$serverip:$rootpath " \ 648129ba616SKumar Gala "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 649129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 650129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 651129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 652129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 653129ba616SKumar Gala 654129ba616SKumar Gala #define CONFIG_RAMBOOTCOMMAND \ 655129ba616SKumar Gala "setenv bootargs root=/dev/ram rw " \ 656129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 657129ba616SKumar Gala "tftp $ramdiskaddr $ramdiskfile;" \ 658129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 659129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 660129ba616SKumar Gala "bootm $loadaddr $ramdiskaddr $fdtaddr" 661129ba616SKumar Gala 662129ba616SKumar Gala #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 663129ba616SKumar Gala 664129ba616SKumar Gala #endif /* __CONFIG_H */ 665