1129ba616SKumar Gala /* 2129ba616SKumar Gala * Copyright 2007-2008 Freescale Semiconductor, Inc. 3129ba616SKumar Gala * 4129ba616SKumar Gala * See file CREDITS for list of people who contributed to this 5129ba616SKumar Gala * project. 6129ba616SKumar Gala * 7129ba616SKumar Gala * This program is free software; you can redistribute it and/or 8129ba616SKumar Gala * modify it under the terms of the GNU General Public License as 9129ba616SKumar Gala * published by the Free Software Foundation; either version 2 of 10129ba616SKumar Gala * the License, or (at your option) any later version. 11129ba616SKumar Gala * 12129ba616SKumar Gala * This program is distributed in the hope that it will be useful, 13129ba616SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 14129ba616SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15129ba616SKumar Gala * GNU General Public License for more details. 16129ba616SKumar Gala * 17129ba616SKumar Gala * You should have received a copy of the GNU General Public License 18129ba616SKumar Gala * along with this program; if not, write to the Free Software 19129ba616SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20129ba616SKumar Gala * MA 02111-1307 USA 21129ba616SKumar Gala */ 22129ba616SKumar Gala 23129ba616SKumar Gala /* 24129ba616SKumar Gala * mpc8572ds board configuration file 25129ba616SKumar Gala * 26129ba616SKumar Gala */ 27129ba616SKumar Gala #ifndef __CONFIG_H 28129ba616SKumar Gala #define __CONFIG_H 29129ba616SKumar Gala 30129ba616SKumar Gala /* High Level Configuration Options */ 31129ba616SKumar Gala #define CONFIG_BOOKE 1 /* BOOKE */ 32129ba616SKumar Gala #define CONFIG_E500 1 /* BOOKE e500 family */ 33129ba616SKumar Gala #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34129ba616SKumar Gala #define CONFIG_MPC8572 1 35129ba616SKumar Gala #define CONFIG_MPC8572DS 1 36129ba616SKumar Gala #define CONFIG_MP 1 /* support multiple processors */ 37129ba616SKumar Gala #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 38129ba616SKumar Gala 39c51fc5d5SKumar Gala #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 40129ba616SKumar Gala #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 41129ba616SKumar Gala #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 42129ba616SKumar Gala #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 43129ba616SKumar Gala #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 44129ba616SKumar Gala #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 45129ba616SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 460151cbacSKumar Gala #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 47129ba616SKumar Gala 48129ba616SKumar Gala #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 49129ba616SKumar Gala 50129ba616SKumar Gala #define CONFIG_TSEC_ENET /* tsec ethernet support */ 51129ba616SKumar Gala #define CONFIG_ENV_OVERWRITE 52129ba616SKumar Gala 53129ba616SKumar Gala /* 54129ba616SKumar Gala * When initializing flash, if we cannot find the manufacturer ID, 55129ba616SKumar Gala * assume this is the AMD flash associated with the CDS board. 56129ba616SKumar Gala * This allows booting from a promjet. 57129ba616SKumar Gala */ 58129ba616SKumar Gala #define CONFIG_ASSUME_AMD_FLASH 59129ba616SKumar Gala 60129ba616SKumar Gala #ifndef __ASSEMBLY__ 61129ba616SKumar Gala extern unsigned long get_board_sys_clk(unsigned long dummy); 62129ba616SKumar Gala extern unsigned long get_board_ddr_clk(unsigned long dummy); 63129ba616SKumar Gala #endif 64129ba616SKumar Gala #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 65129ba616SKumar Gala #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 664ca06607SHaiying Wang #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 67129ba616SKumar Gala #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 68129ba616SKumar Gala from ICS307 instead of switches */ 69129ba616SKumar Gala 70129ba616SKumar Gala /* 71129ba616SKumar Gala * These can be toggled for performance analysis, otherwise use default. 72129ba616SKumar Gala */ 73129ba616SKumar Gala #define CONFIG_L2_CACHE /* toggle L2 cache */ 74129ba616SKumar Gala #define CONFIG_BTB /* toggle branch predition */ 75129ba616SKumar Gala 76129ba616SKumar Gala #define CONFIG_ENABLE_36BIT_PHYS 1 77129ba616SKumar Gala 7818af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 7918af1c5fSKumar Gala #define CONFIG_ADDR_MAP 1 8018af1c5fSKumar Gala #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 8118af1c5fSKumar Gala #endif 8218af1c5fSKumar Gala 836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x7fffffff 85129ba616SKumar Gala #define CONFIG_PANIC_HANG /* do not reset board on panic */ 86129ba616SKumar Gala 87129ba616SKumar Gala /* 88129ba616SKumar Gala * Base addresses -- Note these are effective addresses where the 89129ba616SKumar Gala * actual resources get mapped (not physical addresses) 90129ba616SKumar Gala */ 916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 9318af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 9418af1c5fSKumar Gala #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 9518af1c5fSKumar Gala #else 966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 9718af1c5fSKumar Gala #endif 986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 99129ba616SKumar Gala 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 1026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 103129ba616SKumar Gala 104129ba616SKumar Gala /* DDR Setup */ 105b5f65dfaSHaiying Wang #define CONFIG_SYS_DDR_TLB_START 9 106f8523cb0SKumar Gala #define CONFIG_VERY_BIG_RAM 107129ba616SKumar Gala #define CONFIG_FSL_DDR2 108129ba616SKumar Gala #undef CONFIG_FSL_DDR_INTERACTIVE 109129ba616SKumar Gala #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 110129ba616SKumar Gala #define CONFIG_DDR_SPD 111129ba616SKumar Gala #undef CONFIG_DDR_DLL 112129ba616SKumar Gala 1139b0ad1b1SDave Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 114129ba616SKumar Gala #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 115129ba616SKumar Gala 1166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 1176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 118129ba616SKumar Gala 119129ba616SKumar Gala #define CONFIG_NUM_DDR_CONTROLLERS 2 120129ba616SKumar Gala #define CONFIG_DIMM_SLOTS_PER_CTLR 1 121129ba616SKumar Gala #define CONFIG_CHIP_SELECTS_PER_CTRL 2 122129ba616SKumar Gala 123129ba616SKumar Gala /* I2C addresses of SPD EEPROMs */ 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 125129ba616SKumar Gala #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 126129ba616SKumar Gala #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 127129ba616SKumar Gala 128129ba616SKumar Gala /* These are used when DDR doesn't use SPD. */ 129dc889e86SDave Liu #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 1306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 131dc889e86SDave Liu #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 132dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_3 0x00020000 1336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 0x00260802 134dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 135dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 136dc889e86SDave Liu #define CONFIG_SYS_DDR_MODE_1 0x00440462 1376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x00000000 138dc889e86SDave Liu #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 1396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 140dc889e86SDave Liu #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 1416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 143dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 144dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL2 0x24400000 145129ba616SKumar Gala 1466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 1476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 1486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SBE 0x00010000 149129ba616SKumar Gala 150129ba616SKumar Gala /* 151129ba616SKumar Gala * Make sure required options are set 152129ba616SKumar Gala */ 153129ba616SKumar Gala #ifndef CONFIG_SPD_EEPROM 154129ba616SKumar Gala #error ("CONFIG_SPD_EEPROM is required") 155129ba616SKumar Gala #endif 156129ba616SKumar Gala 157129ba616SKumar Gala #undef CONFIG_CLOCKS_IN_MHZ 158129ba616SKumar Gala 159129ba616SKumar Gala /* 160129ba616SKumar Gala * Memory map 161129ba616SKumar Gala * 162129ba616SKumar Gala * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 163129ba616SKumar Gala * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 164129ba616SKumar Gala * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 165129ba616SKumar Gala * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 166129ba616SKumar Gala * 167129ba616SKumar Gala * Localbus cacheable (TBD) 168129ba616SKumar Gala * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 169129ba616SKumar Gala * 170129ba616SKumar Gala * Localbus non-cacheable 171129ba616SKumar Gala * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 172129ba616SKumar Gala * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 173c013b749SHaiying Wang * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 174129ba616SKumar Gala * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 175129ba616SKumar Gala * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 176129ba616SKumar Gala * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 177129ba616SKumar Gala */ 178129ba616SKumar Gala 179129ba616SKumar Gala /* 180129ba616SKumar Gala * Local Bus Definitions 181129ba616SKumar Gala */ 1826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 18318af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 18418af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 18518af1c5fSKumar Gala #else 186c953ddfdSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 18718af1c5fSKumar Gala #endif 188129ba616SKumar Gala 189c953ddfdSKumar Gala #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 191129ba616SKumar Gala 192c953ddfdSKumar Gala #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 1936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 194129ba616SKumar Gala 19518af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 1966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 197129ba616SKumar Gala #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 198129ba616SKumar Gala 1996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 2016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CHECKSUM 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 204129ba616SKumar Gala 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 206129ba616SKumar Gala 207129ba616SKumar Gala #define CONFIG_FLASH_CFI_DRIVER 2086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 2096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 2106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 211129ba616SKumar Gala 212129ba616SKumar Gala #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 213129ba616SKumar Gala 214129ba616SKumar Gala #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 215129ba616SKumar Gala #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 21618af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 21718af1c5fSKumar Gala #define PIXIS_BASE_PHYS 0xfffdf0000ull 21818af1c5fSKumar Gala #else 21952b565f5SKumar Gala #define PIXIS_BASE_PHYS PIXIS_BASE 22018af1c5fSKumar Gala #endif 221129ba616SKumar Gala 22252b565f5SKumar Gala #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 224129ba616SKumar Gala 225129ba616SKumar Gala #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 226129ba616SKumar Gala #define PIXIS_VER 0x1 /* Board version at offset 1 */ 227129ba616SKumar Gala #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 228129ba616SKumar Gala #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 229129ba616SKumar Gala #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 230129ba616SKumar Gala #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 231129ba616SKumar Gala #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 232129ba616SKumar Gala #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 233129ba616SKumar Gala #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 234129ba616SKumar Gala #define PIXIS_VCTL 0x10 /* VELA Control Register */ 235129ba616SKumar Gala #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 236129ba616SKumar Gala #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 237129ba616SKumar Gala #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 238129ba616SKumar Gala #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 239129ba616SKumar Gala #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 240129ba616SKumar Gala #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 241129ba616SKumar Gala #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 242129ba616SKumar Gala #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 243129ba616SKumar Gala #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 244129ba616SKumar Gala #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 245129ba616SKumar Gala #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 246129ba616SKumar Gala #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 247129ba616SKumar Gala #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 248129ba616SKumar Gala #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 249129ba616SKumar Gala #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 250129ba616SKumar Gala #define PIXIS_LED 0x25 /* LED Register */ 251129ba616SKumar Gala 252129ba616SKumar Gala /* old pixis referenced names */ 253129ba616SKumar Gala #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 254129ba616SKumar Gala #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 2556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 2567e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC1SER 0x8 2577e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC2SER 0x4 2587e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC3SER 0x2 2597e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC4SER 0x1 2607e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC1SER 0x20 2617e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC2SER 0x20 2627e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC3SER 0x20 2637e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC4SER 0x20 2647e183cadSLiu Yu #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 2657e183cadSLiu Yu | PIXIS_VSPEED2_TSEC2SER \ 2667e183cadSLiu Yu | PIXIS_VSPEED2_TSEC3SER \ 2677e183cadSLiu Yu | PIXIS_VSPEED2_TSEC4SER) 2687e183cadSLiu Yu #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 2697e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC2SER \ 2707e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC3SER \ 2717e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC4SER) 272129ba616SKumar Gala 2736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 2746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 2756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 276129ba616SKumar Gala 2776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 2786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 2796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 280129ba616SKumar Gala 2816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 2826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 283129ba616SKumar Gala 284c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE 0xffa00000 28518af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 28618af1c5fSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 28718af1c5fSKumar Gala #else 288c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 28918af1c5fSKumar Gala #endif 290c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 291c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x40000, \ 292c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x80000,\ 293c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0xC0000} 294c013b749SHaiying Wang #define CONFIG_SYS_MAX_NAND_DEVICE 4 295c013b749SHaiying Wang #define CONFIG_MTD_NAND_VERIFY_WRITE 296c013b749SHaiying Wang #define CONFIG_CMD_NAND 1 297c013b749SHaiying Wang #define CONFIG_NAND_FSL_ELBC 1 298c013b749SHaiying Wang #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 299c013b749SHaiying Wang 300c013b749SHaiying Wang /* NAND flash config */ 30172a9414aSKumar Gala #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 302c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 303c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 304c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 305c013b749SHaiying Wang | BR_V) /* valid */ 306c013b749SHaiying Wang #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 307c013b749SHaiying Wang | OR_FCM_PGS /* Large Page*/ \ 308c013b749SHaiying Wang | OR_FCM_CSCT \ 309c013b749SHaiying Wang | OR_FCM_CST \ 310c013b749SHaiying Wang | OR_FCM_CHT \ 311c013b749SHaiying Wang | OR_FCM_SCY_1 \ 312c013b749SHaiying Wang | OR_FCM_TRLX \ 313c013b749SHaiying Wang | OR_FCM_EHTR) 314c013b749SHaiying Wang 315c013b749SHaiying Wang #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 316c013b749SHaiying Wang #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 317c013b749SHaiying Wang 31872a9414aSKumar Gala #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 319c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 320c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 321c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 322c013b749SHaiying Wang | BR_V) /* valid */ 323c013b749SHaiying Wang #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 32472a9414aSKumar Gala #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 325c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 326c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 327c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 328c013b749SHaiying Wang | BR_V) /* valid */ 329c013b749SHaiying Wang #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 330c013b749SHaiying Wang 33172a9414aSKumar Gala #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 332c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 333c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 334c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 335c013b749SHaiying Wang | BR_V) /* valid */ 336c013b749SHaiying Wang #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 337c013b749SHaiying Wang 338c013b749SHaiying Wang 339129ba616SKumar Gala /* Serial Port - controlled on board with jumper J8 340129ba616SKumar Gala * open - index 2 341129ba616SKumar Gala * shorted - index 1 342129ba616SKumar Gala */ 343129ba616SKumar Gala #define CONFIG_CONS_INDEX 1 344129ba616SKumar Gala #undef CONFIG_SERIAL_SOFTWARE_FIFO 3456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 349129ba616SKumar Gala 3506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 351129ba616SKumar Gala {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 352129ba616SKumar Gala 3536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 3546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 355129ba616SKumar Gala 356129ba616SKumar Gala /* Use the HUSH parser */ 3576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 3586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_HUSH_PARSER 3596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 360129ba616SKumar Gala #endif 361129ba616SKumar Gala 362129ba616SKumar Gala /* 363129ba616SKumar Gala * Pass open firmware flat tree 364129ba616SKumar Gala */ 365129ba616SKumar Gala #define CONFIG_OF_LIBFDT 1 366129ba616SKumar Gala #define CONFIG_OF_BOARD_SETUP 1 367129ba616SKumar Gala #define CONFIG_OF_STDOUT_VIA_ALIAS 1 368129ba616SKumar Gala 3696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_64BIT_VSPRINTF 1 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_64BIT_STRTOUL 1 371129ba616SKumar Gala 372129ba616SKumar Gala /* new uImage format support */ 373129ba616SKumar Gala #define CONFIG_FIT 1 374129ba616SKumar Gala #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 375129ba616SKumar Gala 376129ba616SKumar Gala /* I2C */ 377129ba616SKumar Gala #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 378129ba616SKumar Gala #define CONFIG_HARD_I2C /* I2C with hardware support */ 379129ba616SKumar Gala #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 3801f3ba317SHaiying Wang #define CONFIG_I2C_MULTI_BUS 3811f3ba317SHaiying Wang #define CONFIG_I2C_CMD_TREE 3826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 3836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 3846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 3856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 3866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 3876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 388129ba616SKumar Gala 389129ba616SKumar Gala /* 390445a7b38SHaiying Wang * I2C2 EEPROM 391445a7b38SHaiying Wang */ 392445a7b38SHaiying Wang #define CONFIG_ID_EEPROM 393445a7b38SHaiying Wang #ifdef CONFIG_ID_EEPROM 3946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_NXID 395445a7b38SHaiying Wang #endif 3966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 3976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 3986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_EEPROM_BUS_NUM 1 399445a7b38SHaiying Wang 400445a7b38SHaiying Wang /* 401129ba616SKumar Gala * General PCI 402129ba616SKumar Gala * Memory space is mapped 1-1, but I/O space must start from 0. 403129ba616SKumar Gala */ 404129ba616SKumar Gala 405129ba616SKumar Gala /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 4065af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 40718af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 408*ad97dce1SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 40918af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 41018af1c5fSKumar Gala #else 411*ad97dce1SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 4125af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 41318af1c5fSKumar Gala #endif 4146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 415aca5f018SKumar Gala #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 4165f91ef6aSKumar Gala #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 41718af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 41818af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 41918af1c5fSKumar Gala #else 4206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 42118af1c5fSKumar Gala #endif 4226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 423129ba616SKumar Gala 424129ba616SKumar Gala /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 4255af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 42618af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 427*ad97dce1SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 42818af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 42918af1c5fSKumar Gala #else 430*ad97dce1SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 4315af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 43218af1c5fSKumar Gala #endif 4336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 434aca5f018SKumar Gala #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 4355f91ef6aSKumar Gala #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 43618af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 43718af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 43818af1c5fSKumar Gala #else 4396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 44018af1c5fSKumar Gala #endif 4416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 442129ba616SKumar Gala 443129ba616SKumar Gala /* controller 1, Slot 1, tgtid 1, Base address a000 */ 4445af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 44518af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 446*ad97dce1SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 44718af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 44818af1c5fSKumar Gala #else 449*ad97dce1SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 4505af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 45118af1c5fSKumar Gala #endif 4526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 453aca5f018SKumar Gala #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 4545f91ef6aSKumar Gala #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 45518af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 45618af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 45718af1c5fSKumar Gala #else 4586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 45918af1c5fSKumar Gala #endif 4606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 461129ba616SKumar Gala 462129ba616SKumar Gala #if defined(CONFIG_PCI) 463129ba616SKumar Gala 464129ba616SKumar Gala /*PCIE video card used*/ 465aca5f018SKumar Gala #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 466129ba616SKumar Gala 467129ba616SKumar Gala /* video */ 468129ba616SKumar Gala #define CONFIG_VIDEO 469129ba616SKumar Gala 470129ba616SKumar Gala #if defined(CONFIG_VIDEO) 471129ba616SKumar Gala #define CONFIG_BIOSEMU 472129ba616SKumar Gala #define CONFIG_CFB_CONSOLE 473129ba616SKumar Gala #define CONFIG_VIDEO_SW_CURSOR 474129ba616SKumar Gala #define CONFIG_VGA_AS_SINGLE_DEVICE 475129ba616SKumar Gala #define CONFIG_ATI_RADEON_FB 476129ba616SKumar Gala #define CONFIG_VIDEO_LOGO 477129ba616SKumar Gala /*#define CONFIG_CONSOLE_CURSOR*/ 4786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 479129ba616SKumar Gala #endif 480129ba616SKumar Gala 481129ba616SKumar Gala #define CONFIG_NET_MULTI 482129ba616SKumar Gala #define CONFIG_PCI_PNP /* do pci plug-and-play */ 483129ba616SKumar Gala 484129ba616SKumar Gala #undef CONFIG_EEPRO100 485129ba616SKumar Gala #undef CONFIG_TULIP 486129ba616SKumar Gala #undef CONFIG_RTL8139 487129ba616SKumar Gala 488129ba616SKumar Gala #ifdef CONFIG_RTL8139 489129ba616SKumar Gala /* This macro is used by RTL8139 but not defined in PPC architecture */ 490129ba616SKumar Gala #define KSEG1ADDR(x) (x) 491129ba616SKumar Gala #define _IO_BASE 0x00000000 492129ba616SKumar Gala #endif 493129ba616SKumar Gala 494129ba616SKumar Gala #ifndef CONFIG_PCI_PNP 4955f91ef6aSKumar Gala #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 4965f91ef6aSKumar Gala #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 497129ba616SKumar Gala #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 498129ba616SKumar Gala #endif 499129ba616SKumar Gala 500129ba616SKumar Gala #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 501129ba616SKumar Gala #define CONFIG_DOS_PARTITION 502129ba616SKumar Gala #define CONFIG_SCSI_AHCI 503129ba616SKumar Gala 504129ba616SKumar Gala #ifdef CONFIG_SCSI_AHCI 505129ba616SKumar Gala #define CONFIG_SATA_ULI5288 5066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 5076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_LUN 1 5086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 5096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 510129ba616SKumar Gala #endif /* SCSI */ 511129ba616SKumar Gala 512129ba616SKumar Gala #endif /* CONFIG_PCI */ 513129ba616SKumar Gala 514129ba616SKumar Gala 515129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 516129ba616SKumar Gala 517129ba616SKumar Gala #ifndef CONFIG_NET_MULTI 518129ba616SKumar Gala #define CONFIG_NET_MULTI 1 519129ba616SKumar Gala #endif 520129ba616SKumar Gala 521129ba616SKumar Gala #define CONFIG_MII 1 /* MII PHY management */ 522129ba616SKumar Gala #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 523129ba616SKumar Gala #define CONFIG_TSEC1 1 524129ba616SKumar Gala #define CONFIG_TSEC1_NAME "eTSEC1" 525129ba616SKumar Gala #define CONFIG_TSEC2 1 526129ba616SKumar Gala #define CONFIG_TSEC2_NAME "eTSEC2" 527129ba616SKumar Gala #define CONFIG_TSEC3 1 528129ba616SKumar Gala #define CONFIG_TSEC3_NAME "eTSEC3" 529129ba616SKumar Gala #define CONFIG_TSEC4 1 530129ba616SKumar Gala #define CONFIG_TSEC4_NAME "eTSEC4" 531129ba616SKumar Gala 5327e183cadSLiu Yu #define CONFIG_PIXIS_SGMII_CMD 5337e183cadSLiu Yu #define CONFIG_FSL_SGMII_RISER 1 5347e183cadSLiu Yu #define SGMII_RISER_PHY_OFFSET 0x1c 5357e183cadSLiu Yu 5367e183cadSLiu Yu #ifdef CONFIG_FSL_SGMII_RISER 5377e183cadSLiu Yu #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 5387e183cadSLiu Yu #endif 5397e183cadSLiu Yu 540129ba616SKumar Gala #define TSEC1_PHY_ADDR 0 541129ba616SKumar Gala #define TSEC2_PHY_ADDR 1 542129ba616SKumar Gala #define TSEC3_PHY_ADDR 2 543129ba616SKumar Gala #define TSEC4_PHY_ADDR 3 544129ba616SKumar Gala 545129ba616SKumar Gala #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 546129ba616SKumar Gala #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 547129ba616SKumar Gala #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 548129ba616SKumar Gala #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 549129ba616SKumar Gala 550129ba616SKumar Gala #define TSEC1_PHYIDX 0 551129ba616SKumar Gala #define TSEC2_PHYIDX 0 552129ba616SKumar Gala #define TSEC3_PHYIDX 0 553129ba616SKumar Gala #define TSEC4_PHYIDX 0 554129ba616SKumar Gala 555129ba616SKumar Gala #define CONFIG_ETHPRIME "eTSEC1" 556129ba616SKumar Gala 557129ba616SKumar Gala #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 558129ba616SKumar Gala #endif /* CONFIG_TSEC_ENET */ 559129ba616SKumar Gala 560129ba616SKumar Gala /* 561129ba616SKumar Gala * Environment 562129ba616SKumar Gala */ 5635a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 5646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 5650e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR 0xfff80000 566129ba616SKumar Gala #else 5676fc110bdSHaiying Wang #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 568129ba616SKumar Gala #endif 5690e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 5700e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 571129ba616SKumar Gala 572129ba616SKumar Gala #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 5736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 574129ba616SKumar Gala 575129ba616SKumar Gala /* 576129ba616SKumar Gala * Command line configuration. 577129ba616SKumar Gala */ 578129ba616SKumar Gala #include <config_cmd_default.h> 579129ba616SKumar Gala 580129ba616SKumar Gala #define CONFIG_CMD_IRQ 581129ba616SKumar Gala #define CONFIG_CMD_PING 582129ba616SKumar Gala #define CONFIG_CMD_I2C 583129ba616SKumar Gala #define CONFIG_CMD_MII 584129ba616SKumar Gala #define CONFIG_CMD_ELF 5851c9aa76bSKumar Gala #define CONFIG_CMD_IRQ 5861c9aa76bSKumar Gala #define CONFIG_CMD_SETEXPR 587129ba616SKumar Gala 588129ba616SKumar Gala #if defined(CONFIG_PCI) 589129ba616SKumar Gala #define CONFIG_CMD_PCI 590129ba616SKumar Gala #define CONFIG_CMD_BEDBUG 591129ba616SKumar Gala #define CONFIG_CMD_NET 592129ba616SKumar Gala #define CONFIG_CMD_SCSI 593129ba616SKumar Gala #define CONFIG_CMD_EXT2 594129ba616SKumar Gala #endif 595129ba616SKumar Gala 596129ba616SKumar Gala #undef CONFIG_WATCHDOG /* watchdog disabled */ 597129ba616SKumar Gala 598129ba616SKumar Gala /* 599129ba616SKumar Gala * Miscellaneous configurable options 600129ba616SKumar Gala */ 6016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 602129ba616SKumar Gala #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 6036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 6046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 605129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 6066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 607129ba616SKumar Gala #else 6086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 609129ba616SKumar Gala #endif 6106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 6116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 6126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 6136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 614129ba616SKumar Gala 615129ba616SKumar Gala /* 616129ba616SKumar Gala * For booting Linux, the board info and command line data 617129ba616SKumar Gala * have to be in the first 8 MB of memory, since this is 618129ba616SKumar Gala * the maximum mapped by the Linux kernel during initialization. 619129ba616SKumar Gala */ 6206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 621129ba616SKumar Gala 622129ba616SKumar Gala /* 623129ba616SKumar Gala * Internal Definitions 624129ba616SKumar Gala * 625129ba616SKumar Gala * Boot Flags 626129ba616SKumar Gala */ 627129ba616SKumar Gala #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 628129ba616SKumar Gala #define BOOTFLAG_WARM 0x02 /* Software reboot */ 629129ba616SKumar Gala 630129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 631129ba616SKumar Gala #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 632129ba616SKumar Gala #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 633129ba616SKumar Gala #endif 634129ba616SKumar Gala 635129ba616SKumar Gala /* 636129ba616SKumar Gala * Environment Configuration 637129ba616SKumar Gala */ 638129ba616SKumar Gala 639129ba616SKumar Gala /* The mac addresses for all ethernet interface */ 640129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 641129ba616SKumar Gala #define CONFIG_HAS_ETH0 642129ba616SKumar Gala #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 643129ba616SKumar Gala #define CONFIG_HAS_ETH1 644129ba616SKumar Gala #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 645129ba616SKumar Gala #define CONFIG_HAS_ETH2 646129ba616SKumar Gala #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 647129ba616SKumar Gala #define CONFIG_HAS_ETH3 648129ba616SKumar Gala #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 649129ba616SKumar Gala #endif 650129ba616SKumar Gala 651129ba616SKumar Gala #define CONFIG_IPADDR 192.168.1.254 652129ba616SKumar Gala 653129ba616SKumar Gala #define CONFIG_HOSTNAME unknown 654129ba616SKumar Gala #define CONFIG_ROOTPATH /opt/nfsroot 655129ba616SKumar Gala #define CONFIG_BOOTFILE uImage 656129ba616SKumar Gala #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 657129ba616SKumar Gala 658129ba616SKumar Gala #define CONFIG_SERVERIP 192.168.1.1 659129ba616SKumar Gala #define CONFIG_GATEWAYIP 192.168.1.1 660129ba616SKumar Gala #define CONFIG_NETMASK 255.255.255.0 661129ba616SKumar Gala 662129ba616SKumar Gala /* default location for tftp and bootm */ 663129ba616SKumar Gala #define CONFIG_LOADADDR 1000000 664129ba616SKumar Gala 665129ba616SKumar Gala #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 666129ba616SKumar Gala #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 667129ba616SKumar Gala 668129ba616SKumar Gala #define CONFIG_BAUDRATE 115200 669129ba616SKumar Gala 670129ba616SKumar Gala #define CONFIG_EXTRA_ENV_SETTINGS \ 6714ca06607SHaiying Wang "memctl_intlv_ctl=2\0" \ 672129ba616SKumar Gala "netdev=eth0\0" \ 673129ba616SKumar Gala "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 674129ba616SKumar Gala "tftpflash=tftpboot $loadaddr $uboot; " \ 675129ba616SKumar Gala "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 676129ba616SKumar Gala "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 677129ba616SKumar Gala "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 678129ba616SKumar Gala "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 679129ba616SKumar Gala "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 680129ba616SKumar Gala "consoledev=ttyS0\0" \ 681129ba616SKumar Gala "ramdiskaddr=2000000\0" \ 682129ba616SKumar Gala "ramdiskfile=8572ds/ramdisk.uboot\0" \ 683129ba616SKumar Gala "fdtaddr=c00000\0" \ 684129ba616SKumar Gala "fdtfile=8572ds/mpc8572ds.dtb\0" \ 685129ba616SKumar Gala "bdev=sda3\0" 686129ba616SKumar Gala 687129ba616SKumar Gala #define CONFIG_HDBOOT \ 688129ba616SKumar Gala "setenv bootargs root=/dev/$bdev rw " \ 689129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 690129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 691129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 692129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 693129ba616SKumar Gala 694129ba616SKumar Gala #define CONFIG_NFSBOOTCOMMAND \ 695129ba616SKumar Gala "setenv bootargs root=/dev/nfs rw " \ 696129ba616SKumar Gala "nfsroot=$serverip:$rootpath " \ 697129ba616SKumar Gala "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 698129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 699129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 700129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 701129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 702129ba616SKumar Gala 703129ba616SKumar Gala #define CONFIG_RAMBOOTCOMMAND \ 704129ba616SKumar Gala "setenv bootargs root=/dev/ram rw " \ 705129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 706129ba616SKumar Gala "tftp $ramdiskaddr $ramdiskfile;" \ 707129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 708129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 709129ba616SKumar Gala "bootm $loadaddr $ramdiskaddr $fdtaddr" 710129ba616SKumar Gala 711129ba616SKumar Gala #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 712129ba616SKumar Gala 713129ba616SKumar Gala #endif /* __CONFIG_H */ 714