1129ba616SKumar Gala /* 27c57f3e8SKumar Gala * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3129ba616SKumar Gala * 4129ba616SKumar Gala * See file CREDITS for list of people who contributed to this 5129ba616SKumar Gala * project. 6129ba616SKumar Gala * 7129ba616SKumar Gala * This program is free software; you can redistribute it and/or 8129ba616SKumar Gala * modify it under the terms of the GNU General Public License as 9129ba616SKumar Gala * published by the Free Software Foundation; either version 2 of 10129ba616SKumar Gala * the License, or (at your option) any later version. 11129ba616SKumar Gala * 12129ba616SKumar Gala * This program is distributed in the hope that it will be useful, 13129ba616SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 14129ba616SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15129ba616SKumar Gala * GNU General Public License for more details. 16129ba616SKumar Gala * 17129ba616SKumar Gala * You should have received a copy of the GNU General Public License 18129ba616SKumar Gala * along with this program; if not, write to the Free Software 19129ba616SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20129ba616SKumar Gala * MA 02111-1307 USA 21129ba616SKumar Gala */ 22129ba616SKumar Gala 23129ba616SKumar Gala /* 24129ba616SKumar Gala * mpc8572ds board configuration file 25129ba616SKumar Gala * 26129ba616SKumar Gala */ 27129ba616SKumar Gala #ifndef __CONFIG_H 28129ba616SKumar Gala #define __CONFIG_H 29129ba616SKumar Gala 30509c4c4cSKumar Gala #include "../board/freescale/common/ics307_clk.h" 31509c4c4cSKumar Gala 32d24f2d32SWolfgang Denk #ifdef CONFIG_36BIT 33f9edcc10SKumar Gala #define CONFIG_PHYS_64BIT 34f9edcc10SKumar Gala #endif 35f9edcc10SKumar Gala 36cb14e93bSKumar Gala #ifdef CONFIG_NAND 37cb14e93bSKumar Gala #define CONFIG_NAND_U_BOOT 38cb14e93bSKumar Gala #define CONFIG_RAMBOOT_NAND 39cb14e93bSKumar Gala #ifdef CONFIG_NAND_SPL 40cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 41cb14e93bSKumar Gala #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 42cb14e93bSKumar Gala #else 4300203c64SKumar Gala #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds 44cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE 0xf8f82000 45cb14e93bSKumar Gala #endif /* CONFIG_NAND_SPL */ 46cb14e93bSKumar Gala #endif 47cb14e93bSKumar Gala 48cb14e93bSKumar Gala #ifndef CONFIG_SYS_TEXT_BASE 49cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE 0xeff80000 50cb14e93bSKumar Gala #endif 51cb14e93bSKumar Gala 527a577fdaSKumar Gala #ifndef CONFIG_RESET_VECTOR_ADDRESS 537a577fdaSKumar Gala #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 547a577fdaSKumar Gala #endif 557a577fdaSKumar Gala 56cb14e93bSKumar Gala #ifndef CONFIG_SYS_MONITOR_BASE 57cb14e93bSKumar Gala #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 58cb14e93bSKumar Gala #endif 59cb14e93bSKumar Gala 60129ba616SKumar Gala /* High Level Configuration Options */ 61129ba616SKumar Gala #define CONFIG_BOOKE 1 /* BOOKE */ 62129ba616SKumar Gala #define CONFIG_E500 1 /* BOOKE e500 family */ 63129ba616SKumar Gala #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 64129ba616SKumar Gala #define CONFIG_MPC8572 1 65129ba616SKumar Gala #define CONFIG_MPC8572DS 1 66129ba616SKumar Gala #define CONFIG_MP 1 /* support multiple processors */ 67129ba616SKumar Gala 68c51fc5d5SKumar Gala #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 69129ba616SKumar Gala #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 70129ba616SKumar Gala #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 71129ba616SKumar Gala #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 72129ba616SKumar Gala #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 73129ba616SKumar Gala #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 74129ba616SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 750151cbacSKumar Gala #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 76129ba616SKumar Gala 77129ba616SKumar Gala #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 78129ba616SKumar Gala 79129ba616SKumar Gala #define CONFIG_TSEC_ENET /* tsec ethernet support */ 80129ba616SKumar Gala #define CONFIG_ENV_OVERWRITE 81129ba616SKumar Gala 82509c4c4cSKumar Gala #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 83509c4c4cSKumar Gala #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 844ca06607SHaiying Wang #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 85129ba616SKumar Gala 86129ba616SKumar Gala /* 87129ba616SKumar Gala * These can be toggled for performance analysis, otherwise use default. 88129ba616SKumar Gala */ 89129ba616SKumar Gala #define CONFIG_L2_CACHE /* toggle L2 cache */ 90129ba616SKumar Gala #define CONFIG_BTB /* toggle branch predition */ 91129ba616SKumar Gala 92129ba616SKumar Gala #define CONFIG_ENABLE_36BIT_PHYS 1 93129ba616SKumar Gala 9418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 9518af1c5fSKumar Gala #define CONFIG_ADDR_MAP 1 9618af1c5fSKumar Gala #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 9718af1c5fSKumar Gala #endif 9818af1c5fSKumar Gala 996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x7fffffff 101129ba616SKumar Gala #define CONFIG_PANIC_HANG /* do not reset board on panic */ 102129ba616SKumar Gala 103129ba616SKumar Gala /* 104cb14e93bSKumar Gala * Config the L2 Cache as L2 SRAM 105cb14e93bSKumar Gala */ 106cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 107cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 108cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 109cb14e93bSKumar Gala #else 110cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 111cb14e93bSKumar Gala #endif 112cb14e93bSKumar Gala #define CONFIG_SYS_L2_SIZE (512 << 10) 113cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 114cb14e93bSKumar Gala 115cb14e93bSKumar Gala /* 116129ba616SKumar Gala * Base addresses -- Note these are effective addresses where the 117129ba616SKumar Gala * actual resources get mapped (not physical addresses) 118129ba616SKumar Gala */ 1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 12018af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 12118af1c5fSKumar Gala #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 12218af1c5fSKumar Gala #else 1236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 12418af1c5fSKumar Gala #endif 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 126129ba616SKumar Gala 127cb14e93bSKumar Gala #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) 128cb14e93bSKumar Gala #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR 129cb14e93bSKumar Gala #else 130cb14e93bSKumar Gala #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 131cb14e93bSKumar Gala #endif 132cb14e93bSKumar Gala 133129ba616SKumar Gala /* DDR Setup */ 134f8523cb0SKumar Gala #define CONFIG_VERY_BIG_RAM 135129ba616SKumar Gala #define CONFIG_FSL_DDR2 136129ba616SKumar Gala #undef CONFIG_FSL_DDR_INTERACTIVE 137129ba616SKumar Gala #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 138129ba616SKumar Gala #define CONFIG_DDR_SPD 139129ba616SKumar Gala 140d34897d3SYork Sun #define CONFIG_DDR_ECC 1419b0ad1b1SDave Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 142129ba616SKumar Gala #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 143129ba616SKumar Gala 1446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 1456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 146129ba616SKumar Gala 147129ba616SKumar Gala #define CONFIG_NUM_DDR_CONTROLLERS 2 148129ba616SKumar Gala #define CONFIG_DIMM_SLOTS_PER_CTLR 1 149129ba616SKumar Gala #define CONFIG_CHIP_SELECTS_PER_CTRL 2 150129ba616SKumar Gala 151129ba616SKumar Gala /* I2C addresses of SPD EEPROMs */ 1526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 153129ba616SKumar Gala #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 154129ba616SKumar Gala #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 155129ba616SKumar Gala 156129ba616SKumar Gala /* These are used when DDR doesn't use SPD. */ 157dc889e86SDave Liu #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 1586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 159dc889e86SDave Liu #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 160dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_3 0x00020000 1616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 0x00260802 162dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 163dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 164dc889e86SDave Liu #define CONFIG_SYS_DDR_MODE_1 0x00440462 1656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x00000000 166dc889e86SDave Liu #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 1676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 168dc889e86SDave Liu #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 1696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 1706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 171dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 172dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL2 0x24400000 173129ba616SKumar Gala 1746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 1756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 1766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SBE 0x00010000 177129ba616SKumar Gala 178129ba616SKumar Gala /* 179129ba616SKumar Gala * Make sure required options are set 180129ba616SKumar Gala */ 181129ba616SKumar Gala #ifndef CONFIG_SPD_EEPROM 182129ba616SKumar Gala #error ("CONFIG_SPD_EEPROM is required") 183129ba616SKumar Gala #endif 184129ba616SKumar Gala 185129ba616SKumar Gala #undef CONFIG_CLOCKS_IN_MHZ 186129ba616SKumar Gala 187129ba616SKumar Gala /* 188129ba616SKumar Gala * Memory map 189129ba616SKumar Gala * 190129ba616SKumar Gala * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 191129ba616SKumar Gala * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 192129ba616SKumar Gala * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 193129ba616SKumar Gala * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 194129ba616SKumar Gala * 195129ba616SKumar Gala * Localbus cacheable (TBD) 196129ba616SKumar Gala * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 197129ba616SKumar Gala * 198129ba616SKumar Gala * Localbus non-cacheable 199129ba616SKumar Gala * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 200129ba616SKumar Gala * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 201c013b749SHaiying Wang * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 202129ba616SKumar Gala * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 203129ba616SKumar Gala * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 204129ba616SKumar Gala * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 205129ba616SKumar Gala */ 206129ba616SKumar Gala 207129ba616SKumar Gala /* 208129ba616SKumar Gala * Local Bus Definitions 209129ba616SKumar Gala */ 2106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 21118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 21218af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 21318af1c5fSKumar Gala #else 214c953ddfdSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 21518af1c5fSKumar Gala #endif 216129ba616SKumar Gala 217cb14e93bSKumar Gala 218cb14e93bSKumar Gala #define CONFIG_FLASH_BR_PRELIM \ 219cb14e93bSKumar Gala (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ 220cb14e93bSKumar Gala | BR_PS_16 | BR_V) 221cb14e93bSKumar Gala #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 222129ba616SKumar Gala 223c953ddfdSKumar Gala #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 2246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 225129ba616SKumar Gala 22618af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 2276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 228129ba616SKumar Gala #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 229129ba616SKumar Gala 2306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 2316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 2326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CHECKSUM 2336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 235129ba616SKumar Gala 236cb14e93bSKumar Gala #if defined(CONFIG_RAMBOOT_NAND) 237cb14e93bSKumar Gala #define CONFIG_SYS_RAMBOOT 238cb14e93bSKumar Gala #define CONFIG_SYS_EXTRA_ENV_RELOC 239cb14e93bSKumar Gala #else 240cb14e93bSKumar Gala #undef CONFIG_SYS_RAMBOOT 241cb14e93bSKumar Gala #endif 242129ba616SKumar Gala 243129ba616SKumar Gala #define CONFIG_FLASH_CFI_DRIVER 2446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 2456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 2466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 247129ba616SKumar Gala 248129ba616SKumar Gala #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 249129ba616SKumar Gala 250558710b9SKumar Gala #define CONFIG_HWCONFIG /* enable hwconfig */ 251129ba616SKumar Gala #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 252129ba616SKumar Gala #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 25318af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 25418af1c5fSKumar Gala #define PIXIS_BASE_PHYS 0xfffdf0000ull 25518af1c5fSKumar Gala #else 25652b565f5SKumar Gala #define PIXIS_BASE_PHYS PIXIS_BASE 25718af1c5fSKumar Gala #endif 258129ba616SKumar Gala 25952b565f5SKumar Gala #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 2606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 261129ba616SKumar Gala 262129ba616SKumar Gala #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 263129ba616SKumar Gala #define PIXIS_VER 0x1 /* Board version at offset 1 */ 264129ba616SKumar Gala #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 265129ba616SKumar Gala #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 266129ba616SKumar Gala #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 267129ba616SKumar Gala #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 268129ba616SKumar Gala #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 269129ba616SKumar Gala #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 270129ba616SKumar Gala #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 271129ba616SKumar Gala #define PIXIS_VCTL 0x10 /* VELA Control Register */ 272129ba616SKumar Gala #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 273129ba616SKumar Gala #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 274129ba616SKumar Gala #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 275129ba616SKumar Gala #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 276129ba616SKumar Gala #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 2776bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 2786bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 2796bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 2806bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 2816bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 282129ba616SKumar Gala #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 283129ba616SKumar Gala #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 284129ba616SKumar Gala #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 285129ba616SKumar Gala #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 286129ba616SKumar Gala #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 287129ba616SKumar Gala #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 288129ba616SKumar Gala #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 289129ba616SKumar Gala #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 290129ba616SKumar Gala #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 291129ba616SKumar Gala #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 292129ba616SKumar Gala #define PIXIS_LED 0x25 /* LED Register */ 293129ba616SKumar Gala 294cb14e93bSKumar Gala #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 295cb14e93bSKumar Gala 296129ba616SKumar Gala /* old pixis referenced names */ 297129ba616SKumar Gala #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 298129ba616SKumar Gala #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 2996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 3007e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC1SER 0x8 3017e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC2SER 0x4 3027e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC3SER 0x2 3037e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC4SER 0x1 3047e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC1SER 0x20 3057e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC2SER 0x20 3067e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC3SER 0x20 3077e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC4SER 0x20 3087e183cadSLiu Yu #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 3097e183cadSLiu Yu | PIXIS_VSPEED2_TSEC2SER \ 3107e183cadSLiu Yu | PIXIS_VSPEED2_TSEC3SER \ 3117e183cadSLiu Yu | PIXIS_VSPEED2_TSEC4SER) 3127e183cadSLiu Yu #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 3137e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC2SER \ 3147e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC3SER \ 3157e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC4SER) 316129ba616SKumar Gala 3176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 3186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 319553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 320129ba616SKumar Gala 32125ddd1fbSWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 3226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 323129ba616SKumar Gala 3246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 3256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 326129ba616SKumar Gala 327cb14e93bSKumar Gala #ifndef CONFIG_NAND_SPL 328c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE 0xffa00000 32918af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 33018af1c5fSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 33118af1c5fSKumar Gala #else 332c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 33318af1c5fSKumar Gala #endif 334cb14e93bSKumar Gala #else 335cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE 0xfff00000 336cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 337cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 338cb14e93bSKumar Gala #else 339cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 340cb14e93bSKumar Gala #endif 341cb14e93bSKumar Gala #endif 342cb14e93bSKumar Gala 343c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 344c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x40000, \ 345c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x80000,\ 346c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0xC0000} 347c013b749SHaiying Wang #define CONFIG_SYS_MAX_NAND_DEVICE 4 348c013b749SHaiying Wang #define CONFIG_MTD_NAND_VERIFY_WRITE 349c013b749SHaiying Wang #define CONFIG_CMD_NAND 1 350c013b749SHaiying Wang #define CONFIG_NAND_FSL_ELBC 1 351c013b749SHaiying Wang #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 352c013b749SHaiying Wang 353cb14e93bSKumar Gala /* NAND boot: 4K NAND loader config */ 354cb14e93bSKumar Gala #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 355cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 356cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 357cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_START \ 358cb14e93bSKumar Gala (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 359cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 360cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 361cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 362cb14e93bSKumar Gala 363cb14e93bSKumar Gala 364c013b749SHaiying Wang /* NAND flash config */ 365a3055c58SMatthew McClintock #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 366c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 367c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 368c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 369c013b749SHaiying Wang | BR_V) /* valid */ 370a3055c58SMatthew McClintock #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 371c013b749SHaiying Wang | OR_FCM_PGS /* Large Page*/ \ 372c013b749SHaiying Wang | OR_FCM_CSCT \ 373c013b749SHaiying Wang | OR_FCM_CST \ 374c013b749SHaiying Wang | OR_FCM_CHT \ 375c013b749SHaiying Wang | OR_FCM_SCY_1 \ 376c013b749SHaiying Wang | OR_FCM_TRLX \ 377c013b749SHaiying Wang | OR_FCM_EHTR) 378c013b749SHaiying Wang 379cb14e93bSKumar Gala #ifdef CONFIG_RAMBOOT_NAND 380a3055c58SMatthew McClintock #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 381a3055c58SMatthew McClintock #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 382cb14e93bSKumar Gala #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 383cb14e93bSKumar Gala #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 384cb14e93bSKumar Gala #else 385cb14e93bSKumar Gala #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 386cb14e93bSKumar Gala #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 387a3055c58SMatthew McClintock #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 388a3055c58SMatthew McClintock #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 389cb14e93bSKumar Gala #endif 39072a9414aSKumar Gala #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 391c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 392c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 393c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 394c013b749SHaiying Wang | BR_V) /* valid */ 395a3055c58SMatthew McClintock #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 39672a9414aSKumar Gala #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 397c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 398c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 399c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 400c013b749SHaiying Wang | BR_V) /* valid */ 401a3055c58SMatthew McClintock #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 402c013b749SHaiying Wang 40372a9414aSKumar Gala #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 404c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 405c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 406c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 407c013b749SHaiying Wang | BR_V) /* valid */ 408a3055c58SMatthew McClintock #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 409c013b749SHaiying Wang 410c013b749SHaiying Wang 411129ba616SKumar Gala /* Serial Port - controlled on board with jumper J8 412129ba616SKumar Gala * open - index 2 413129ba616SKumar Gala * shorted - index 1 414129ba616SKumar Gala */ 415129ba616SKumar Gala #define CONFIG_CONS_INDEX 1 4166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 4176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 4186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 4196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 420cb14e93bSKumar Gala #ifdef CONFIG_NAND_SPL 421cb14e93bSKumar Gala #define CONFIG_NS16550_MIN_FUNCTIONS 422cb14e93bSKumar Gala #endif 423129ba616SKumar Gala 4246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 425129ba616SKumar Gala {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 426129ba616SKumar Gala 4276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 4286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 429129ba616SKumar Gala 430129ba616SKumar Gala /* Use the HUSH parser */ 4316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 4326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_HUSH_PARSER 4336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 434129ba616SKumar Gala #endif 435129ba616SKumar Gala 436129ba616SKumar Gala /* 437129ba616SKumar Gala * Pass open firmware flat tree 438129ba616SKumar Gala */ 439129ba616SKumar Gala #define CONFIG_OF_LIBFDT 1 440129ba616SKumar Gala #define CONFIG_OF_BOARD_SETUP 1 441129ba616SKumar Gala #define CONFIG_OF_STDOUT_VIA_ALIAS 1 442129ba616SKumar Gala 443129ba616SKumar Gala /* new uImage format support */ 444129ba616SKumar Gala #define CONFIG_FIT 1 445129ba616SKumar Gala #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 446129ba616SKumar Gala 447129ba616SKumar Gala /* I2C */ 448129ba616SKumar Gala #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 449129ba616SKumar Gala #define CONFIG_HARD_I2C /* I2C with hardware support */ 450129ba616SKumar Gala #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 4511f3ba317SHaiying Wang #define CONFIG_I2C_MULTI_BUS 4526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 4536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 4546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 4556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 4566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 4576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 458129ba616SKumar Gala 459129ba616SKumar Gala /* 460445a7b38SHaiying Wang * I2C2 EEPROM 461445a7b38SHaiying Wang */ 462445a7b38SHaiying Wang #define CONFIG_ID_EEPROM 463445a7b38SHaiying Wang #ifdef CONFIG_ID_EEPROM 4646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_NXID 465445a7b38SHaiying Wang #endif 4666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 4676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 4686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_EEPROM_BUS_NUM 1 469445a7b38SHaiying Wang 470445a7b38SHaiying Wang /* 471129ba616SKumar Gala * General PCI 472129ba616SKumar Gala * Memory space is mapped 1-1, but I/O space must start from 0. 473129ba616SKumar Gala */ 474129ba616SKumar Gala 475129ba616SKumar Gala /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 47618ea5551SKumar Gala #define CONFIG_SYS_PCIE3_NAME "ULI" 4775af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 47818af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 479156984a3SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 48018af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 48118af1c5fSKumar Gala #else 482ad97dce1SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 4835af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 48418af1c5fSKumar Gala #endif 4856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 486aca5f018SKumar Gala #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 4875f91ef6aSKumar Gala #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 48818af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 48918af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 49018af1c5fSKumar Gala #else 4916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 49218af1c5fSKumar Gala #endif 4936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 494129ba616SKumar Gala 495129ba616SKumar Gala /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 49618ea5551SKumar Gala #define CONFIG_SYS_PCIE2_NAME "Slot 1" 4975af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 49818af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 499156984a3SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 50018af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 50118af1c5fSKumar Gala #else 502ad97dce1SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 5035af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 50418af1c5fSKumar Gala #endif 5056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 506aca5f018SKumar Gala #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 5075f91ef6aSKumar Gala #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 50818af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 50918af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 51018af1c5fSKumar Gala #else 5116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 51218af1c5fSKumar Gala #endif 5136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 514129ba616SKumar Gala 515129ba616SKumar Gala /* controller 1, Slot 1, tgtid 1, Base address a000 */ 51618ea5551SKumar Gala #define CONFIG_SYS_PCIE1_NAME "Slot 2" 5175af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 51818af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 519156984a3SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 52018af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 52118af1c5fSKumar Gala #else 522ad97dce1SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 5235af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 52418af1c5fSKumar Gala #endif 5256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 526aca5f018SKumar Gala #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 5275f91ef6aSKumar Gala #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 52818af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 52918af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 53018af1c5fSKumar Gala #else 5316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 53218af1c5fSKumar Gala #endif 5336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 534129ba616SKumar Gala 535129ba616SKumar Gala #if defined(CONFIG_PCI) 536129ba616SKumar Gala 537129ba616SKumar Gala /*PCIE video card used*/ 538aca5f018SKumar Gala #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 539129ba616SKumar Gala 540129ba616SKumar Gala /* video */ 541129ba616SKumar Gala #define CONFIG_VIDEO 542129ba616SKumar Gala 543129ba616SKumar Gala #if defined(CONFIG_VIDEO) 544129ba616SKumar Gala #define CONFIG_BIOSEMU 545129ba616SKumar Gala #define CONFIG_CFB_CONSOLE 546129ba616SKumar Gala #define CONFIG_VIDEO_SW_CURSOR 547129ba616SKumar Gala #define CONFIG_VGA_AS_SINGLE_DEVICE 548129ba616SKumar Gala #define CONFIG_ATI_RADEON_FB 549129ba616SKumar Gala #define CONFIG_VIDEO_LOGO 550129ba616SKumar Gala /*#define CONFIG_CONSOLE_CURSOR*/ 5516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 552129ba616SKumar Gala #endif 553129ba616SKumar Gala 554129ba616SKumar Gala #define CONFIG_NET_MULTI 555129ba616SKumar Gala #define CONFIG_PCI_PNP /* do pci plug-and-play */ 556129ba616SKumar Gala 557129ba616SKumar Gala #undef CONFIG_EEPRO100 558129ba616SKumar Gala #undef CONFIG_TULIP 559129ba616SKumar Gala #undef CONFIG_RTL8139 56016855ec1SKumar Gala #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 561129ba616SKumar Gala 562129ba616SKumar Gala #ifndef CONFIG_PCI_PNP 5635f91ef6aSKumar Gala #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 5645f91ef6aSKumar Gala #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 565129ba616SKumar Gala #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 566129ba616SKumar Gala #endif 567129ba616SKumar Gala 568129ba616SKumar Gala #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 569129ba616SKumar Gala #define CONFIG_DOS_PARTITION 570129ba616SKumar Gala #define CONFIG_SCSI_AHCI 571129ba616SKumar Gala 572129ba616SKumar Gala #ifdef CONFIG_SCSI_AHCI 573129ba616SKumar Gala #define CONFIG_SATA_ULI5288 5746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 5756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_LUN 1 5766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 5776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 578129ba616SKumar Gala #endif /* SCSI */ 579129ba616SKumar Gala 580129ba616SKumar Gala #endif /* CONFIG_PCI */ 581129ba616SKumar Gala 582129ba616SKumar Gala 583129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 584129ba616SKumar Gala 585129ba616SKumar Gala #ifndef CONFIG_NET_MULTI 586129ba616SKumar Gala #define CONFIG_NET_MULTI 1 587129ba616SKumar Gala #endif 588129ba616SKumar Gala 589129ba616SKumar Gala #define CONFIG_MII 1 /* MII PHY management */ 590129ba616SKumar Gala #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 591129ba616SKumar Gala #define CONFIG_TSEC1 1 592129ba616SKumar Gala #define CONFIG_TSEC1_NAME "eTSEC1" 593129ba616SKumar Gala #define CONFIG_TSEC2 1 594129ba616SKumar Gala #define CONFIG_TSEC2_NAME "eTSEC2" 595129ba616SKumar Gala #define CONFIG_TSEC3 1 596129ba616SKumar Gala #define CONFIG_TSEC3_NAME "eTSEC3" 597129ba616SKumar Gala #define CONFIG_TSEC4 1 598129ba616SKumar Gala #define CONFIG_TSEC4_NAME "eTSEC4" 599129ba616SKumar Gala 6007e183cadSLiu Yu #define CONFIG_PIXIS_SGMII_CMD 6017e183cadSLiu Yu #define CONFIG_FSL_SGMII_RISER 1 6027e183cadSLiu Yu #define SGMII_RISER_PHY_OFFSET 0x1c 6037e183cadSLiu Yu 6047e183cadSLiu Yu #ifdef CONFIG_FSL_SGMII_RISER 6057e183cadSLiu Yu #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 6067e183cadSLiu Yu #endif 6077e183cadSLiu Yu 608129ba616SKumar Gala #define TSEC1_PHY_ADDR 0 609129ba616SKumar Gala #define TSEC2_PHY_ADDR 1 610129ba616SKumar Gala #define TSEC3_PHY_ADDR 2 611129ba616SKumar Gala #define TSEC4_PHY_ADDR 3 612129ba616SKumar Gala 613129ba616SKumar Gala #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 614129ba616SKumar Gala #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 615129ba616SKumar Gala #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 616129ba616SKumar Gala #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 617129ba616SKumar Gala 618129ba616SKumar Gala #define TSEC1_PHYIDX 0 619129ba616SKumar Gala #define TSEC2_PHYIDX 0 620129ba616SKumar Gala #define TSEC3_PHYIDX 0 621129ba616SKumar Gala #define TSEC4_PHYIDX 0 622129ba616SKumar Gala 623129ba616SKumar Gala #define CONFIG_ETHPRIME "eTSEC1" 624129ba616SKumar Gala 625129ba616SKumar Gala #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 626129ba616SKumar Gala #endif /* CONFIG_TSEC_ENET */ 627129ba616SKumar Gala 628129ba616SKumar Gala /* 629129ba616SKumar Gala * Environment 630129ba616SKumar Gala */ 631cb14e93bSKumar Gala 632cb14e93bSKumar Gala #if defined(CONFIG_SYS_RAMBOOT) 633cb14e93bSKumar Gala #if defined(CONFIG_RAMBOOT_NAND) 634cb14e93bSKumar Gala #define CONFIG_ENV_IS_IN_NAND 1 635cb14e93bSKumar Gala #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 636cb14e93bSKumar Gala #define CONFIG_ENV_OFFSET ((512 * 1024)\ 637cb14e93bSKumar Gala + CONFIG_SYS_NAND_BLOCK_SIZE) 638cb14e93bSKumar Gala #endif 639cb14e93bSKumar Gala 640cb14e93bSKumar Gala #else 6415a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 6426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 6430e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR 0xfff80000 644129ba616SKumar Gala #else 6456fc110bdSHaiying Wang #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 646129ba616SKumar Gala #endif 6470e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 6480e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 649cb14e93bSKumar Gala #endif 650129ba616SKumar Gala 651129ba616SKumar Gala #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 6526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 653129ba616SKumar Gala 654129ba616SKumar Gala /* 655129ba616SKumar Gala * Command line configuration. 656129ba616SKumar Gala */ 657129ba616SKumar Gala #include <config_cmd_default.h> 658129ba616SKumar Gala 65967f94476SYork Sun #define CONFIG_CMD_ERRATA 660129ba616SKumar Gala #define CONFIG_CMD_IRQ 661129ba616SKumar Gala #define CONFIG_CMD_PING 662129ba616SKumar Gala #define CONFIG_CMD_I2C 663129ba616SKumar Gala #define CONFIG_CMD_MII 664129ba616SKumar Gala #define CONFIG_CMD_ELF 6651c9aa76bSKumar Gala #define CONFIG_CMD_SETEXPR 666199e262eSBecky Bruce #define CONFIG_CMD_REGINFO 667129ba616SKumar Gala 668129ba616SKumar Gala #if defined(CONFIG_PCI) 669129ba616SKumar Gala #define CONFIG_CMD_PCI 670129ba616SKumar Gala #define CONFIG_CMD_NET 671129ba616SKumar Gala #define CONFIG_CMD_SCSI 672129ba616SKumar Gala #define CONFIG_CMD_EXT2 673129ba616SKumar Gala #endif 674129ba616SKumar Gala 675863a3eacSZhao Chenhui /* 676863a3eacSZhao Chenhui * USB 677863a3eacSZhao Chenhui */ 678863a3eacSZhao Chenhui #define CONFIG_USB_EHCI 679863a3eacSZhao Chenhui 680863a3eacSZhao Chenhui #ifdef CONFIG_USB_EHCI 681863a3eacSZhao Chenhui #define CONFIG_CMD_USB 682863a3eacSZhao Chenhui #define CONFIG_USB_EHCI_PCI 683863a3eacSZhao Chenhui #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 684863a3eacSZhao Chenhui #define CONFIG_USB_STORAGE 685863a3eacSZhao Chenhui #define CONFIG_PCI_EHCI_DEVICE 0 686863a3eacSZhao Chenhui #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 687863a3eacSZhao Chenhui #endif 688863a3eacSZhao Chenhui 689129ba616SKumar Gala #undef CONFIG_WATCHDOG /* watchdog disabled */ 690129ba616SKumar Gala 691129ba616SKumar Gala /* 692129ba616SKumar Gala * Miscellaneous configurable options 693129ba616SKumar Gala */ 6946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 695129ba616SKumar Gala #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 6965be58f5fSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 6976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 6986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 699129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 7006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 701129ba616SKumar Gala #else 7026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 703129ba616SKumar Gala #endif 7046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 7056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 7066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 7076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 708129ba616SKumar Gala 709129ba616SKumar Gala /* 710129ba616SKumar Gala * For booting Linux, the board info and command line data 711*a832ac41SKumar Gala * have to be in the first 64 MB of memory, since this is 712129ba616SKumar Gala * the maximum mapped by the Linux kernel during initialization. 713129ba616SKumar Gala */ 714*a832ac41SKumar Gala #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 715*a832ac41SKumar Gala #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 716129ba616SKumar Gala 717129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 718129ba616SKumar Gala #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 719129ba616SKumar Gala #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 720129ba616SKumar Gala #endif 721129ba616SKumar Gala 722129ba616SKumar Gala /* 723129ba616SKumar Gala * Environment Configuration 724129ba616SKumar Gala */ 725129ba616SKumar Gala 726129ba616SKumar Gala /* The mac addresses for all ethernet interface */ 727129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 728129ba616SKumar Gala #define CONFIG_HAS_ETH0 729129ba616SKumar Gala #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 730129ba616SKumar Gala #define CONFIG_HAS_ETH1 731129ba616SKumar Gala #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 732129ba616SKumar Gala #define CONFIG_HAS_ETH2 733129ba616SKumar Gala #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 734129ba616SKumar Gala #define CONFIG_HAS_ETH3 735129ba616SKumar Gala #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 736129ba616SKumar Gala #endif 737129ba616SKumar Gala 738129ba616SKumar Gala #define CONFIG_IPADDR 192.168.1.254 739129ba616SKumar Gala 740129ba616SKumar Gala #define CONFIG_HOSTNAME unknown 741129ba616SKumar Gala #define CONFIG_ROOTPATH /opt/nfsroot 742129ba616SKumar Gala #define CONFIG_BOOTFILE uImage 743129ba616SKumar Gala #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 744129ba616SKumar Gala 745129ba616SKumar Gala #define CONFIG_SERVERIP 192.168.1.1 746129ba616SKumar Gala #define CONFIG_GATEWAYIP 192.168.1.1 747129ba616SKumar Gala #define CONFIG_NETMASK 255.255.255.0 748129ba616SKumar Gala 749129ba616SKumar Gala /* default location for tftp and bootm */ 750129ba616SKumar Gala #define CONFIG_LOADADDR 1000000 751129ba616SKumar Gala 752129ba616SKumar Gala #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 753129ba616SKumar Gala #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 754129ba616SKumar Gala 755129ba616SKumar Gala #define CONFIG_BAUDRATE 115200 756129ba616SKumar Gala 757129ba616SKumar Gala #define CONFIG_EXTRA_ENV_SETTINGS \ 7585103d7aaSZhao Chenhui "hwconfig=fsl_ddr:ctlr_intlv=bank,ecc=off\0" \ 759129ba616SKumar Gala "netdev=eth0\0" \ 760129ba616SKumar Gala "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 761129ba616SKumar Gala "tftpflash=tftpboot $loadaddr $uboot; " \ 76214d0a02aSWolfgang Denk "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 76314d0a02aSWolfgang Denk "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 76414d0a02aSWolfgang Denk "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 76514d0a02aSWolfgang Denk "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 76614d0a02aSWolfgang Denk "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 767129ba616SKumar Gala "consoledev=ttyS0\0" \ 768129ba616SKumar Gala "ramdiskaddr=2000000\0" \ 769129ba616SKumar Gala "ramdiskfile=8572ds/ramdisk.uboot\0" \ 770129ba616SKumar Gala "fdtaddr=c00000\0" \ 771129ba616SKumar Gala "fdtfile=8572ds/mpc8572ds.dtb\0" \ 772129ba616SKumar Gala "bdev=sda3\0" 773129ba616SKumar Gala 774129ba616SKumar Gala #define CONFIG_HDBOOT \ 775129ba616SKumar Gala "setenv bootargs root=/dev/$bdev rw " \ 776129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 777129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 778129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 779129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 780129ba616SKumar Gala 781129ba616SKumar Gala #define CONFIG_NFSBOOTCOMMAND \ 782129ba616SKumar Gala "setenv bootargs root=/dev/nfs rw " \ 783129ba616SKumar Gala "nfsroot=$serverip:$rootpath " \ 784129ba616SKumar Gala "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 785129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 786129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 787129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 788129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 789129ba616SKumar Gala 790129ba616SKumar Gala #define CONFIG_RAMBOOTCOMMAND \ 791129ba616SKumar Gala "setenv bootargs root=/dev/ram rw " \ 792129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 793129ba616SKumar Gala "tftp $ramdiskaddr $ramdiskfile;" \ 794129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 795129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 796129ba616SKumar Gala "bootm $loadaddr $ramdiskaddr $fdtaddr" 797129ba616SKumar Gala 798129ba616SKumar Gala #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 799129ba616SKumar Gala 800129ba616SKumar Gala #endif /* __CONFIG_H */ 801