1129ba616SKumar Gala /* 27c57f3e8SKumar Gala * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3129ba616SKumar Gala * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5129ba616SKumar Gala */ 6129ba616SKumar Gala 7129ba616SKumar Gala /* 8129ba616SKumar Gala * mpc8572ds board configuration file 9129ba616SKumar Gala * 10129ba616SKumar Gala */ 11129ba616SKumar Gala #ifndef __CONFIG_H 12129ba616SKumar Gala #define __CONFIG_H 13129ba616SKumar Gala 14509c4c4cSKumar Gala #include "../board/freescale/common/ics307_clk.h" 15509c4c4cSKumar Gala 16cb14e93bSKumar Gala #ifndef CONFIG_SYS_TEXT_BASE 1718025756SYork Sun #define CONFIG_SYS_TEXT_BASE 0xeff40000 18cb14e93bSKumar Gala #endif 19cb14e93bSKumar Gala 207a577fdaSKumar Gala #ifndef CONFIG_RESET_VECTOR_ADDRESS 217a577fdaSKumar Gala #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 227a577fdaSKumar Gala #endif 237a577fdaSKumar Gala 24cb14e93bSKumar Gala #ifndef CONFIG_SYS_MONITOR_BASE 25cb14e93bSKumar Gala #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 26cb14e93bSKumar Gala #endif 27cb14e93bSKumar Gala 28129ba616SKumar Gala /* High Level Configuration Options */ 29129ba616SKumar Gala #define CONFIG_MP 1 /* support multiple processors */ 30129ba616SKumar Gala 31b38eaec5SRobert P. J. Day #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 32b38eaec5SRobert P. J. Day #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 33b38eaec5SRobert P. J. Day #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 34129ba616SKumar Gala #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 35842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 36129ba616SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 370151cbacSKumar Gala #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 38129ba616SKumar Gala 39129ba616SKumar Gala #define CONFIG_TSEC_ENET /* tsec ethernet support */ 40129ba616SKumar Gala #define CONFIG_ENV_OVERWRITE 41129ba616SKumar Gala 42509c4c4cSKumar Gala #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 43509c4c4cSKumar Gala #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 444ca06607SHaiying Wang #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 45129ba616SKumar Gala 46129ba616SKumar Gala /* 47129ba616SKumar Gala * These can be toggled for performance analysis, otherwise use default. 48129ba616SKumar Gala */ 49129ba616SKumar Gala #define CONFIG_L2_CACHE /* toggle L2 cache */ 50129ba616SKumar Gala #define CONFIG_BTB /* toggle branch predition */ 51129ba616SKumar Gala 52129ba616SKumar Gala #define CONFIG_ENABLE_36BIT_PHYS 1 53129ba616SKumar Gala 5418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 5518af1c5fSKumar Gala #define CONFIG_ADDR_MAP 1 5618af1c5fSKumar Gala #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 5718af1c5fSKumar Gala #endif 5818af1c5fSKumar Gala 596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x7fffffff 61129ba616SKumar Gala #define CONFIG_PANIC_HANG /* do not reset board on panic */ 62129ba616SKumar Gala 63129ba616SKumar Gala /* 64cb14e93bSKumar Gala * Config the L2 Cache as L2 SRAM 65cb14e93bSKumar Gala */ 66cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 67cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 68cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 69cb14e93bSKumar Gala #else 70cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 71cb14e93bSKumar Gala #endif 72cb14e93bSKumar Gala #define CONFIG_SYS_L2_SIZE (512 << 10) 73cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 74cb14e93bSKumar Gala 75e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR 0xffe00000 76e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 77129ba616SKumar Gala 788d22ddcaSKumar Gala #if defined(CONFIG_NAND_SPL) 79e46fedfeSTimur Tabi #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 80cb14e93bSKumar Gala #endif 81cb14e93bSKumar Gala 82129ba616SKumar Gala /* DDR Setup */ 83f8523cb0SKumar Gala #define CONFIG_VERY_BIG_RAM 84129ba616SKumar Gala #undef CONFIG_FSL_DDR_INTERACTIVE 85129ba616SKumar Gala #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 86129ba616SKumar Gala #define CONFIG_DDR_SPD 87129ba616SKumar Gala 88d34897d3SYork Sun #define CONFIG_DDR_ECC 899b0ad1b1SDave Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 90129ba616SKumar Gala #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 91129ba616SKumar Gala 926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 94129ba616SKumar Gala 95129ba616SKumar Gala #define CONFIG_DIMM_SLOTS_PER_CTLR 1 96129ba616SKumar Gala #define CONFIG_CHIP_SELECTS_PER_CTRL 2 97129ba616SKumar Gala 98129ba616SKumar Gala /* I2C addresses of SPD EEPROMs */ 996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 100129ba616SKumar Gala #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 101129ba616SKumar Gala #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 102129ba616SKumar Gala 103129ba616SKumar Gala /* These are used when DDR doesn't use SPD. */ 104dc889e86SDave Liu #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 106dc889e86SDave Liu #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 107dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_3 0x00020000 1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 0x00260802 109dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 110dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 111dc889e86SDave Liu #define CONFIG_SYS_DDR_MODE_1 0x00440462 1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x00000000 113dc889e86SDave Liu #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 115dc889e86SDave Liu #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 1166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 1176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 118dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 119dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL2 0x24400000 120129ba616SKumar Gala 1216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 1226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 1236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SBE 0x00010000 124129ba616SKumar Gala 125129ba616SKumar Gala /* 126129ba616SKumar Gala * Make sure required options are set 127129ba616SKumar Gala */ 128129ba616SKumar Gala #ifndef CONFIG_SPD_EEPROM 129129ba616SKumar Gala #error ("CONFIG_SPD_EEPROM is required") 130129ba616SKumar Gala #endif 131129ba616SKumar Gala 132129ba616SKumar Gala #undef CONFIG_CLOCKS_IN_MHZ 133129ba616SKumar Gala 134129ba616SKumar Gala /* 135129ba616SKumar Gala * Memory map 136129ba616SKumar Gala * 137129ba616SKumar Gala * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 138129ba616SKumar Gala * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 139129ba616SKumar Gala * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 140129ba616SKumar Gala * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 141129ba616SKumar Gala * 142129ba616SKumar Gala * Localbus cacheable (TBD) 143129ba616SKumar Gala * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 144129ba616SKumar Gala * 145129ba616SKumar Gala * Localbus non-cacheable 146129ba616SKumar Gala * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 147129ba616SKumar Gala * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 148c013b749SHaiying Wang * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 149129ba616SKumar Gala * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 150129ba616SKumar Gala * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 151129ba616SKumar Gala * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 152129ba616SKumar Gala */ 153129ba616SKumar Gala 154129ba616SKumar Gala /* 155129ba616SKumar Gala * Local Bus Definitions 156129ba616SKumar Gala */ 1576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 15818af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 15918af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 16018af1c5fSKumar Gala #else 161c953ddfdSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 16218af1c5fSKumar Gala #endif 163129ba616SKumar Gala 164cb14e93bSKumar Gala #define CONFIG_FLASH_BR_PRELIM \ 1657ee41107STimur Tabi (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 166cb14e93bSKumar Gala #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 167129ba616SKumar Gala 168c953ddfdSKumar Gala #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 1696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 170129ba616SKumar Gala 17118af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 1726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 173129ba616SKumar Gala #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 174129ba616SKumar Gala 1756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 1766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CHECKSUM 1786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 1796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 180129ba616SKumar Gala 181cb14e93bSKumar Gala #undef CONFIG_SYS_RAMBOOT 182129ba616SKumar Gala 183129ba616SKumar Gala #define CONFIG_FLASH_CFI_DRIVER 1846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 1866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 187129ba616SKumar Gala 188129ba616SKumar Gala #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 189129ba616SKumar Gala 190558710b9SKumar Gala #define CONFIG_HWCONFIG /* enable hwconfig */ 191129ba616SKumar Gala #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 192129ba616SKumar Gala #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 19318af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 19418af1c5fSKumar Gala #define PIXIS_BASE_PHYS 0xfffdf0000ull 19518af1c5fSKumar Gala #else 19652b565f5SKumar Gala #define PIXIS_BASE_PHYS PIXIS_BASE 19718af1c5fSKumar Gala #endif 198129ba616SKumar Gala 19952b565f5SKumar Gala #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 201129ba616SKumar Gala 202129ba616SKumar Gala #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 203129ba616SKumar Gala #define PIXIS_VER 0x1 /* Board version at offset 1 */ 204129ba616SKumar Gala #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 205129ba616SKumar Gala #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 206129ba616SKumar Gala #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 207129ba616SKumar Gala #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 208129ba616SKumar Gala #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 209129ba616SKumar Gala #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 210129ba616SKumar Gala #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 211129ba616SKumar Gala #define PIXIS_VCTL 0x10 /* VELA Control Register */ 212129ba616SKumar Gala #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 213129ba616SKumar Gala #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 214129ba616SKumar Gala #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 215129ba616SKumar Gala #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 216129ba616SKumar Gala #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 2176bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 2186bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 2196bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 2206bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 2216bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 222129ba616SKumar Gala #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 223129ba616SKumar Gala #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 224129ba616SKumar Gala #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 225129ba616SKumar Gala #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 226129ba616SKumar Gala #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 227129ba616SKumar Gala #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 228129ba616SKumar Gala #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 229129ba616SKumar Gala #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 230129ba616SKumar Gala #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 231129ba616SKumar Gala #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 232129ba616SKumar Gala #define PIXIS_LED 0x25 /* LED Register */ 233129ba616SKumar Gala 234cb14e93bSKumar Gala #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 235cb14e93bSKumar Gala 236129ba616SKumar Gala /* old pixis referenced names */ 237129ba616SKumar Gala #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 238129ba616SKumar Gala #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 2396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 2407e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC1SER 0x8 2417e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC2SER 0x4 2427e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC3SER 0x2 2437e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC4SER 0x1 2447e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC1SER 0x20 2457e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC2SER 0x20 2467e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC3SER 0x20 2477e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC4SER 0x20 2487e183cadSLiu Yu #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 2497e183cadSLiu Yu | PIXIS_VSPEED2_TSEC2SER \ 2507e183cadSLiu Yu | PIXIS_VSPEED2_TSEC3SER \ 2517e183cadSLiu Yu | PIXIS_VSPEED2_TSEC4SER) 2527e183cadSLiu Yu #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 2537e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC2SER \ 2547e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC3SER \ 2557e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC4SER) 256129ba616SKumar Gala 2576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 2586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 259553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 260129ba616SKumar Gala 26125ddd1fbSWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 263129ba616SKumar Gala 2646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 2656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 266129ba616SKumar Gala 267cb14e93bSKumar Gala #ifndef CONFIG_NAND_SPL 268c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE 0xffa00000 26918af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 27018af1c5fSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 27118af1c5fSKumar Gala #else 272c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 27318af1c5fSKumar Gala #endif 274cb14e93bSKumar Gala #else 275cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE 0xfff00000 276cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 277cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 278cb14e93bSKumar Gala #else 279cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 280cb14e93bSKumar Gala #endif 281cb14e93bSKumar Gala #endif 282cb14e93bSKumar Gala 283c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 284c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x40000, \ 285c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x80000,\ 286c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0xC0000} 287c013b749SHaiying Wang #define CONFIG_SYS_MAX_NAND_DEVICE 4 288c013b749SHaiying Wang #define CONFIG_CMD_NAND 1 289c013b749SHaiying Wang #define CONFIG_NAND_FSL_ELBC 1 290c013b749SHaiying Wang #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 29168ec9c85SPrabhakar Kushwaha #define CONFIG_SYS_NAND_MAX_OOBFREE 5 29268ec9c85SPrabhakar Kushwaha #define CONFIG_SYS_NAND_MAX_ECCPOS 56 293c013b749SHaiying Wang 294cb14e93bSKumar Gala /* NAND boot: 4K NAND loader config */ 295cb14e93bSKumar Gala #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 296cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 297cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 298cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_START \ 299cb14e93bSKumar Gala (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 300cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 301cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 302cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 303cb14e93bSKumar Gala 304c013b749SHaiying Wang /* NAND flash config */ 305a3055c58SMatthew McClintock #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 306c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 307c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 308c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 309c013b749SHaiying Wang | BR_V) /* valid */ 310a3055c58SMatthew McClintock #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 311c013b749SHaiying Wang | OR_FCM_PGS /* Large Page*/ \ 312c013b749SHaiying Wang | OR_FCM_CSCT \ 313c013b749SHaiying Wang | OR_FCM_CST \ 314c013b749SHaiying Wang | OR_FCM_CHT \ 315c013b749SHaiying Wang | OR_FCM_SCY_1 \ 316c013b749SHaiying Wang | OR_FCM_TRLX \ 317c013b749SHaiying Wang | OR_FCM_EHTR) 318c013b749SHaiying Wang 319cb14e93bSKumar Gala #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 320cb14e93bSKumar Gala #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 321a3055c58SMatthew McClintock #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 322a3055c58SMatthew McClintock #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 3237ee41107STimur Tabi #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 324c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 325c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 326c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 327c013b749SHaiying Wang | BR_V) /* valid */ 328a3055c58SMatthew McClintock #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 3297ee41107STimur Tabi #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 330c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 331c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 332c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 333c013b749SHaiying Wang | BR_V) /* valid */ 334a3055c58SMatthew McClintock #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 335c013b749SHaiying Wang 3367ee41107STimur Tabi #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 337c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 338c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 339c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 340c013b749SHaiying Wang | BR_V) /* valid */ 341a3055c58SMatthew McClintock #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 342c013b749SHaiying Wang 343129ba616SKumar Gala /* Serial Port - controlled on board with jumper J8 344129ba616SKumar Gala * open - index 2 345129ba616SKumar Gala * shorted - index 1 346129ba616SKumar Gala */ 347129ba616SKumar Gala #define CONFIG_CONS_INDEX 1 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 351cb14e93bSKumar Gala #ifdef CONFIG_NAND_SPL 352cb14e93bSKumar Gala #define CONFIG_NS16550_MIN_FUNCTIONS 353cb14e93bSKumar Gala #endif 354129ba616SKumar Gala 3556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 356129ba616SKumar Gala {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 357129ba616SKumar Gala 3586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 3596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 360129ba616SKumar Gala 361129ba616SKumar Gala /* I2C */ 36200f792e0SHeiko Schocher #define CONFIG_SYS_I2C 36300f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 36400f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 36500f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 36600f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 36700f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 36800f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 36900f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 37000f792e0SHeiko Schocher #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 3716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 372129ba616SKumar Gala 373129ba616SKumar Gala /* 374445a7b38SHaiying Wang * I2C2 EEPROM 375445a7b38SHaiying Wang */ 376445a7b38SHaiying Wang #define CONFIG_ID_EEPROM 377445a7b38SHaiying Wang #ifdef CONFIG_ID_EEPROM 3786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_NXID 379445a7b38SHaiying Wang #endif 3806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 3816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 3826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_EEPROM_BUS_NUM 1 383445a7b38SHaiying Wang 384445a7b38SHaiying Wang /* 385129ba616SKumar Gala * General PCI 386129ba616SKumar Gala * Memory space is mapped 1-1, but I/O space must start from 0. 387129ba616SKumar Gala */ 388129ba616SKumar Gala 389129ba616SKumar Gala /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 39018ea5551SKumar Gala #define CONFIG_SYS_PCIE3_NAME "ULI" 3915af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 39218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 393156984a3SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 39418af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 39518af1c5fSKumar Gala #else 396ad97dce1SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 3975af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 39818af1c5fSKumar Gala #endif 3996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 400aca5f018SKumar Gala #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 4015f91ef6aSKumar Gala #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 40218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 40318af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 40418af1c5fSKumar Gala #else 4056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 40618af1c5fSKumar Gala #endif 4076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 408129ba616SKumar Gala 409129ba616SKumar Gala /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 41018ea5551SKumar Gala #define CONFIG_SYS_PCIE2_NAME "Slot 1" 4115af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 41218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 413156984a3SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 41418af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 41518af1c5fSKumar Gala #else 416ad97dce1SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 4175af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 41818af1c5fSKumar Gala #endif 4196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 420aca5f018SKumar Gala #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 4215f91ef6aSKumar Gala #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 42218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 42318af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 42418af1c5fSKumar Gala #else 4256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 42618af1c5fSKumar Gala #endif 4276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 428129ba616SKumar Gala 429129ba616SKumar Gala /* controller 1, Slot 1, tgtid 1, Base address a000 */ 43018ea5551SKumar Gala #define CONFIG_SYS_PCIE1_NAME "Slot 2" 4315af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 43218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 433156984a3SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 43418af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 43518af1c5fSKumar Gala #else 436ad97dce1SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 4375af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 43818af1c5fSKumar Gala #endif 4396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 440aca5f018SKumar Gala #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 4415f91ef6aSKumar Gala #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 44218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 44318af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 44418af1c5fSKumar Gala #else 4456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 44618af1c5fSKumar Gala #endif 4476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 448129ba616SKumar Gala 449129ba616SKumar Gala #if defined(CONFIG_PCI) 450129ba616SKumar Gala 451129ba616SKumar Gala /*PCIE video card used*/ 452aca5f018SKumar Gala #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 453129ba616SKumar Gala 454129ba616SKumar Gala /* video */ 455129ba616SKumar Gala 456129ba616SKumar Gala #if defined(CONFIG_VIDEO) 457129ba616SKumar Gala #define CONFIG_BIOSEMU 458129ba616SKumar Gala #define CONFIG_ATI_RADEON_FB 459129ba616SKumar Gala #define CONFIG_VIDEO_LOGO 4606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 461129ba616SKumar Gala #endif 462129ba616SKumar Gala 463129ba616SKumar Gala #undef CONFIG_EEPRO100 464129ba616SKumar Gala #undef CONFIG_TULIP 465129ba616SKumar Gala 466129ba616SKumar Gala #ifndef CONFIG_PCI_PNP 4675f91ef6aSKumar Gala #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 4685f91ef6aSKumar Gala #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 469129ba616SKumar Gala #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 470129ba616SKumar Gala #endif 471129ba616SKumar Gala 472129ba616SKumar Gala #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 473129ba616SKumar Gala #define CONFIG_SCSI_AHCI 474129ba616SKumar Gala 475129ba616SKumar Gala #ifdef CONFIG_SCSI_AHCI 476344ca0b4SRob Herring #define CONFIG_LIBATA 477129ba616SKumar Gala #define CONFIG_SATA_ULI5288 4786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 4796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_LUN 1 4806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 4816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 482129ba616SKumar Gala #endif /* SCSI */ 483129ba616SKumar Gala 484129ba616SKumar Gala #endif /* CONFIG_PCI */ 485129ba616SKumar Gala 486129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 487129ba616SKumar Gala 488129ba616SKumar Gala #define CONFIG_MII 1 /* MII PHY management */ 489129ba616SKumar Gala #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 490129ba616SKumar Gala #define CONFIG_TSEC1 1 491129ba616SKumar Gala #define CONFIG_TSEC1_NAME "eTSEC1" 492129ba616SKumar Gala #define CONFIG_TSEC2 1 493129ba616SKumar Gala #define CONFIG_TSEC2_NAME "eTSEC2" 494129ba616SKumar Gala #define CONFIG_TSEC3 1 495129ba616SKumar Gala #define CONFIG_TSEC3_NAME "eTSEC3" 496129ba616SKumar Gala #define CONFIG_TSEC4 1 497129ba616SKumar Gala #define CONFIG_TSEC4_NAME "eTSEC4" 498129ba616SKumar Gala 4997e183cadSLiu Yu #define CONFIG_PIXIS_SGMII_CMD 5007e183cadSLiu Yu #define CONFIG_FSL_SGMII_RISER 1 5017e183cadSLiu Yu #define SGMII_RISER_PHY_OFFSET 0x1c 5027e183cadSLiu Yu 5037e183cadSLiu Yu #ifdef CONFIG_FSL_SGMII_RISER 5047e183cadSLiu Yu #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 5057e183cadSLiu Yu #endif 5067e183cadSLiu Yu 507129ba616SKumar Gala #define TSEC1_PHY_ADDR 0 508129ba616SKumar Gala #define TSEC2_PHY_ADDR 1 509129ba616SKumar Gala #define TSEC3_PHY_ADDR 2 510129ba616SKumar Gala #define TSEC4_PHY_ADDR 3 511129ba616SKumar Gala 512129ba616SKumar Gala #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 513129ba616SKumar Gala #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 514129ba616SKumar Gala #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 515129ba616SKumar Gala #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 516129ba616SKumar Gala 517129ba616SKumar Gala #define TSEC1_PHYIDX 0 518129ba616SKumar Gala #define TSEC2_PHYIDX 0 519129ba616SKumar Gala #define TSEC3_PHYIDX 0 520129ba616SKumar Gala #define TSEC4_PHYIDX 0 521129ba616SKumar Gala 522129ba616SKumar Gala #define CONFIG_ETHPRIME "eTSEC1" 523129ba616SKumar Gala 524129ba616SKumar Gala #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 525129ba616SKumar Gala #endif /* CONFIG_TSEC_ENET */ 526129ba616SKumar Gala 527129ba616SKumar Gala /* 528129ba616SKumar Gala * Environment 529129ba616SKumar Gala */ 530cb14e93bSKumar Gala 531cb14e93bSKumar Gala #if defined(CONFIG_SYS_RAMBOOT) 532cb14e93bSKumar Gala 533cb14e93bSKumar Gala #else 5345a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 5356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 5360e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR 0xfff80000 537129ba616SKumar Gala #else 5386fc110bdSHaiying Wang #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 539129ba616SKumar Gala #endif 5400e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 5410e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 542cb14e93bSKumar Gala #endif 543129ba616SKumar Gala 544129ba616SKumar Gala #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 5456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 546129ba616SKumar Gala 547129ba616SKumar Gala /* 548129ba616SKumar Gala * Command line configuration. 549129ba616SKumar Gala */ 55067f94476SYork Sun #define CONFIG_CMD_ERRATA 551129ba616SKumar Gala #define CONFIG_CMD_IRQ 552199e262eSBecky Bruce #define CONFIG_CMD_REGINFO 553129ba616SKumar Gala 554129ba616SKumar Gala #if defined(CONFIG_PCI) 555129ba616SKumar Gala #define CONFIG_CMD_PCI 556c649e3c9SSimon Glass #define CONFIG_SCSI 557129ba616SKumar Gala #endif 558129ba616SKumar Gala 559863a3eacSZhao Chenhui /* 560863a3eacSZhao Chenhui * USB 561863a3eacSZhao Chenhui */ 562*8850c5d5STom Rini #define CONFIG_USB_EHCI_HCD 563863a3eacSZhao Chenhui 564*8850c5d5STom Rini #ifdef CONFIG_USB_EHCI_HCD 565863a3eacSZhao Chenhui #define CONFIG_USB_EHCI_PCI 566863a3eacSZhao Chenhui #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 567863a3eacSZhao Chenhui #define CONFIG_PCI_EHCI_DEVICE 0 568863a3eacSZhao Chenhui #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 569863a3eacSZhao Chenhui #endif 570863a3eacSZhao Chenhui 571129ba616SKumar Gala #undef CONFIG_WATCHDOG /* watchdog disabled */ 572129ba616SKumar Gala 573129ba616SKumar Gala /* 574129ba616SKumar Gala * Miscellaneous configurable options 575129ba616SKumar Gala */ 5766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 577129ba616SKumar Gala #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 5785be58f5fSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 5796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 580129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 5816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 582129ba616SKumar Gala #else 5836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 584129ba616SKumar Gala #endif 5856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 5866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 5876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 588129ba616SKumar Gala 589129ba616SKumar Gala /* 590129ba616SKumar Gala * For booting Linux, the board info and command line data 591a832ac41SKumar Gala * have to be in the first 64 MB of memory, since this is 592129ba616SKumar Gala * the maximum mapped by the Linux kernel during initialization. 593129ba616SKumar Gala */ 594a832ac41SKumar Gala #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 595a832ac41SKumar Gala #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 596129ba616SKumar Gala 597129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 598129ba616SKumar Gala #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 599129ba616SKumar Gala #endif 600129ba616SKumar Gala 601129ba616SKumar Gala /* 602129ba616SKumar Gala * Environment Configuration 603129ba616SKumar Gala */ 604129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 605129ba616SKumar Gala #define CONFIG_HAS_ETH0 606129ba616SKumar Gala #define CONFIG_HAS_ETH1 607129ba616SKumar Gala #define CONFIG_HAS_ETH2 608129ba616SKumar Gala #define CONFIG_HAS_ETH3 609129ba616SKumar Gala #endif 610129ba616SKumar Gala 611129ba616SKumar Gala #define CONFIG_IPADDR 192.168.1.254 612129ba616SKumar Gala 613129ba616SKumar Gala #define CONFIG_HOSTNAME unknown 6148b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/opt/nfsroot" 615b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 616129ba616SKumar Gala #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 617129ba616SKumar Gala 618129ba616SKumar Gala #define CONFIG_SERVERIP 192.168.1.1 619129ba616SKumar Gala #define CONFIG_GATEWAYIP 192.168.1.1 620129ba616SKumar Gala #define CONFIG_NETMASK 255.255.255.0 621129ba616SKumar Gala 622129ba616SKumar Gala /* default location for tftp and bootm */ 623129ba616SKumar Gala #define CONFIG_LOADADDR 1000000 624129ba616SKumar Gala 625129ba616SKumar Gala #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 626129ba616SKumar Gala 627129ba616SKumar Gala #define CONFIG_EXTRA_ENV_SETTINGS \ 628238e1467SHongtao Jia "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 629129ba616SKumar Gala "netdev=eth0\0" \ 6305368c55dSMarek Vasut "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 631129ba616SKumar Gala "tftpflash=tftpboot $loadaddr $uboot; " \ 6325368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 6335368c55dSMarek Vasut " +$filesize; " \ 6345368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 6355368c55dSMarek Vasut " +$filesize; " \ 6365368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6375368c55dSMarek Vasut " $filesize; " \ 6385368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 6395368c55dSMarek Vasut " +$filesize; " \ 6405368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 6415368c55dSMarek Vasut " $filesize\0" \ 642129ba616SKumar Gala "consoledev=ttyS0\0" \ 643129ba616SKumar Gala "ramdiskaddr=2000000\0" \ 644129ba616SKumar Gala "ramdiskfile=8572ds/ramdisk.uboot\0" \ 645b24a4f62SScott Wood "fdtaddr=1e00000\0" \ 646129ba616SKumar Gala "fdtfile=8572ds/mpc8572ds.dtb\0" \ 647129ba616SKumar Gala "bdev=sda3\0" 648129ba616SKumar Gala 649129ba616SKumar Gala #define CONFIG_HDBOOT \ 650129ba616SKumar Gala "setenv bootargs root=/dev/$bdev rw " \ 651129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 652129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 653129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 654129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 655129ba616SKumar Gala 656129ba616SKumar Gala #define CONFIG_NFSBOOTCOMMAND \ 657129ba616SKumar Gala "setenv bootargs root=/dev/nfs rw " \ 658129ba616SKumar Gala "nfsroot=$serverip:$rootpath " \ 659129ba616SKumar Gala "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 660129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 661129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 662129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 663129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 664129ba616SKumar Gala 665129ba616SKumar Gala #define CONFIG_RAMBOOTCOMMAND \ 666129ba616SKumar Gala "setenv bootargs root=/dev/ram rw " \ 667129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 668129ba616SKumar Gala "tftp $ramdiskaddr $ramdiskfile;" \ 669129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 670129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 671129ba616SKumar Gala "bootm $loadaddr $ramdiskaddr $fdtaddr" 672129ba616SKumar Gala 673129ba616SKumar Gala #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 674129ba616SKumar Gala 675129ba616SKumar Gala #endif /* __CONFIG_H */ 676