1129ba616SKumar Gala /* 27c57f3e8SKumar Gala * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3129ba616SKumar Gala * 4129ba616SKumar Gala * See file CREDITS for list of people who contributed to this 5129ba616SKumar Gala * project. 6129ba616SKumar Gala * 7129ba616SKumar Gala * This program is free software; you can redistribute it and/or 8129ba616SKumar Gala * modify it under the terms of the GNU General Public License as 9129ba616SKumar Gala * published by the Free Software Foundation; either version 2 of 10129ba616SKumar Gala * the License, or (at your option) any later version. 11129ba616SKumar Gala * 12129ba616SKumar Gala * This program is distributed in the hope that it will be useful, 13129ba616SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 14129ba616SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15129ba616SKumar Gala * GNU General Public License for more details. 16129ba616SKumar Gala * 17129ba616SKumar Gala * You should have received a copy of the GNU General Public License 18129ba616SKumar Gala * along with this program; if not, write to the Free Software 19129ba616SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20129ba616SKumar Gala * MA 02111-1307 USA 21129ba616SKumar Gala */ 22129ba616SKumar Gala 23129ba616SKumar Gala /* 24129ba616SKumar Gala * mpc8572ds board configuration file 25129ba616SKumar Gala * 26129ba616SKumar Gala */ 27129ba616SKumar Gala #ifndef __CONFIG_H 28129ba616SKumar Gala #define __CONFIG_H 29129ba616SKumar Gala 30509c4c4cSKumar Gala #include "../board/freescale/common/ics307_clk.h" 31509c4c4cSKumar Gala 32d24f2d32SWolfgang Denk #ifdef CONFIG_36BIT 33f9edcc10SKumar Gala #define CONFIG_PHYS_64BIT 34f9edcc10SKumar Gala #endif 35f9edcc10SKumar Gala 36cb14e93bSKumar Gala #ifdef CONFIG_NAND 37cb14e93bSKumar Gala #define CONFIG_NAND_U_BOOT 38cb14e93bSKumar Gala #define CONFIG_RAMBOOT_NAND 39cb14e93bSKumar Gala #ifdef CONFIG_NAND_SPL 40cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 41cb14e93bSKumar Gala #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 42cb14e93bSKumar Gala #else 4300203c64SKumar Gala #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds 44cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE 0xf8f82000 45cb14e93bSKumar Gala #endif /* CONFIG_NAND_SPL */ 46cb14e93bSKumar Gala #endif 47cb14e93bSKumar Gala 48cb14e93bSKumar Gala #ifndef CONFIG_SYS_TEXT_BASE 49cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE 0xeff80000 50cb14e93bSKumar Gala #endif 51cb14e93bSKumar Gala 527a577fdaSKumar Gala #ifndef CONFIG_RESET_VECTOR_ADDRESS 537a577fdaSKumar Gala #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 547a577fdaSKumar Gala #endif 557a577fdaSKumar Gala 56cb14e93bSKumar Gala #ifndef CONFIG_SYS_MONITOR_BASE 57cb14e93bSKumar Gala #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 58cb14e93bSKumar Gala #endif 59cb14e93bSKumar Gala 60129ba616SKumar Gala /* High Level Configuration Options */ 61129ba616SKumar Gala #define CONFIG_BOOKE 1 /* BOOKE */ 62129ba616SKumar Gala #define CONFIG_E500 1 /* BOOKE e500 family */ 63129ba616SKumar Gala #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 64129ba616SKumar Gala #define CONFIG_MPC8572 1 65129ba616SKumar Gala #define CONFIG_MPC8572DS 1 66129ba616SKumar Gala #define CONFIG_MP 1 /* support multiple processors */ 67129ba616SKumar Gala 68c51fc5d5SKumar Gala #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 69129ba616SKumar Gala #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 70129ba616SKumar Gala #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 71129ba616SKumar Gala #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 72129ba616SKumar Gala #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 73129ba616SKumar Gala #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 74*842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 75129ba616SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 760151cbacSKumar Gala #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 77129ba616SKumar Gala 78129ba616SKumar Gala #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 79129ba616SKumar Gala 80129ba616SKumar Gala #define CONFIG_TSEC_ENET /* tsec ethernet support */ 81129ba616SKumar Gala #define CONFIG_ENV_OVERWRITE 82129ba616SKumar Gala 83509c4c4cSKumar Gala #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 84509c4c4cSKumar Gala #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 854ca06607SHaiying Wang #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 86129ba616SKumar Gala 87129ba616SKumar Gala /* 88129ba616SKumar Gala * These can be toggled for performance analysis, otherwise use default. 89129ba616SKumar Gala */ 90129ba616SKumar Gala #define CONFIG_L2_CACHE /* toggle L2 cache */ 91129ba616SKumar Gala #define CONFIG_BTB /* toggle branch predition */ 92129ba616SKumar Gala 93129ba616SKumar Gala #define CONFIG_ENABLE_36BIT_PHYS 1 94129ba616SKumar Gala 9518af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 9618af1c5fSKumar Gala #define CONFIG_ADDR_MAP 1 9718af1c5fSKumar Gala #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 9818af1c5fSKumar Gala #endif 9918af1c5fSKumar Gala 1006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x7fffffff 102129ba616SKumar Gala #define CONFIG_PANIC_HANG /* do not reset board on panic */ 103129ba616SKumar Gala 104129ba616SKumar Gala /* 105cb14e93bSKumar Gala * Config the L2 Cache as L2 SRAM 106cb14e93bSKumar Gala */ 107cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 108cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 109cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 110cb14e93bSKumar Gala #else 111cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 112cb14e93bSKumar Gala #endif 113cb14e93bSKumar Gala #define CONFIG_SYS_L2_SIZE (512 << 10) 114cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 115cb14e93bSKumar Gala 116e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR 0xffe00000 117e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 118129ba616SKumar Gala 1198d22ddcaSKumar Gala #if defined(CONFIG_NAND_SPL) 120e46fedfeSTimur Tabi #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 121cb14e93bSKumar Gala #endif 122cb14e93bSKumar Gala 123129ba616SKumar Gala /* DDR Setup */ 124f8523cb0SKumar Gala #define CONFIG_VERY_BIG_RAM 125129ba616SKumar Gala #define CONFIG_FSL_DDR2 126129ba616SKumar Gala #undef CONFIG_FSL_DDR_INTERACTIVE 127129ba616SKumar Gala #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 128129ba616SKumar Gala #define CONFIG_DDR_SPD 129129ba616SKumar Gala 130d34897d3SYork Sun #define CONFIG_DDR_ECC 1319b0ad1b1SDave Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 132129ba616SKumar Gala #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 133129ba616SKumar Gala 1346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 1356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 136129ba616SKumar Gala 137129ba616SKumar Gala #define CONFIG_NUM_DDR_CONTROLLERS 2 138129ba616SKumar Gala #define CONFIG_DIMM_SLOTS_PER_CTLR 1 139129ba616SKumar Gala #define CONFIG_CHIP_SELECTS_PER_CTRL 2 140129ba616SKumar Gala 141129ba616SKumar Gala /* I2C addresses of SPD EEPROMs */ 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 143129ba616SKumar Gala #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 144129ba616SKumar Gala #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 145129ba616SKumar Gala 146129ba616SKumar Gala /* These are used when DDR doesn't use SPD. */ 147dc889e86SDave Liu #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 1486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 149dc889e86SDave Liu #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 150dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_3 0x00020000 1516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 0x00260802 152dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 153dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 154dc889e86SDave Liu #define CONFIG_SYS_DDR_MODE_1 0x00440462 1556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x00000000 156dc889e86SDave Liu #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 1576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 158dc889e86SDave Liu #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 1596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 1606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 161dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 162dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL2 0x24400000 163129ba616SKumar Gala 1646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 1656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 1666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SBE 0x00010000 167129ba616SKumar Gala 168129ba616SKumar Gala /* 169129ba616SKumar Gala * Make sure required options are set 170129ba616SKumar Gala */ 171129ba616SKumar Gala #ifndef CONFIG_SPD_EEPROM 172129ba616SKumar Gala #error ("CONFIG_SPD_EEPROM is required") 173129ba616SKumar Gala #endif 174129ba616SKumar Gala 175129ba616SKumar Gala #undef CONFIG_CLOCKS_IN_MHZ 176129ba616SKumar Gala 177129ba616SKumar Gala /* 178129ba616SKumar Gala * Memory map 179129ba616SKumar Gala * 180129ba616SKumar Gala * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 181129ba616SKumar Gala * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 182129ba616SKumar Gala * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 183129ba616SKumar Gala * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 184129ba616SKumar Gala * 185129ba616SKumar Gala * Localbus cacheable (TBD) 186129ba616SKumar Gala * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 187129ba616SKumar Gala * 188129ba616SKumar Gala * Localbus non-cacheable 189129ba616SKumar Gala * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 190129ba616SKumar Gala * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 191c013b749SHaiying Wang * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 192129ba616SKumar Gala * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 193129ba616SKumar Gala * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 194129ba616SKumar Gala * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 195129ba616SKumar Gala */ 196129ba616SKumar Gala 197129ba616SKumar Gala /* 198129ba616SKumar Gala * Local Bus Definitions 199129ba616SKumar Gala */ 2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 20118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 20218af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 20318af1c5fSKumar Gala #else 204c953ddfdSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 20518af1c5fSKumar Gala #endif 206129ba616SKumar Gala 207cb14e93bSKumar Gala 208cb14e93bSKumar Gala #define CONFIG_FLASH_BR_PRELIM \ 2097ee41107STimur Tabi (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 210cb14e93bSKumar Gala #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 211129ba616SKumar Gala 212c953ddfdSKumar Gala #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 2136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 214129ba616SKumar Gala 21518af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 2166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 217129ba616SKumar Gala #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 218129ba616SKumar Gala 2196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 2206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CHECKSUM 2226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 224129ba616SKumar Gala 225cb14e93bSKumar Gala #if defined(CONFIG_RAMBOOT_NAND) 226cb14e93bSKumar Gala #define CONFIG_SYS_RAMBOOT 227cb14e93bSKumar Gala #define CONFIG_SYS_EXTRA_ENV_RELOC 228cb14e93bSKumar Gala #else 229cb14e93bSKumar Gala #undef CONFIG_SYS_RAMBOOT 230cb14e93bSKumar Gala #endif 231129ba616SKumar Gala 232129ba616SKumar Gala #define CONFIG_FLASH_CFI_DRIVER 2336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 2346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 2356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 236129ba616SKumar Gala 237129ba616SKumar Gala #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 238129ba616SKumar Gala 239558710b9SKumar Gala #define CONFIG_HWCONFIG /* enable hwconfig */ 240129ba616SKumar Gala #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 241129ba616SKumar Gala #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 24218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 24318af1c5fSKumar Gala #define PIXIS_BASE_PHYS 0xfffdf0000ull 24418af1c5fSKumar Gala #else 24552b565f5SKumar Gala #define PIXIS_BASE_PHYS PIXIS_BASE 24618af1c5fSKumar Gala #endif 247129ba616SKumar Gala 24852b565f5SKumar Gala #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 2496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 250129ba616SKumar Gala 251129ba616SKumar Gala #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 252129ba616SKumar Gala #define PIXIS_VER 0x1 /* Board version at offset 1 */ 253129ba616SKumar Gala #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 254129ba616SKumar Gala #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 255129ba616SKumar Gala #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 256129ba616SKumar Gala #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 257129ba616SKumar Gala #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 258129ba616SKumar Gala #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 259129ba616SKumar Gala #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 260129ba616SKumar Gala #define PIXIS_VCTL 0x10 /* VELA Control Register */ 261129ba616SKumar Gala #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 262129ba616SKumar Gala #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 263129ba616SKumar Gala #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 264129ba616SKumar Gala #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 265129ba616SKumar Gala #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 2666bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 2676bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 2686bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 2696bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 2706bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 271129ba616SKumar Gala #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 272129ba616SKumar Gala #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 273129ba616SKumar Gala #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 274129ba616SKumar Gala #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 275129ba616SKumar Gala #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 276129ba616SKumar Gala #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 277129ba616SKumar Gala #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 278129ba616SKumar Gala #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 279129ba616SKumar Gala #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 280129ba616SKumar Gala #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 281129ba616SKumar Gala #define PIXIS_LED 0x25 /* LED Register */ 282129ba616SKumar Gala 283cb14e93bSKumar Gala #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 284cb14e93bSKumar Gala 285129ba616SKumar Gala /* old pixis referenced names */ 286129ba616SKumar Gala #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 287129ba616SKumar Gala #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 2886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 2897e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC1SER 0x8 2907e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC2SER 0x4 2917e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC3SER 0x2 2927e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC4SER 0x1 2937e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC1SER 0x20 2947e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC2SER 0x20 2957e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC3SER 0x20 2967e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC4SER 0x20 2977e183cadSLiu Yu #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 2987e183cadSLiu Yu | PIXIS_VSPEED2_TSEC2SER \ 2997e183cadSLiu Yu | PIXIS_VSPEED2_TSEC3SER \ 3007e183cadSLiu Yu | PIXIS_VSPEED2_TSEC4SER) 3017e183cadSLiu Yu #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 3027e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC2SER \ 3037e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC3SER \ 3047e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC4SER) 305129ba616SKumar Gala 3066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 3076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 308553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 309129ba616SKumar Gala 31025ddd1fbSWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 3116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 312129ba616SKumar Gala 3136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 3146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 315129ba616SKumar Gala 316cb14e93bSKumar Gala #ifndef CONFIG_NAND_SPL 317c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE 0xffa00000 31818af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 31918af1c5fSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 32018af1c5fSKumar Gala #else 321c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 32218af1c5fSKumar Gala #endif 323cb14e93bSKumar Gala #else 324cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE 0xfff00000 325cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 326cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 327cb14e93bSKumar Gala #else 328cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 329cb14e93bSKumar Gala #endif 330cb14e93bSKumar Gala #endif 331cb14e93bSKumar Gala 332c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 333c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x40000, \ 334c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x80000,\ 335c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0xC0000} 336c013b749SHaiying Wang #define CONFIG_SYS_MAX_NAND_DEVICE 4 337c013b749SHaiying Wang #define CONFIG_MTD_NAND_VERIFY_WRITE 338c013b749SHaiying Wang #define CONFIG_CMD_NAND 1 339c013b749SHaiying Wang #define CONFIG_NAND_FSL_ELBC 1 340c013b749SHaiying Wang #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 341c013b749SHaiying Wang 342cb14e93bSKumar Gala /* NAND boot: 4K NAND loader config */ 343cb14e93bSKumar Gala #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 344cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 345cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 346cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_START \ 347cb14e93bSKumar Gala (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 348cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 349cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 350cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 351cb14e93bSKumar Gala 352cb14e93bSKumar Gala 353c013b749SHaiying Wang /* NAND flash config */ 354a3055c58SMatthew McClintock #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 355c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 356c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 357c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 358c013b749SHaiying Wang | BR_V) /* valid */ 359a3055c58SMatthew McClintock #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 360c013b749SHaiying Wang | OR_FCM_PGS /* Large Page*/ \ 361c013b749SHaiying Wang | OR_FCM_CSCT \ 362c013b749SHaiying Wang | OR_FCM_CST \ 363c013b749SHaiying Wang | OR_FCM_CHT \ 364c013b749SHaiying Wang | OR_FCM_SCY_1 \ 365c013b749SHaiying Wang | OR_FCM_TRLX \ 366c013b749SHaiying Wang | OR_FCM_EHTR) 367c013b749SHaiying Wang 368cb14e93bSKumar Gala #ifdef CONFIG_RAMBOOT_NAND 369a3055c58SMatthew McClintock #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 370a3055c58SMatthew McClintock #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 371cb14e93bSKumar Gala #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 372cb14e93bSKumar Gala #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 373cb14e93bSKumar Gala #else 374cb14e93bSKumar Gala #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 375cb14e93bSKumar Gala #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 376a3055c58SMatthew McClintock #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 377a3055c58SMatthew McClintock #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 378cb14e93bSKumar Gala #endif 3797ee41107STimur Tabi #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 380c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 381c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 382c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 383c013b749SHaiying Wang | BR_V) /* valid */ 384a3055c58SMatthew McClintock #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 3857ee41107STimur Tabi #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 386c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 387c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 388c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 389c013b749SHaiying Wang | BR_V) /* valid */ 390a3055c58SMatthew McClintock #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 391c013b749SHaiying Wang 3927ee41107STimur Tabi #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 393c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 394c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 395c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 396c013b749SHaiying Wang | BR_V) /* valid */ 397a3055c58SMatthew McClintock #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 398c013b749SHaiying Wang 399c013b749SHaiying Wang 400129ba616SKumar Gala /* Serial Port - controlled on board with jumper J8 401129ba616SKumar Gala * open - index 2 402129ba616SKumar Gala * shorted - index 1 403129ba616SKumar Gala */ 404129ba616SKumar Gala #define CONFIG_CONS_INDEX 1 4056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 4066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 4076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 4086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 409cb14e93bSKumar Gala #ifdef CONFIG_NAND_SPL 410cb14e93bSKumar Gala #define CONFIG_NS16550_MIN_FUNCTIONS 411cb14e93bSKumar Gala #endif 412129ba616SKumar Gala 4136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 414129ba616SKumar Gala {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 415129ba616SKumar Gala 4166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 4176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 418129ba616SKumar Gala 419129ba616SKumar Gala /* Use the HUSH parser */ 4206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 421129ba616SKumar Gala 422129ba616SKumar Gala /* 423129ba616SKumar Gala * Pass open firmware flat tree 424129ba616SKumar Gala */ 425129ba616SKumar Gala #define CONFIG_OF_LIBFDT 1 426129ba616SKumar Gala #define CONFIG_OF_BOARD_SETUP 1 427129ba616SKumar Gala #define CONFIG_OF_STDOUT_VIA_ALIAS 1 428129ba616SKumar Gala 429129ba616SKumar Gala /* new uImage format support */ 430129ba616SKumar Gala #define CONFIG_FIT 1 431129ba616SKumar Gala #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 432129ba616SKumar Gala 433129ba616SKumar Gala /* I2C */ 434129ba616SKumar Gala #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 435129ba616SKumar Gala #define CONFIG_HARD_I2C /* I2C with hardware support */ 436129ba616SKumar Gala #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 4371f3ba317SHaiying Wang #define CONFIG_I2C_MULTI_BUS 4386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 4396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 4406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 4416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 4426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 4436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 444129ba616SKumar Gala 445129ba616SKumar Gala /* 446445a7b38SHaiying Wang * I2C2 EEPROM 447445a7b38SHaiying Wang */ 448445a7b38SHaiying Wang #define CONFIG_ID_EEPROM 449445a7b38SHaiying Wang #ifdef CONFIG_ID_EEPROM 4506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_NXID 451445a7b38SHaiying Wang #endif 4526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 4536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 4546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_EEPROM_BUS_NUM 1 455445a7b38SHaiying Wang 456445a7b38SHaiying Wang /* 457129ba616SKumar Gala * General PCI 458129ba616SKumar Gala * Memory space is mapped 1-1, but I/O space must start from 0. 459129ba616SKumar Gala */ 460129ba616SKumar Gala 461129ba616SKumar Gala /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 46218ea5551SKumar Gala #define CONFIG_SYS_PCIE3_NAME "ULI" 4635af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 46418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 465156984a3SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 46618af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 46718af1c5fSKumar Gala #else 468ad97dce1SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 4695af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 47018af1c5fSKumar Gala #endif 4716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 472aca5f018SKumar Gala #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 4735f91ef6aSKumar Gala #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 47418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 47518af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 47618af1c5fSKumar Gala #else 4776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 47818af1c5fSKumar Gala #endif 4796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 480129ba616SKumar Gala 481129ba616SKumar Gala /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 48218ea5551SKumar Gala #define CONFIG_SYS_PCIE2_NAME "Slot 1" 4835af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 48418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 485156984a3SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 48618af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 48718af1c5fSKumar Gala #else 488ad97dce1SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 4895af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 49018af1c5fSKumar Gala #endif 4916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 492aca5f018SKumar Gala #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 4935f91ef6aSKumar Gala #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 49418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 49518af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 49618af1c5fSKumar Gala #else 4976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 49818af1c5fSKumar Gala #endif 4996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 500129ba616SKumar Gala 501129ba616SKumar Gala /* controller 1, Slot 1, tgtid 1, Base address a000 */ 50218ea5551SKumar Gala #define CONFIG_SYS_PCIE1_NAME "Slot 2" 5035af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 50418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 505156984a3SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 50618af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 50718af1c5fSKumar Gala #else 508ad97dce1SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 5095af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 51018af1c5fSKumar Gala #endif 5116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 512aca5f018SKumar Gala #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 5135f91ef6aSKumar Gala #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 51418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 51518af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 51618af1c5fSKumar Gala #else 5176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 51818af1c5fSKumar Gala #endif 5196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 520129ba616SKumar Gala 521129ba616SKumar Gala #if defined(CONFIG_PCI) 522129ba616SKumar Gala 523129ba616SKumar Gala /*PCIE video card used*/ 524aca5f018SKumar Gala #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 525129ba616SKumar Gala 526129ba616SKumar Gala /* video */ 527129ba616SKumar Gala #define CONFIG_VIDEO 528129ba616SKumar Gala 529129ba616SKumar Gala #if defined(CONFIG_VIDEO) 530129ba616SKumar Gala #define CONFIG_BIOSEMU 531129ba616SKumar Gala #define CONFIG_CFB_CONSOLE 532129ba616SKumar Gala #define CONFIG_VIDEO_SW_CURSOR 533129ba616SKumar Gala #define CONFIG_VGA_AS_SINGLE_DEVICE 534129ba616SKumar Gala #define CONFIG_ATI_RADEON_FB 535129ba616SKumar Gala #define CONFIG_VIDEO_LOGO 536129ba616SKumar Gala /*#define CONFIG_CONSOLE_CURSOR*/ 5376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 538129ba616SKumar Gala #endif 539129ba616SKumar Gala 540129ba616SKumar Gala #define CONFIG_PCI_PNP /* do pci plug-and-play */ 541129ba616SKumar Gala 542129ba616SKumar Gala #undef CONFIG_EEPRO100 543129ba616SKumar Gala #undef CONFIG_TULIP 544129ba616SKumar Gala #undef CONFIG_RTL8139 54516855ec1SKumar Gala #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 546129ba616SKumar Gala 547129ba616SKumar Gala #ifndef CONFIG_PCI_PNP 5485f91ef6aSKumar Gala #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 5495f91ef6aSKumar Gala #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 550129ba616SKumar Gala #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 551129ba616SKumar Gala #endif 552129ba616SKumar Gala 553129ba616SKumar Gala #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 554129ba616SKumar Gala #define CONFIG_DOS_PARTITION 555129ba616SKumar Gala #define CONFIG_SCSI_AHCI 556129ba616SKumar Gala 557129ba616SKumar Gala #ifdef CONFIG_SCSI_AHCI 558129ba616SKumar Gala #define CONFIG_SATA_ULI5288 5596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 5606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_LUN 1 5616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 5626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 563129ba616SKumar Gala #endif /* SCSI */ 564129ba616SKumar Gala 565129ba616SKumar Gala #endif /* CONFIG_PCI */ 566129ba616SKumar Gala 567129ba616SKumar Gala 568129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 569129ba616SKumar Gala 570129ba616SKumar Gala #define CONFIG_MII 1 /* MII PHY management */ 571129ba616SKumar Gala #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 572129ba616SKumar Gala #define CONFIG_TSEC1 1 573129ba616SKumar Gala #define CONFIG_TSEC1_NAME "eTSEC1" 574129ba616SKumar Gala #define CONFIG_TSEC2 1 575129ba616SKumar Gala #define CONFIG_TSEC2_NAME "eTSEC2" 576129ba616SKumar Gala #define CONFIG_TSEC3 1 577129ba616SKumar Gala #define CONFIG_TSEC3_NAME "eTSEC3" 578129ba616SKumar Gala #define CONFIG_TSEC4 1 579129ba616SKumar Gala #define CONFIG_TSEC4_NAME "eTSEC4" 580129ba616SKumar Gala 5817e183cadSLiu Yu #define CONFIG_PIXIS_SGMII_CMD 5827e183cadSLiu Yu #define CONFIG_FSL_SGMII_RISER 1 5837e183cadSLiu Yu #define SGMII_RISER_PHY_OFFSET 0x1c 5847e183cadSLiu Yu 5857e183cadSLiu Yu #ifdef CONFIG_FSL_SGMII_RISER 5867e183cadSLiu Yu #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 5877e183cadSLiu Yu #endif 5887e183cadSLiu Yu 589129ba616SKumar Gala #define TSEC1_PHY_ADDR 0 590129ba616SKumar Gala #define TSEC2_PHY_ADDR 1 591129ba616SKumar Gala #define TSEC3_PHY_ADDR 2 592129ba616SKumar Gala #define TSEC4_PHY_ADDR 3 593129ba616SKumar Gala 594129ba616SKumar Gala #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 595129ba616SKumar Gala #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 596129ba616SKumar Gala #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 597129ba616SKumar Gala #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 598129ba616SKumar Gala 599129ba616SKumar Gala #define TSEC1_PHYIDX 0 600129ba616SKumar Gala #define TSEC2_PHYIDX 0 601129ba616SKumar Gala #define TSEC3_PHYIDX 0 602129ba616SKumar Gala #define TSEC4_PHYIDX 0 603129ba616SKumar Gala 604129ba616SKumar Gala #define CONFIG_ETHPRIME "eTSEC1" 605129ba616SKumar Gala 606129ba616SKumar Gala #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 607129ba616SKumar Gala #endif /* CONFIG_TSEC_ENET */ 608129ba616SKumar Gala 609129ba616SKumar Gala /* 610129ba616SKumar Gala * Environment 611129ba616SKumar Gala */ 612cb14e93bSKumar Gala 613cb14e93bSKumar Gala #if defined(CONFIG_SYS_RAMBOOT) 614cb14e93bSKumar Gala #if defined(CONFIG_RAMBOOT_NAND) 615cb14e93bSKumar Gala #define CONFIG_ENV_IS_IN_NAND 1 616cb14e93bSKumar Gala #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 617cb14e93bSKumar Gala #define CONFIG_ENV_OFFSET ((512 * 1024)\ 618cb14e93bSKumar Gala + CONFIG_SYS_NAND_BLOCK_SIZE) 619cb14e93bSKumar Gala #endif 620cb14e93bSKumar Gala 621cb14e93bSKumar Gala #else 6225a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 6236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 6240e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR 0xfff80000 625129ba616SKumar Gala #else 6266fc110bdSHaiying Wang #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 627129ba616SKumar Gala #endif 6280e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 6290e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 630cb14e93bSKumar Gala #endif 631129ba616SKumar Gala 632129ba616SKumar Gala #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 6336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 634129ba616SKumar Gala 635129ba616SKumar Gala /* 636129ba616SKumar Gala * Command line configuration. 637129ba616SKumar Gala */ 638129ba616SKumar Gala #include <config_cmd_default.h> 639129ba616SKumar Gala 64067f94476SYork Sun #define CONFIG_CMD_ERRATA 641129ba616SKumar Gala #define CONFIG_CMD_IRQ 642129ba616SKumar Gala #define CONFIG_CMD_PING 643129ba616SKumar Gala #define CONFIG_CMD_I2C 644129ba616SKumar Gala #define CONFIG_CMD_MII 645129ba616SKumar Gala #define CONFIG_CMD_ELF 6461c9aa76bSKumar Gala #define CONFIG_CMD_SETEXPR 647199e262eSBecky Bruce #define CONFIG_CMD_REGINFO 648129ba616SKumar Gala 649129ba616SKumar Gala #if defined(CONFIG_PCI) 650129ba616SKumar Gala #define CONFIG_CMD_PCI 651129ba616SKumar Gala #define CONFIG_CMD_NET 652129ba616SKumar Gala #define CONFIG_CMD_SCSI 653129ba616SKumar Gala #define CONFIG_CMD_EXT2 654129ba616SKumar Gala #endif 655129ba616SKumar Gala 656863a3eacSZhao Chenhui /* 657863a3eacSZhao Chenhui * USB 658863a3eacSZhao Chenhui */ 659863a3eacSZhao Chenhui #define CONFIG_USB_EHCI 660863a3eacSZhao Chenhui 661863a3eacSZhao Chenhui #ifdef CONFIG_USB_EHCI 662863a3eacSZhao Chenhui #define CONFIG_CMD_USB 663863a3eacSZhao Chenhui #define CONFIG_USB_EHCI_PCI 664863a3eacSZhao Chenhui #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 665863a3eacSZhao Chenhui #define CONFIG_USB_STORAGE 666863a3eacSZhao Chenhui #define CONFIG_PCI_EHCI_DEVICE 0 667863a3eacSZhao Chenhui #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 668863a3eacSZhao Chenhui #endif 669863a3eacSZhao Chenhui 670129ba616SKumar Gala #undef CONFIG_WATCHDOG /* watchdog disabled */ 671129ba616SKumar Gala 672129ba616SKumar Gala /* 673129ba616SKumar Gala * Miscellaneous configurable options 674129ba616SKumar Gala */ 6756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 676129ba616SKumar Gala #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 6775be58f5fSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 6786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 6796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 680129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 6816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 682129ba616SKumar Gala #else 6836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 684129ba616SKumar Gala #endif 6856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 6866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 6876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 6886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 689129ba616SKumar Gala 690129ba616SKumar Gala /* 691129ba616SKumar Gala * For booting Linux, the board info and command line data 692a832ac41SKumar Gala * have to be in the first 64 MB of memory, since this is 693129ba616SKumar Gala * the maximum mapped by the Linux kernel during initialization. 694129ba616SKumar Gala */ 695a832ac41SKumar Gala #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 696a832ac41SKumar Gala #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 697129ba616SKumar Gala 698129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 699129ba616SKumar Gala #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 700129ba616SKumar Gala #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 701129ba616SKumar Gala #endif 702129ba616SKumar Gala 703129ba616SKumar Gala /* 704129ba616SKumar Gala * Environment Configuration 705129ba616SKumar Gala */ 706129ba616SKumar Gala 707129ba616SKumar Gala /* The mac addresses for all ethernet interface */ 708129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 709129ba616SKumar Gala #define CONFIG_HAS_ETH0 710129ba616SKumar Gala #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 711129ba616SKumar Gala #define CONFIG_HAS_ETH1 712129ba616SKumar Gala #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 713129ba616SKumar Gala #define CONFIG_HAS_ETH2 714129ba616SKumar Gala #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 715129ba616SKumar Gala #define CONFIG_HAS_ETH3 716129ba616SKumar Gala #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 717129ba616SKumar Gala #endif 718129ba616SKumar Gala 719129ba616SKumar Gala #define CONFIG_IPADDR 192.168.1.254 720129ba616SKumar Gala 721129ba616SKumar Gala #define CONFIG_HOSTNAME unknown 7228b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/opt/nfsroot" 723b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 724129ba616SKumar Gala #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 725129ba616SKumar Gala 726129ba616SKumar Gala #define CONFIG_SERVERIP 192.168.1.1 727129ba616SKumar Gala #define CONFIG_GATEWAYIP 192.168.1.1 728129ba616SKumar Gala #define CONFIG_NETMASK 255.255.255.0 729129ba616SKumar Gala 730129ba616SKumar Gala /* default location for tftp and bootm */ 731129ba616SKumar Gala #define CONFIG_LOADADDR 1000000 732129ba616SKumar Gala 733129ba616SKumar Gala #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 734129ba616SKumar Gala #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 735129ba616SKumar Gala 736129ba616SKumar Gala #define CONFIG_BAUDRATE 115200 737129ba616SKumar Gala 738129ba616SKumar Gala #define CONFIG_EXTRA_ENV_SETTINGS \ 739238e1467SHongtao Jia "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 740129ba616SKumar Gala "netdev=eth0\0" \ 7415368c55dSMarek Vasut "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 742129ba616SKumar Gala "tftpflash=tftpboot $loadaddr $uboot; " \ 7435368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 7445368c55dSMarek Vasut " +$filesize; " \ 7455368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 7465368c55dSMarek Vasut " +$filesize; " \ 7475368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7485368c55dSMarek Vasut " $filesize; " \ 7495368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 7505368c55dSMarek Vasut " +$filesize; " \ 7515368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7525368c55dSMarek Vasut " $filesize\0" \ 753129ba616SKumar Gala "consoledev=ttyS0\0" \ 754129ba616SKumar Gala "ramdiskaddr=2000000\0" \ 755129ba616SKumar Gala "ramdiskfile=8572ds/ramdisk.uboot\0" \ 756129ba616SKumar Gala "fdtaddr=c00000\0" \ 757129ba616SKumar Gala "fdtfile=8572ds/mpc8572ds.dtb\0" \ 758129ba616SKumar Gala "bdev=sda3\0" 759129ba616SKumar Gala 760129ba616SKumar Gala #define CONFIG_HDBOOT \ 761129ba616SKumar Gala "setenv bootargs root=/dev/$bdev rw " \ 762129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 763129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 764129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 765129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 766129ba616SKumar Gala 767129ba616SKumar Gala #define CONFIG_NFSBOOTCOMMAND \ 768129ba616SKumar Gala "setenv bootargs root=/dev/nfs rw " \ 769129ba616SKumar Gala "nfsroot=$serverip:$rootpath " \ 770129ba616SKumar Gala "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 771129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 772129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 773129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 774129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 775129ba616SKumar Gala 776129ba616SKumar Gala #define CONFIG_RAMBOOTCOMMAND \ 777129ba616SKumar Gala "setenv bootargs root=/dev/ram rw " \ 778129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 779129ba616SKumar Gala "tftp $ramdiskaddr $ramdiskfile;" \ 780129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 781129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 782129ba616SKumar Gala "bootm $loadaddr $ramdiskaddr $fdtaddr" 783129ba616SKumar Gala 784129ba616SKumar Gala #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 785129ba616SKumar Gala 786129ba616SKumar Gala #endif /* __CONFIG_H */ 787