1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2129ba616SKumar Gala /* 37c57f3e8SKumar Gala * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 4129ba616SKumar Gala */ 5129ba616SKumar Gala 6129ba616SKumar Gala /* 7129ba616SKumar Gala * mpc8572ds board configuration file 8129ba616SKumar Gala * 9129ba616SKumar Gala */ 10129ba616SKumar Gala #ifndef __CONFIG_H 11129ba616SKumar Gala #define __CONFIG_H 12129ba616SKumar Gala 13509c4c4cSKumar Gala #include "../board/freescale/common/ics307_clk.h" 14509c4c4cSKumar Gala 157a577fdaSKumar Gala #ifndef CONFIG_RESET_VECTOR_ADDRESS 167a577fdaSKumar Gala #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 177a577fdaSKumar Gala #endif 187a577fdaSKumar Gala 19cb14e93bSKumar Gala #ifndef CONFIG_SYS_MONITOR_BASE 20cb14e93bSKumar Gala #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 21cb14e93bSKumar Gala #endif 22cb14e93bSKumar Gala 23129ba616SKumar Gala /* High Level Configuration Options */ 24129ba616SKumar Gala #define CONFIG_MP 1 /* support multiple processors */ 25129ba616SKumar Gala 26b38eaec5SRobert P. J. Day #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 27b38eaec5SRobert P. J. Day #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 28b38eaec5SRobert P. J. Day #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 29129ba616SKumar Gala #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 30842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 31129ba616SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 320151cbacSKumar Gala #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 33129ba616SKumar Gala 34129ba616SKumar Gala #define CONFIG_ENV_OVERWRITE 35129ba616SKumar Gala 36509c4c4cSKumar Gala #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 37509c4c4cSKumar Gala #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 384ca06607SHaiying Wang #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 39129ba616SKumar Gala 40129ba616SKumar Gala /* 41129ba616SKumar Gala * These can be toggled for performance analysis, otherwise use default. 42129ba616SKumar Gala */ 43129ba616SKumar Gala #define CONFIG_L2_CACHE /* toggle L2 cache */ 44129ba616SKumar Gala #define CONFIG_BTB /* toggle branch predition */ 45129ba616SKumar Gala 46129ba616SKumar Gala #define CONFIG_ENABLE_36BIT_PHYS 1 47129ba616SKumar Gala 4818af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 4918af1c5fSKumar Gala #define CONFIG_ADDR_MAP 1 5018af1c5fSKumar Gala #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 5118af1c5fSKumar Gala #endif 5218af1c5fSKumar Gala 536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x7fffffff 55129ba616SKumar Gala 56129ba616SKumar Gala /* 57cb14e93bSKumar Gala * Config the L2 Cache as L2 SRAM 58cb14e93bSKumar Gala */ 59cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 60cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 61cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 62cb14e93bSKumar Gala #else 63cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 64cb14e93bSKumar Gala #endif 65cb14e93bSKumar Gala #define CONFIG_SYS_L2_SIZE (512 << 10) 66cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 67cb14e93bSKumar Gala 68e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR 0xffe00000 69e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 70129ba616SKumar Gala 718d22ddcaSKumar Gala #if defined(CONFIG_NAND_SPL) 72e46fedfeSTimur Tabi #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 73cb14e93bSKumar Gala #endif 74cb14e93bSKumar Gala 75129ba616SKumar Gala /* DDR Setup */ 76f8523cb0SKumar Gala #define CONFIG_VERY_BIG_RAM 77129ba616SKumar Gala #undef CONFIG_FSL_DDR_INTERACTIVE 78129ba616SKumar Gala #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 79129ba616SKumar Gala #define CONFIG_DDR_SPD 80129ba616SKumar Gala 81d34897d3SYork Sun #define CONFIG_DDR_ECC 829b0ad1b1SDave Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 83129ba616SKumar Gala #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 84129ba616SKumar Gala 856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 87129ba616SKumar Gala 88129ba616SKumar Gala #define CONFIG_DIMM_SLOTS_PER_CTLR 1 89129ba616SKumar Gala #define CONFIG_CHIP_SELECTS_PER_CTRL 2 90129ba616SKumar Gala 91129ba616SKumar Gala /* I2C addresses of SPD EEPROMs */ 926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 93129ba616SKumar Gala #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 94129ba616SKumar Gala #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 95129ba616SKumar Gala 96129ba616SKumar Gala /* These are used when DDR doesn't use SPD. */ 97dc889e86SDave Liu #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 99dc889e86SDave Liu #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 100dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_3 0x00020000 1016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 0x00260802 102dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 103dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 104dc889e86SDave Liu #define CONFIG_SYS_DDR_MODE_1 0x00440462 1056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x00000000 106dc889e86SDave Liu #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 1076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 108dc889e86SDave Liu #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 1096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 1106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 111dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 112dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL2 0x24400000 113129ba616SKumar Gala 1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 1156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 1166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SBE 0x00010000 117129ba616SKumar Gala 118129ba616SKumar Gala /* 119129ba616SKumar Gala * Make sure required options are set 120129ba616SKumar Gala */ 121129ba616SKumar Gala #ifndef CONFIG_SPD_EEPROM 122129ba616SKumar Gala #error ("CONFIG_SPD_EEPROM is required") 123129ba616SKumar Gala #endif 124129ba616SKumar Gala 125129ba616SKumar Gala #undef CONFIG_CLOCKS_IN_MHZ 126129ba616SKumar Gala 127129ba616SKumar Gala /* 128129ba616SKumar Gala * Memory map 129129ba616SKumar Gala * 130129ba616SKumar Gala * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 131129ba616SKumar Gala * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 132129ba616SKumar Gala * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 133129ba616SKumar Gala * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 134129ba616SKumar Gala * 135129ba616SKumar Gala * Localbus cacheable (TBD) 136129ba616SKumar Gala * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 137129ba616SKumar Gala * 138129ba616SKumar Gala * Localbus non-cacheable 139129ba616SKumar Gala * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 140129ba616SKumar Gala * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 141c013b749SHaiying Wang * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 142129ba616SKumar Gala * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 143129ba616SKumar Gala * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 144129ba616SKumar Gala * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 145129ba616SKumar Gala */ 146129ba616SKumar Gala 147129ba616SKumar Gala /* 148129ba616SKumar Gala * Local Bus Definitions 149129ba616SKumar Gala */ 1506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 15118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 15218af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 15318af1c5fSKumar Gala #else 154c953ddfdSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 15518af1c5fSKumar Gala #endif 156129ba616SKumar Gala 157cb14e93bSKumar Gala #define CONFIG_FLASH_BR_PRELIM \ 1587ee41107STimur Tabi (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 159cb14e93bSKumar Gala #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 160129ba616SKumar Gala 161c953ddfdSKumar Gala #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 1626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 163129ba616SKumar Gala 16418af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 1656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 166129ba616SKumar Gala #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 167129ba616SKumar Gala 1686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 1696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 1706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CHECKSUM 1716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 1726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 173129ba616SKumar Gala 174cb14e93bSKumar Gala #undef CONFIG_SYS_RAMBOOT 175129ba616SKumar Gala 176129ba616SKumar Gala #define CONFIG_FLASH_CFI_DRIVER 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 1786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 1796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 180129ba616SKumar Gala 181558710b9SKumar Gala #define CONFIG_HWCONFIG /* enable hwconfig */ 182129ba616SKumar Gala #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 183129ba616SKumar Gala #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 18418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 18518af1c5fSKumar Gala #define PIXIS_BASE_PHYS 0xfffdf0000ull 18618af1c5fSKumar Gala #else 18752b565f5SKumar Gala #define PIXIS_BASE_PHYS PIXIS_BASE 18818af1c5fSKumar Gala #endif 189129ba616SKumar Gala 19052b565f5SKumar Gala #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 1916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 192129ba616SKumar Gala 193129ba616SKumar Gala #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 194129ba616SKumar Gala #define PIXIS_VER 0x1 /* Board version at offset 1 */ 195129ba616SKumar Gala #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 196129ba616SKumar Gala #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 197129ba616SKumar Gala #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 198129ba616SKumar Gala #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 199129ba616SKumar Gala #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 200129ba616SKumar Gala #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 201129ba616SKumar Gala #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 202129ba616SKumar Gala #define PIXIS_VCTL 0x10 /* VELA Control Register */ 203129ba616SKumar Gala #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 204129ba616SKumar Gala #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 205129ba616SKumar Gala #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 206129ba616SKumar Gala #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 207129ba616SKumar Gala #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 2086bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 2096bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 2106bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 2116bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 2126bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 213129ba616SKumar Gala #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 214129ba616SKumar Gala #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 215129ba616SKumar Gala #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 216129ba616SKumar Gala #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 217129ba616SKumar Gala #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 218129ba616SKumar Gala #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 219129ba616SKumar Gala #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 220129ba616SKumar Gala #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 221129ba616SKumar Gala #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 222129ba616SKumar Gala #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 223129ba616SKumar Gala #define PIXIS_LED 0x25 /* LED Register */ 224129ba616SKumar Gala 225cb14e93bSKumar Gala #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 226cb14e93bSKumar Gala 227129ba616SKumar Gala /* old pixis referenced names */ 228129ba616SKumar Gala #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 229129ba616SKumar Gala #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 2306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 2317e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC1SER 0x8 2327e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC2SER 0x4 2337e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC3SER 0x2 2347e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC4SER 0x1 2357e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC1SER 0x20 2367e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC2SER 0x20 2377e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC3SER 0x20 2387e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC4SER 0x20 2397e183cadSLiu Yu #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 2407e183cadSLiu Yu | PIXIS_VSPEED2_TSEC2SER \ 2417e183cadSLiu Yu | PIXIS_VSPEED2_TSEC3SER \ 2427e183cadSLiu Yu | PIXIS_VSPEED2_TSEC4SER) 2437e183cadSLiu Yu #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 2447e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC2SER \ 2457e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC3SER \ 2467e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC4SER) 247129ba616SKumar Gala 2486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 2496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 250553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 251129ba616SKumar Gala 25225ddd1fbSWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 254129ba616SKumar Gala 2556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 2566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 257129ba616SKumar Gala 258cb14e93bSKumar Gala #ifndef CONFIG_NAND_SPL 259c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE 0xffa00000 26018af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 26118af1c5fSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 26218af1c5fSKumar Gala #else 263c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 26418af1c5fSKumar Gala #endif 265cb14e93bSKumar Gala #else 266cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE 0xfff00000 267cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 268cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 269cb14e93bSKumar Gala #else 270cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 271cb14e93bSKumar Gala #endif 272cb14e93bSKumar Gala #endif 273cb14e93bSKumar Gala 274c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 275c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x40000, \ 276c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x80000,\ 277c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0xC0000} 278c013b749SHaiying Wang #define CONFIG_SYS_MAX_NAND_DEVICE 4 279c013b749SHaiying Wang #define CONFIG_NAND_FSL_ELBC 1 280c013b749SHaiying Wang #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 28168ec9c85SPrabhakar Kushwaha #define CONFIG_SYS_NAND_MAX_OOBFREE 5 28268ec9c85SPrabhakar Kushwaha #define CONFIG_SYS_NAND_MAX_ECCPOS 56 283c013b749SHaiying Wang 284cb14e93bSKumar Gala /* NAND boot: 4K NAND loader config */ 285cb14e93bSKumar Gala #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 286cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 287cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 288cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_START \ 289cb14e93bSKumar Gala (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 290cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 291cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 292cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 293cb14e93bSKumar Gala 294c013b749SHaiying Wang /* NAND flash config */ 295a3055c58SMatthew McClintock #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 296c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 297c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 298c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 299c013b749SHaiying Wang | BR_V) /* valid */ 300a3055c58SMatthew McClintock #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 301c013b749SHaiying Wang | OR_FCM_PGS /* Large Page*/ \ 302c013b749SHaiying Wang | OR_FCM_CSCT \ 303c013b749SHaiying Wang | OR_FCM_CST \ 304c013b749SHaiying Wang | OR_FCM_CHT \ 305c013b749SHaiying Wang | OR_FCM_SCY_1 \ 306c013b749SHaiying Wang | OR_FCM_TRLX \ 307c013b749SHaiying Wang | OR_FCM_EHTR) 308c013b749SHaiying Wang 309cb14e93bSKumar Gala #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 310cb14e93bSKumar Gala #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 311a3055c58SMatthew McClintock #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 312a3055c58SMatthew McClintock #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 3137ee41107STimur Tabi #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 314c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 315c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 316c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 317c013b749SHaiying Wang | BR_V) /* valid */ 318a3055c58SMatthew McClintock #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 3197ee41107STimur Tabi #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 320c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 321c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 322c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 323c013b749SHaiying Wang | BR_V) /* valid */ 324a3055c58SMatthew McClintock #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 325c013b749SHaiying Wang 3267ee41107STimur Tabi #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 327c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 328c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 329c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 330c013b749SHaiying Wang | BR_V) /* valid */ 331a3055c58SMatthew McClintock #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 332c013b749SHaiying Wang 333129ba616SKumar Gala /* Serial Port - controlled on board with jumper J8 334129ba616SKumar Gala * open - index 2 335129ba616SKumar Gala * shorted - index 1 336129ba616SKumar Gala */ 3376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 340cb14e93bSKumar Gala #ifdef CONFIG_NAND_SPL 341cb14e93bSKumar Gala #define CONFIG_NS16550_MIN_FUNCTIONS 342cb14e93bSKumar Gala #endif 343129ba616SKumar Gala 3446d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 345129ba616SKumar Gala {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 346129ba616SKumar Gala 3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 349129ba616SKumar Gala 350129ba616SKumar Gala /* I2C */ 35100f792e0SHeiko Schocher #define CONFIG_SYS_I2C 35200f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 35300f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 35400f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 35500f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 35600f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 35700f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 35800f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 35900f792e0SHeiko Schocher #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 3606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 361129ba616SKumar Gala 362129ba616SKumar Gala /* 363445a7b38SHaiying Wang * I2C2 EEPROM 364445a7b38SHaiying Wang */ 365445a7b38SHaiying Wang #define CONFIG_ID_EEPROM 366445a7b38SHaiying Wang #ifdef CONFIG_ID_EEPROM 3676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_NXID 368445a7b38SHaiying Wang #endif 3696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 3706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 3716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_EEPROM_BUS_NUM 1 372445a7b38SHaiying Wang 373445a7b38SHaiying Wang /* 374129ba616SKumar Gala * General PCI 375129ba616SKumar Gala * Memory space is mapped 1-1, but I/O space must start from 0. 376129ba616SKumar Gala */ 377129ba616SKumar Gala 378129ba616SKumar Gala /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 37918ea5551SKumar Gala #define CONFIG_SYS_PCIE3_NAME "ULI" 3805af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 38118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 382156984a3SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 38318af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 38418af1c5fSKumar Gala #else 385ad97dce1SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 3865af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 38718af1c5fSKumar Gala #endif 3886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 389aca5f018SKumar Gala #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 3905f91ef6aSKumar Gala #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 39118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 39218af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 39318af1c5fSKumar Gala #else 3946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 39518af1c5fSKumar Gala #endif 3966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 397129ba616SKumar Gala 398129ba616SKumar Gala /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 39918ea5551SKumar Gala #define CONFIG_SYS_PCIE2_NAME "Slot 1" 4005af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 40118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 402156984a3SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 40318af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 40418af1c5fSKumar Gala #else 405ad97dce1SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 4065af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 40718af1c5fSKumar Gala #endif 4086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 409aca5f018SKumar Gala #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 4105f91ef6aSKumar Gala #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 41118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 41218af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 41318af1c5fSKumar Gala #else 4146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 41518af1c5fSKumar Gala #endif 4166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 417129ba616SKumar Gala 418129ba616SKumar Gala /* controller 1, Slot 1, tgtid 1, Base address a000 */ 41918ea5551SKumar Gala #define CONFIG_SYS_PCIE1_NAME "Slot 2" 4205af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 42118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 422156984a3SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 42318af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 42418af1c5fSKumar Gala #else 425ad97dce1SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 4265af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 42718af1c5fSKumar Gala #endif 4286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 429aca5f018SKumar Gala #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 4305f91ef6aSKumar Gala #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 43118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 43218af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 43318af1c5fSKumar Gala #else 4346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 43518af1c5fSKumar Gala #endif 4366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 437129ba616SKumar Gala 438129ba616SKumar Gala #if defined(CONFIG_PCI) 439129ba616SKumar Gala 440129ba616SKumar Gala /*PCIE video card used*/ 441aca5f018SKumar Gala #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 442129ba616SKumar Gala 443129ba616SKumar Gala /* video */ 444129ba616SKumar Gala 445129ba616SKumar Gala #if defined(CONFIG_VIDEO) 446129ba616SKumar Gala #define CONFIG_BIOSEMU 447129ba616SKumar Gala #define CONFIG_ATI_RADEON_FB 448129ba616SKumar Gala #define CONFIG_VIDEO_LOGO 4496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 450129ba616SKumar Gala #endif 451129ba616SKumar Gala 452129ba616SKumar Gala #undef CONFIG_EEPRO100 453129ba616SKumar Gala #undef CONFIG_TULIP 454129ba616SKumar Gala 455129ba616SKumar Gala #ifndef CONFIG_PCI_PNP 4565f91ef6aSKumar Gala #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 4575f91ef6aSKumar Gala #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 458129ba616SKumar Gala #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 459129ba616SKumar Gala #endif 460129ba616SKumar Gala 461129ba616SKumar Gala #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 462129ba616SKumar Gala 463129ba616SKumar Gala #ifdef CONFIG_SCSI_AHCI 464129ba616SKumar Gala #define CONFIG_SATA_ULI5288 4656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 4666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_LUN 1 4676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 4686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 469129ba616SKumar Gala #endif /* SCSI */ 470129ba616SKumar Gala 471129ba616SKumar Gala #endif /* CONFIG_PCI */ 472129ba616SKumar Gala 473129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 474129ba616SKumar Gala 475129ba616SKumar Gala #define CONFIG_MII 1 /* MII PHY management */ 476129ba616SKumar Gala #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 477129ba616SKumar Gala #define CONFIG_TSEC1 1 478129ba616SKumar Gala #define CONFIG_TSEC1_NAME "eTSEC1" 479129ba616SKumar Gala #define CONFIG_TSEC2 1 480129ba616SKumar Gala #define CONFIG_TSEC2_NAME "eTSEC2" 481129ba616SKumar Gala #define CONFIG_TSEC3 1 482129ba616SKumar Gala #define CONFIG_TSEC3_NAME "eTSEC3" 483129ba616SKumar Gala #define CONFIG_TSEC4 1 484129ba616SKumar Gala #define CONFIG_TSEC4_NAME "eTSEC4" 485129ba616SKumar Gala 4867e183cadSLiu Yu #define CONFIG_PIXIS_SGMII_CMD 4877e183cadSLiu Yu #define CONFIG_FSL_SGMII_RISER 1 4887e183cadSLiu Yu #define SGMII_RISER_PHY_OFFSET 0x1c 4897e183cadSLiu Yu 4907e183cadSLiu Yu #ifdef CONFIG_FSL_SGMII_RISER 4917e183cadSLiu Yu #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 4927e183cadSLiu Yu #endif 4937e183cadSLiu Yu 494129ba616SKumar Gala #define TSEC1_PHY_ADDR 0 495129ba616SKumar Gala #define TSEC2_PHY_ADDR 1 496129ba616SKumar Gala #define TSEC3_PHY_ADDR 2 497129ba616SKumar Gala #define TSEC4_PHY_ADDR 3 498129ba616SKumar Gala 499129ba616SKumar Gala #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 500129ba616SKumar Gala #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 501129ba616SKumar Gala #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 502129ba616SKumar Gala #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 503129ba616SKumar Gala 504129ba616SKumar Gala #define TSEC1_PHYIDX 0 505129ba616SKumar Gala #define TSEC2_PHYIDX 0 506129ba616SKumar Gala #define TSEC3_PHYIDX 0 507129ba616SKumar Gala #define TSEC4_PHYIDX 0 508129ba616SKumar Gala 509129ba616SKumar Gala #define CONFIG_ETHPRIME "eTSEC1" 510129ba616SKumar Gala #endif /* CONFIG_TSEC_ENET */ 511129ba616SKumar Gala 512129ba616SKumar Gala /* 513129ba616SKumar Gala * Environment 514129ba616SKumar Gala */ 515cb14e93bSKumar Gala 516cb14e93bSKumar Gala #if defined(CONFIG_SYS_RAMBOOT) 517cb14e93bSKumar Gala 518cb14e93bSKumar Gala #else 5196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 5200e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR 0xfff80000 521129ba616SKumar Gala #else 5226fc110bdSHaiying Wang #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 523129ba616SKumar Gala #endif 5240e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 5250e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 526cb14e93bSKumar Gala #endif 527129ba616SKumar Gala 528129ba616SKumar Gala #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 5296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 530129ba616SKumar Gala 531129ba616SKumar Gala /* 532863a3eacSZhao Chenhui * USB 533863a3eacSZhao Chenhui */ 534863a3eacSZhao Chenhui 5358850c5d5STom Rini #ifdef CONFIG_USB_EHCI_HCD 536863a3eacSZhao Chenhui #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 537863a3eacSZhao Chenhui #define CONFIG_PCI_EHCI_DEVICE 0 538863a3eacSZhao Chenhui #endif 539863a3eacSZhao Chenhui 540129ba616SKumar Gala #undef CONFIG_WATCHDOG /* watchdog disabled */ 541129ba616SKumar Gala 542129ba616SKumar Gala /* 543129ba616SKumar Gala * Miscellaneous configurable options 544129ba616SKumar Gala */ 5456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 546129ba616SKumar Gala 547129ba616SKumar Gala /* 548129ba616SKumar Gala * For booting Linux, the board info and command line data 549a832ac41SKumar Gala * have to be in the first 64 MB of memory, since this is 550129ba616SKumar Gala * the maximum mapped by the Linux kernel during initialization. 551129ba616SKumar Gala */ 552a832ac41SKumar Gala #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 553a832ac41SKumar Gala #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 554129ba616SKumar Gala 555129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 556129ba616SKumar Gala #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 557129ba616SKumar Gala #endif 558129ba616SKumar Gala 559129ba616SKumar Gala /* 560129ba616SKumar Gala * Environment Configuration 561129ba616SKumar Gala */ 562129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 563129ba616SKumar Gala #define CONFIG_HAS_ETH0 564129ba616SKumar Gala #define CONFIG_HAS_ETH1 565129ba616SKumar Gala #define CONFIG_HAS_ETH2 566129ba616SKumar Gala #define CONFIG_HAS_ETH3 567129ba616SKumar Gala #endif 568129ba616SKumar Gala 569129ba616SKumar Gala #define CONFIG_IPADDR 192.168.1.254 570129ba616SKumar Gala 5715bc0543dSMario Six #define CONFIG_HOSTNAME "unknown" 5728b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/opt/nfsroot" 573b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 574129ba616SKumar Gala #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 575129ba616SKumar Gala 576129ba616SKumar Gala #define CONFIG_SERVERIP 192.168.1.1 577129ba616SKumar Gala #define CONFIG_GATEWAYIP 192.168.1.1 578129ba616SKumar Gala #define CONFIG_NETMASK 255.255.255.0 579129ba616SKumar Gala 580129ba616SKumar Gala /* default location for tftp and bootm */ 581129ba616SKumar Gala #define CONFIG_LOADADDR 1000000 582129ba616SKumar Gala 583129ba616SKumar Gala #define CONFIG_EXTRA_ENV_SETTINGS \ 584238e1467SHongtao Jia "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 585129ba616SKumar Gala "netdev=eth0\0" \ 5865368c55dSMarek Vasut "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 587129ba616SKumar Gala "tftpflash=tftpboot $loadaddr $uboot; " \ 5885368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 5895368c55dSMarek Vasut " +$filesize; " \ 5905368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 5915368c55dSMarek Vasut " +$filesize; " \ 5925368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 5935368c55dSMarek Vasut " $filesize; " \ 5945368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 5955368c55dSMarek Vasut " +$filesize; " \ 5965368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 5975368c55dSMarek Vasut " $filesize\0" \ 598129ba616SKumar Gala "consoledev=ttyS0\0" \ 599129ba616SKumar Gala "ramdiskaddr=2000000\0" \ 600129ba616SKumar Gala "ramdiskfile=8572ds/ramdisk.uboot\0" \ 601b24a4f62SScott Wood "fdtaddr=1e00000\0" \ 602129ba616SKumar Gala "fdtfile=8572ds/mpc8572ds.dtb\0" \ 603129ba616SKumar Gala "bdev=sda3\0" 604129ba616SKumar Gala 605129ba616SKumar Gala #define CONFIG_HDBOOT \ 606129ba616SKumar Gala "setenv bootargs root=/dev/$bdev rw " \ 607129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 608129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 609129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 610129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 611129ba616SKumar Gala 612129ba616SKumar Gala #define CONFIG_NFSBOOTCOMMAND \ 613129ba616SKumar Gala "setenv bootargs root=/dev/nfs rw " \ 614129ba616SKumar Gala "nfsroot=$serverip:$rootpath " \ 615129ba616SKumar Gala "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 616129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 617129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 618129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 619129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 620129ba616SKumar Gala 621129ba616SKumar Gala #define CONFIG_RAMBOOTCOMMAND \ 622129ba616SKumar Gala "setenv bootargs root=/dev/ram rw " \ 623129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 624129ba616SKumar Gala "tftp $ramdiskaddr $ramdiskfile;" \ 625129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 626129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 627129ba616SKumar Gala "bootm $loadaddr $ramdiskaddr $fdtaddr" 628129ba616SKumar Gala 629129ba616SKumar Gala #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 630129ba616SKumar Gala 631129ba616SKumar Gala #endif /* __CONFIG_H */ 632