1129ba616SKumar Gala /* 2129ba616SKumar Gala * Copyright 2007-2008 Freescale Semiconductor, Inc. 3129ba616SKumar Gala * 4129ba616SKumar Gala * See file CREDITS for list of people who contributed to this 5129ba616SKumar Gala * project. 6129ba616SKumar Gala * 7129ba616SKumar Gala * This program is free software; you can redistribute it and/or 8129ba616SKumar Gala * modify it under the terms of the GNU General Public License as 9129ba616SKumar Gala * published by the Free Software Foundation; either version 2 of 10129ba616SKumar Gala * the License, or (at your option) any later version. 11129ba616SKumar Gala * 12129ba616SKumar Gala * This program is distributed in the hope that it will be useful, 13129ba616SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 14129ba616SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15129ba616SKumar Gala * GNU General Public License for more details. 16129ba616SKumar Gala * 17129ba616SKumar Gala * You should have received a copy of the GNU General Public License 18129ba616SKumar Gala * along with this program; if not, write to the Free Software 19129ba616SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20129ba616SKumar Gala * MA 02111-1307 USA 21129ba616SKumar Gala */ 22129ba616SKumar Gala 23129ba616SKumar Gala /* 24129ba616SKumar Gala * mpc8572ds board configuration file 25129ba616SKumar Gala * 26129ba616SKumar Gala */ 27129ba616SKumar Gala #ifndef __CONFIG_H 28129ba616SKumar Gala #define __CONFIG_H 29129ba616SKumar Gala 30129ba616SKumar Gala /* High Level Configuration Options */ 31129ba616SKumar Gala #define CONFIG_BOOKE 1 /* BOOKE */ 32129ba616SKumar Gala #define CONFIG_E500 1 /* BOOKE e500 family */ 33129ba616SKumar Gala #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34129ba616SKumar Gala #define CONFIG_MPC8572 1 35129ba616SKumar Gala #define CONFIG_MPC8572DS 1 36129ba616SKumar Gala #define CONFIG_MP 1 /* support multiple processors */ 37129ba616SKumar Gala #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 38129ba616SKumar Gala 39129ba616SKumar Gala #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 40129ba616SKumar Gala #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 41129ba616SKumar Gala #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 42129ba616SKumar Gala #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 43129ba616SKumar Gala #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 44129ba616SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 45129ba616SKumar Gala 46129ba616SKumar Gala #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 47129ba616SKumar Gala 48129ba616SKumar Gala #define CONFIG_TSEC_ENET /* tsec ethernet support */ 49129ba616SKumar Gala #define CONFIG_ENV_OVERWRITE 50129ba616SKumar Gala 51129ba616SKumar Gala /* 52129ba616SKumar Gala * When initializing flash, if we cannot find the manufacturer ID, 53129ba616SKumar Gala * assume this is the AMD flash associated with the CDS board. 54129ba616SKumar Gala * This allows booting from a promjet. 55129ba616SKumar Gala */ 56129ba616SKumar Gala #define CONFIG_ASSUME_AMD_FLASH 57129ba616SKumar Gala 58129ba616SKumar Gala #ifndef __ASSEMBLY__ 59129ba616SKumar Gala extern unsigned long get_board_sys_clk(unsigned long dummy); 60129ba616SKumar Gala extern unsigned long get_board_ddr_clk(unsigned long dummy); 61129ba616SKumar Gala #endif 62129ba616SKumar Gala #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 63129ba616SKumar Gala #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 64129ba616SKumar Gala #define CONFIG_ICS307_REFCLK_HZ 33333333 /* ICS307 clock chip ref freq */ 65129ba616SKumar Gala #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 66129ba616SKumar Gala from ICS307 instead of switches */ 67129ba616SKumar Gala 68129ba616SKumar Gala /* 69129ba616SKumar Gala * These can be toggled for performance analysis, otherwise use default. 70129ba616SKumar Gala */ 71129ba616SKumar Gala #define CONFIG_L2_CACHE /* toggle L2 cache */ 72129ba616SKumar Gala #define CONFIG_BTB /* toggle branch predition */ 73129ba616SKumar Gala #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 74129ba616SKumar Gala 75129ba616SKumar Gala #define CONFIG_ENABLE_36BIT_PHYS 1 76129ba616SKumar Gala 77*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 78*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x7fffffff 79129ba616SKumar Gala #define CONFIG_PANIC_HANG /* do not reset board on panic */ 80129ba616SKumar Gala 81129ba616SKumar Gala /* 82129ba616SKumar Gala * Base addresses -- Note these are effective addresses where the 83129ba616SKumar Gala * actual resources get mapped (not physical addresses) 84129ba616SKumar Gala */ 85*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 86*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 87*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 88*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 89129ba616SKumar Gala 90*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 91*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 92*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 93129ba616SKumar Gala 94129ba616SKumar Gala /* DDR Setup */ 95129ba616SKumar Gala #define CONFIG_FSL_DDR2 96129ba616SKumar Gala #undef CONFIG_FSL_DDR_INTERACTIVE 97129ba616SKumar Gala #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 98129ba616SKumar Gala #define CONFIG_DDR_SPD 99129ba616SKumar Gala #undef CONFIG_DDR_DLL 100129ba616SKumar Gala 101129ba616SKumar Gala #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 102129ba616SKumar Gala 103*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 104*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 105129ba616SKumar Gala 106129ba616SKumar Gala #define CONFIG_NUM_DDR_CONTROLLERS 2 107129ba616SKumar Gala #define CONFIG_DIMM_SLOTS_PER_CTLR 1 108129ba616SKumar Gala #define CONFIG_CHIP_SELECTS_PER_CTRL 2 109129ba616SKumar Gala 110129ba616SKumar Gala /* I2C addresses of SPD EEPROMs */ 111*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 112129ba616SKumar Gala #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 113129ba616SKumar Gala #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 114129ba616SKumar Gala 115129ba616SKumar Gala /* These are used when DDR doesn't use SPD. */ 116*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ 117*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 118*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 119*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_3 0x00000000 120*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 0x00260802 121*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 122*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 123*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_1 0x00480432 124*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x00000000 125*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_INTERVAL 0x06180100 126*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 127*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 128*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 129*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 130*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 131*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CONTROL2 0x04400010 132129ba616SKumar Gala 133*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 134*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 135*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SBE 0x00010000 136129ba616SKumar Gala 137129ba616SKumar Gala /* 138129ba616SKumar Gala * FIXME: Not used in fixed_sdram function 139129ba616SKumar Gala */ 140*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE 0x00000022 141*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 142*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS2_BNDS 0x00000FFF /* Not done */ 143*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS3_BNDS 0x00000FFF /* Not done */ 144*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS4_BNDS 0x00000FFF /* Not done */ 145*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS5_BNDS 0x00000FFF /* Not done */ 146129ba616SKumar Gala 147129ba616SKumar Gala /* 148129ba616SKumar Gala * Make sure required options are set 149129ba616SKumar Gala */ 150129ba616SKumar Gala #ifndef CONFIG_SPD_EEPROM 151129ba616SKumar Gala #error ("CONFIG_SPD_EEPROM is required") 152129ba616SKumar Gala #endif 153129ba616SKumar Gala 154129ba616SKumar Gala #undef CONFIG_CLOCKS_IN_MHZ 155129ba616SKumar Gala 156129ba616SKumar Gala /* 157129ba616SKumar Gala * Memory map 158129ba616SKumar Gala * 159129ba616SKumar Gala * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 160129ba616SKumar Gala * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 161129ba616SKumar Gala * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 162129ba616SKumar Gala * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 163129ba616SKumar Gala * 164129ba616SKumar Gala * Localbus cacheable (TBD) 165129ba616SKumar Gala * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 166129ba616SKumar Gala * 167129ba616SKumar Gala * Localbus non-cacheable 168129ba616SKumar Gala * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 169129ba616SKumar Gala * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 170129ba616SKumar Gala * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 171129ba616SKumar Gala * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 172129ba616SKumar Gala * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 173129ba616SKumar Gala */ 174129ba616SKumar Gala 175129ba616SKumar Gala /* 176129ba616SKumar Gala * Local Bus Definitions 177129ba616SKumar Gala */ 178*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 179129ba616SKumar Gala 180*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR0_PRELIM 0xe8001001 181*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 182129ba616SKumar Gala 183*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR1_PRELIM 0xe0001001 184*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 185129ba616SKumar Gala 186*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} 187*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 188129ba616SKumar Gala #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 189129ba616SKumar Gala 190*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 191*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 192*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CHECKSUM 193*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 194*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 195129ba616SKumar Gala 196*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 197129ba616SKumar Gala 198129ba616SKumar Gala #define CONFIG_FLASH_CFI_DRIVER 199*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 200*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 201*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 202129ba616SKumar Gala 203129ba616SKumar Gala #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 204129ba616SKumar Gala 205129ba616SKumar Gala #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 206129ba616SKumar Gala #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 207129ba616SKumar Gala 208*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ 209*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 210129ba616SKumar Gala 211129ba616SKumar Gala #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 212129ba616SKumar Gala #define PIXIS_VER 0x1 /* Board version at offset 1 */ 213129ba616SKumar Gala #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 214129ba616SKumar Gala #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 215129ba616SKumar Gala #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 216129ba616SKumar Gala #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 217129ba616SKumar Gala #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 218129ba616SKumar Gala #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 219129ba616SKumar Gala #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 220129ba616SKumar Gala #define PIXIS_VCTL 0x10 /* VELA Control Register */ 221129ba616SKumar Gala #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 222129ba616SKumar Gala #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 223129ba616SKumar Gala #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 224129ba616SKumar Gala #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 225129ba616SKumar Gala #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 226129ba616SKumar Gala #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 227129ba616SKumar Gala #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 228129ba616SKumar Gala #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 229129ba616SKumar Gala #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 230129ba616SKumar Gala #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 231129ba616SKumar Gala #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 232129ba616SKumar Gala #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 233129ba616SKumar Gala #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 234129ba616SKumar Gala #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 235129ba616SKumar Gala #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 236129ba616SKumar Gala #define PIXIS_LED 0x25 /* LED Register */ 237129ba616SKumar Gala 238129ba616SKumar Gala /* old pixis referenced names */ 239129ba616SKumar Gala #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 240129ba616SKumar Gala #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 241*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 242129ba616SKumar Gala 243129ba616SKumar Gala /* define to use L1 as initial stack */ 244129ba616SKumar Gala #define CONFIG_L1_INIT_RAM 245*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 246*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 247*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 248129ba616SKumar Gala 249*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 250*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 251*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 252129ba616SKumar Gala 253*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 254*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 255129ba616SKumar Gala 256129ba616SKumar Gala /* Serial Port - controlled on board with jumper J8 257129ba616SKumar Gala * open - index 2 258129ba616SKumar Gala * shorted - index 1 259129ba616SKumar Gala */ 260129ba616SKumar Gala #define CONFIG_CONS_INDEX 1 261129ba616SKumar Gala #undef CONFIG_SERIAL_SOFTWARE_FIFO 262*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 263*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 264*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 265*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 266129ba616SKumar Gala 267*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 268129ba616SKumar Gala {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 269129ba616SKumar Gala 270*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 271*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 272129ba616SKumar Gala 273129ba616SKumar Gala /* Use the HUSH parser */ 274*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 275*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_HUSH_PARSER 276*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 277129ba616SKumar Gala #endif 278129ba616SKumar Gala 279129ba616SKumar Gala /* 280129ba616SKumar Gala * Pass open firmware flat tree 281129ba616SKumar Gala */ 282129ba616SKumar Gala #define CONFIG_OF_LIBFDT 1 283129ba616SKumar Gala #define CONFIG_OF_BOARD_SETUP 1 284129ba616SKumar Gala #define CONFIG_OF_STDOUT_VIA_ALIAS 1 285129ba616SKumar Gala 286*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_64BIT_VSPRINTF 1 287*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_64BIT_STRTOUL 1 288129ba616SKumar Gala 289129ba616SKumar Gala /* new uImage format support */ 290129ba616SKumar Gala #define CONFIG_FIT 1 291129ba616SKumar Gala #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 292129ba616SKumar Gala 293129ba616SKumar Gala /* I2C */ 294129ba616SKumar Gala #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 295129ba616SKumar Gala #define CONFIG_HARD_I2C /* I2C with hardware support */ 296129ba616SKumar Gala #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 2971f3ba317SHaiying Wang #define CONFIG_I2C_MULTI_BUS 2981f3ba317SHaiying Wang #define CONFIG_I2C_CMD_TREE 299*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 300*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 301*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 302*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 303*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 304*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 305129ba616SKumar Gala 306129ba616SKumar Gala /* 307445a7b38SHaiying Wang * I2C2 EEPROM 308445a7b38SHaiying Wang */ 309445a7b38SHaiying Wang #define CONFIG_ID_EEPROM 310445a7b38SHaiying Wang #ifdef CONFIG_ID_EEPROM 311*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_NXID 312445a7b38SHaiying Wang #endif 313*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 314*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 315*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_EEPROM_BUS_NUM 1 316445a7b38SHaiying Wang 317445a7b38SHaiying Wang /* 318129ba616SKumar Gala * General PCI 319129ba616SKumar Gala * Memory space is mapped 1-1, but I/O space must start from 0. 320129ba616SKumar Gala */ 321129ba616SKumar Gala 322129ba616SKumar Gala /* PCI view of System Memory */ 323*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000 324*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000 325*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000 326129ba616SKumar Gala 327129ba616SKumar Gala /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 328*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_BASE 0x80000000 329*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE 330*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 331*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 332*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 333*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 334129ba616SKumar Gala 335129ba616SKumar Gala /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 336*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_BASE 0xa0000000 337*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE 338*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 339*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 340*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 341*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 342129ba616SKumar Gala 343129ba616SKumar Gala /* controller 1, Slot 1, tgtid 1, Base address a000 */ 344*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000 345*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE 346*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 347*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 348*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 349*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 350129ba616SKumar Gala 351129ba616SKumar Gala #if defined(CONFIG_PCI) 352129ba616SKumar Gala 353129ba616SKumar Gala /*PCIE video card used*/ 354*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_PHYS 355129ba616SKumar Gala 356129ba616SKumar Gala /* video */ 357129ba616SKumar Gala #define CONFIG_VIDEO 358129ba616SKumar Gala 359129ba616SKumar Gala #if defined(CONFIG_VIDEO) 360129ba616SKumar Gala #define CONFIG_BIOSEMU 361129ba616SKumar Gala #define CONFIG_CFB_CONSOLE 362129ba616SKumar Gala #define CONFIG_VIDEO_SW_CURSOR 363129ba616SKumar Gala #define CONFIG_VGA_AS_SINGLE_DEVICE 364129ba616SKumar Gala #define CONFIG_ATI_RADEON_FB 365129ba616SKumar Gala #define CONFIG_VIDEO_LOGO 366129ba616SKumar Gala /*#define CONFIG_CONSOLE_CURSOR*/ 367*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 368129ba616SKumar Gala #endif 369129ba616SKumar Gala 370129ba616SKumar Gala #define CONFIG_NET_MULTI 371129ba616SKumar Gala #define CONFIG_PCI_PNP /* do pci plug-and-play */ 372129ba616SKumar Gala 373129ba616SKumar Gala #undef CONFIG_EEPRO100 374129ba616SKumar Gala #undef CONFIG_TULIP 375129ba616SKumar Gala #undef CONFIG_RTL8139 376129ba616SKumar Gala 377129ba616SKumar Gala #ifdef CONFIG_RTL8139 378129ba616SKumar Gala /* This macro is used by RTL8139 but not defined in PPC architecture */ 379129ba616SKumar Gala #define KSEG1ADDR(x) (x) 380129ba616SKumar Gala #define _IO_BASE 0x00000000 381129ba616SKumar Gala #endif 382129ba616SKumar Gala 383129ba616SKumar Gala #ifndef CONFIG_PCI_PNP 384*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BASE 385*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BASE 386129ba616SKumar Gala #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 387129ba616SKumar Gala #endif 388129ba616SKumar Gala 389129ba616SKumar Gala #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 390129ba616SKumar Gala #define CONFIG_DOS_PARTITION 391129ba616SKumar Gala #define CONFIG_SCSI_AHCI 392129ba616SKumar Gala 393129ba616SKumar Gala #ifdef CONFIG_SCSI_AHCI 394129ba616SKumar Gala #define CONFIG_SATA_ULI5288 395*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 396*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_LUN 1 397*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 398*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 399129ba616SKumar Gala #endif /* SCSI */ 400129ba616SKumar Gala 401129ba616SKumar Gala #endif /* CONFIG_PCI */ 402129ba616SKumar Gala 403129ba616SKumar Gala 404129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 405129ba616SKumar Gala 406129ba616SKumar Gala #ifndef CONFIG_NET_MULTI 407129ba616SKumar Gala #define CONFIG_NET_MULTI 1 408129ba616SKumar Gala #endif 409129ba616SKumar Gala 410129ba616SKumar Gala #define CONFIG_MII 1 /* MII PHY management */ 411129ba616SKumar Gala #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 412129ba616SKumar Gala #define CONFIG_TSEC1 1 413129ba616SKumar Gala #define CONFIG_TSEC1_NAME "eTSEC1" 414129ba616SKumar Gala #define CONFIG_TSEC2 1 415129ba616SKumar Gala #define CONFIG_TSEC2_NAME "eTSEC2" 416129ba616SKumar Gala #define CONFIG_TSEC3 1 417129ba616SKumar Gala #define CONFIG_TSEC3_NAME "eTSEC3" 418129ba616SKumar Gala #define CONFIG_TSEC4 1 419129ba616SKumar Gala #define CONFIG_TSEC4_NAME "eTSEC4" 420129ba616SKumar Gala 421129ba616SKumar Gala #define TSEC1_PHY_ADDR 0 422129ba616SKumar Gala #define TSEC2_PHY_ADDR 1 423129ba616SKumar Gala #define TSEC3_PHY_ADDR 2 424129ba616SKumar Gala #define TSEC4_PHY_ADDR 3 425129ba616SKumar Gala 426129ba616SKumar Gala #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 427129ba616SKumar Gala #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 428129ba616SKumar Gala #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 429129ba616SKumar Gala #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 430129ba616SKumar Gala 431129ba616SKumar Gala #define TSEC1_PHYIDX 0 432129ba616SKumar Gala #define TSEC2_PHYIDX 0 433129ba616SKumar Gala #define TSEC3_PHYIDX 0 434129ba616SKumar Gala #define TSEC4_PHYIDX 0 435129ba616SKumar Gala 436129ba616SKumar Gala #define CONFIG_ETHPRIME "eTSEC1" 437129ba616SKumar Gala 438129ba616SKumar Gala #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 439129ba616SKumar Gala #endif /* CONFIG_TSEC_ENET */ 440129ba616SKumar Gala 441129ba616SKumar Gala /* 442129ba616SKumar Gala * Environment 443129ba616SKumar Gala */ 4445a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 445*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 4460e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR 0xfff80000 447129ba616SKumar Gala #else 448*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000) 449129ba616SKumar Gala #endif 4500e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 4510e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 452129ba616SKumar Gala 453129ba616SKumar Gala #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 454*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 455129ba616SKumar Gala 456129ba616SKumar Gala /* 457129ba616SKumar Gala * Command line configuration. 458129ba616SKumar Gala */ 459129ba616SKumar Gala #include <config_cmd_default.h> 460129ba616SKumar Gala 461129ba616SKumar Gala #define CONFIG_CMD_IRQ 462129ba616SKumar Gala #define CONFIG_CMD_PING 463129ba616SKumar Gala #define CONFIG_CMD_I2C 464129ba616SKumar Gala #define CONFIG_CMD_MII 465129ba616SKumar Gala #define CONFIG_CMD_ELF 466129ba616SKumar Gala 467129ba616SKumar Gala #if defined(CONFIG_PCI) 468129ba616SKumar Gala #define CONFIG_CMD_PCI 469129ba616SKumar Gala #define CONFIG_CMD_BEDBUG 470129ba616SKumar Gala #define CONFIG_CMD_NET 471129ba616SKumar Gala #define CONFIG_CMD_SCSI 472129ba616SKumar Gala #define CONFIG_CMD_EXT2 473129ba616SKumar Gala #endif 474129ba616SKumar Gala 475129ba616SKumar Gala #undef CONFIG_WATCHDOG /* watchdog disabled */ 476129ba616SKumar Gala 477129ba616SKumar Gala /* 478129ba616SKumar Gala * Miscellaneous configurable options 479129ba616SKumar Gala */ 480*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 481129ba616SKumar Gala #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 482*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 483*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 484129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 485*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 486129ba616SKumar Gala #else 487*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 488129ba616SKumar Gala #endif 489*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 490*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 491*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 492*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 493129ba616SKumar Gala 494129ba616SKumar Gala /* 495129ba616SKumar Gala * For booting Linux, the board info and command line data 496129ba616SKumar Gala * have to be in the first 8 MB of memory, since this is 497129ba616SKumar Gala * the maximum mapped by the Linux kernel during initialization. 498129ba616SKumar Gala */ 499*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 500129ba616SKumar Gala 501129ba616SKumar Gala /* 502129ba616SKumar Gala * Internal Definitions 503129ba616SKumar Gala * 504129ba616SKumar Gala * Boot Flags 505129ba616SKumar Gala */ 506129ba616SKumar Gala #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 507129ba616SKumar Gala #define BOOTFLAG_WARM 0x02 /* Software reboot */ 508129ba616SKumar Gala 509129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 510129ba616SKumar Gala #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 511129ba616SKumar Gala #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 512129ba616SKumar Gala #endif 513129ba616SKumar Gala 514129ba616SKumar Gala /* 515129ba616SKumar Gala * Environment Configuration 516129ba616SKumar Gala */ 517129ba616SKumar Gala 518129ba616SKumar Gala /* The mac addresses for all ethernet interface */ 519129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 520129ba616SKumar Gala #define CONFIG_HAS_ETH0 521129ba616SKumar Gala #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 522129ba616SKumar Gala #define CONFIG_HAS_ETH1 523129ba616SKumar Gala #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 524129ba616SKumar Gala #define CONFIG_HAS_ETH2 525129ba616SKumar Gala #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 526129ba616SKumar Gala #define CONFIG_HAS_ETH3 527129ba616SKumar Gala #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 528129ba616SKumar Gala #endif 529129ba616SKumar Gala 530129ba616SKumar Gala #define CONFIG_IPADDR 192.168.1.254 531129ba616SKumar Gala 532129ba616SKumar Gala #define CONFIG_HOSTNAME unknown 533129ba616SKumar Gala #define CONFIG_ROOTPATH /opt/nfsroot 534129ba616SKumar Gala #define CONFIG_BOOTFILE uImage 535129ba616SKumar Gala #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 536129ba616SKumar Gala 537129ba616SKumar Gala #define CONFIG_SERVERIP 192.168.1.1 538129ba616SKumar Gala #define CONFIG_GATEWAYIP 192.168.1.1 539129ba616SKumar Gala #define CONFIG_NETMASK 255.255.255.0 540129ba616SKumar Gala 541129ba616SKumar Gala /* default location for tftp and bootm */ 542129ba616SKumar Gala #define CONFIG_LOADADDR 1000000 543129ba616SKumar Gala 544129ba616SKumar Gala #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 545129ba616SKumar Gala #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 546129ba616SKumar Gala 547129ba616SKumar Gala #define CONFIG_BAUDRATE 115200 548129ba616SKumar Gala 549129ba616SKumar Gala #define CONFIG_EXTRA_ENV_SETTINGS \ 550129ba616SKumar Gala "netdev=eth0\0" \ 551129ba616SKumar Gala "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 552129ba616SKumar Gala "tftpflash=tftpboot $loadaddr $uboot; " \ 553129ba616SKumar Gala "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 554129ba616SKumar Gala "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 555129ba616SKumar Gala "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 556129ba616SKumar Gala "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 557129ba616SKumar Gala "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 558129ba616SKumar Gala "consoledev=ttyS0\0" \ 559129ba616SKumar Gala "ramdiskaddr=2000000\0" \ 560129ba616SKumar Gala "ramdiskfile=8572ds/ramdisk.uboot\0" \ 561129ba616SKumar Gala "fdtaddr=c00000\0" \ 562129ba616SKumar Gala "fdtfile=8572ds/mpc8572ds.dtb\0" \ 563129ba616SKumar Gala "bdev=sda3\0" 564129ba616SKumar Gala 565129ba616SKumar Gala #define CONFIG_HDBOOT \ 566129ba616SKumar Gala "setenv bootargs root=/dev/$bdev rw " \ 567129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 568129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 569129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 570129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 571129ba616SKumar Gala 572129ba616SKumar Gala #define CONFIG_NFSBOOTCOMMAND \ 573129ba616SKumar Gala "setenv bootargs root=/dev/nfs rw " \ 574129ba616SKumar Gala "nfsroot=$serverip:$rootpath " \ 575129ba616SKumar Gala "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 576129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 577129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 578129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 579129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 580129ba616SKumar Gala 581129ba616SKumar Gala #define CONFIG_RAMBOOTCOMMAND \ 582129ba616SKumar Gala "setenv bootargs root=/dev/ram rw " \ 583129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 584129ba616SKumar Gala "tftp $ramdiskaddr $ramdiskfile;" \ 585129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 586129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 587129ba616SKumar Gala "bootm $loadaddr $ramdiskaddr $fdtaddr" 588129ba616SKumar Gala 589129ba616SKumar Gala #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 590129ba616SKumar Gala 591129ba616SKumar Gala #endif /* __CONFIG_H */ 592