1129ba616SKumar Gala /* 27c57f3e8SKumar Gala * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3129ba616SKumar Gala * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5129ba616SKumar Gala */ 6129ba616SKumar Gala 7129ba616SKumar Gala /* 8129ba616SKumar Gala * mpc8572ds board configuration file 9129ba616SKumar Gala * 10129ba616SKumar Gala */ 11129ba616SKumar Gala #ifndef __CONFIG_H 12129ba616SKumar Gala #define __CONFIG_H 13129ba616SKumar Gala 14509c4c4cSKumar Gala #include "../board/freescale/common/ics307_clk.h" 15509c4c4cSKumar Gala 16d24f2d32SWolfgang Denk #ifdef CONFIG_36BIT 17f9edcc10SKumar Gala #define CONFIG_PHYS_64BIT 18f9edcc10SKumar Gala #endif 19f9edcc10SKumar Gala 20cb14e93bSKumar Gala #ifdef CONFIG_NAND 21cb14e93bSKumar Gala #define CONFIG_NAND_U_BOOT 22cb14e93bSKumar Gala #define CONFIG_RAMBOOT_NAND 23cb14e93bSKumar Gala #ifdef CONFIG_NAND_SPL 24cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 25cb14e93bSKumar Gala #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 26cb14e93bSKumar Gala #else 27*4a377552SMasahiro Yamada #define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds 28cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE 0xf8f82000 29cb14e93bSKumar Gala #endif /* CONFIG_NAND_SPL */ 30cb14e93bSKumar Gala #endif 31cb14e93bSKumar Gala 32cb14e93bSKumar Gala #ifndef CONFIG_SYS_TEXT_BASE 33cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE 0xeff80000 34cb14e93bSKumar Gala #endif 35cb14e93bSKumar Gala 367a577fdaSKumar Gala #ifndef CONFIG_RESET_VECTOR_ADDRESS 377a577fdaSKumar Gala #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 387a577fdaSKumar Gala #endif 397a577fdaSKumar Gala 40cb14e93bSKumar Gala #ifndef CONFIG_SYS_MONITOR_BASE 41cb14e93bSKumar Gala #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 42cb14e93bSKumar Gala #endif 43cb14e93bSKumar Gala 44129ba616SKumar Gala /* High Level Configuration Options */ 45129ba616SKumar Gala #define CONFIG_BOOKE 1 /* BOOKE */ 46129ba616SKumar Gala #define CONFIG_E500 1 /* BOOKE e500 family */ 47129ba616SKumar Gala #define CONFIG_MPC8572 1 48129ba616SKumar Gala #define CONFIG_MPC8572DS 1 49129ba616SKumar Gala #define CONFIG_MP 1 /* support multiple processors */ 50129ba616SKumar Gala 51c51fc5d5SKumar Gala #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 52129ba616SKumar Gala #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 53129ba616SKumar Gala #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 54129ba616SKumar Gala #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 55129ba616SKumar Gala #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 56129ba616SKumar Gala #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 57842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 58129ba616SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 590151cbacSKumar Gala #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 60129ba616SKumar Gala 61129ba616SKumar Gala #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 62129ba616SKumar Gala 63129ba616SKumar Gala #define CONFIG_TSEC_ENET /* tsec ethernet support */ 64129ba616SKumar Gala #define CONFIG_ENV_OVERWRITE 65129ba616SKumar Gala 66509c4c4cSKumar Gala #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 67509c4c4cSKumar Gala #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 684ca06607SHaiying Wang #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 69129ba616SKumar Gala 70129ba616SKumar Gala /* 71129ba616SKumar Gala * These can be toggled for performance analysis, otherwise use default. 72129ba616SKumar Gala */ 73129ba616SKumar Gala #define CONFIG_L2_CACHE /* toggle L2 cache */ 74129ba616SKumar Gala #define CONFIG_BTB /* toggle branch predition */ 75129ba616SKumar Gala 76129ba616SKumar Gala #define CONFIG_ENABLE_36BIT_PHYS 1 77129ba616SKumar Gala 7818af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 7918af1c5fSKumar Gala #define CONFIG_ADDR_MAP 1 8018af1c5fSKumar Gala #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 8118af1c5fSKumar Gala #endif 8218af1c5fSKumar Gala 836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x7fffffff 85129ba616SKumar Gala #define CONFIG_PANIC_HANG /* do not reset board on panic */ 86129ba616SKumar Gala 87129ba616SKumar Gala /* 88cb14e93bSKumar Gala * Config the L2 Cache as L2 SRAM 89cb14e93bSKumar Gala */ 90cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 91cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 92cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 93cb14e93bSKumar Gala #else 94cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 95cb14e93bSKumar Gala #endif 96cb14e93bSKumar Gala #define CONFIG_SYS_L2_SIZE (512 << 10) 97cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 98cb14e93bSKumar Gala 99e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR 0xffe00000 100e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 101129ba616SKumar Gala 1028d22ddcaSKumar Gala #if defined(CONFIG_NAND_SPL) 103e46fedfeSTimur Tabi #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 104cb14e93bSKumar Gala #endif 105cb14e93bSKumar Gala 106129ba616SKumar Gala /* DDR Setup */ 107f8523cb0SKumar Gala #define CONFIG_VERY_BIG_RAM 1085614e71bSYork Sun #define CONFIG_SYS_FSL_DDR2 109129ba616SKumar Gala #undef CONFIG_FSL_DDR_INTERACTIVE 110129ba616SKumar Gala #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 111129ba616SKumar Gala #define CONFIG_DDR_SPD 112129ba616SKumar Gala 113d34897d3SYork Sun #define CONFIG_DDR_ECC 1149b0ad1b1SDave Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 115129ba616SKumar Gala #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 116129ba616SKumar Gala 1176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 119129ba616SKumar Gala 120129ba616SKumar Gala #define CONFIG_NUM_DDR_CONTROLLERS 2 121129ba616SKumar Gala #define CONFIG_DIMM_SLOTS_PER_CTLR 1 122129ba616SKumar Gala #define CONFIG_CHIP_SELECTS_PER_CTRL 2 123129ba616SKumar Gala 124129ba616SKumar Gala /* I2C addresses of SPD EEPROMs */ 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 126129ba616SKumar Gala #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 127129ba616SKumar Gala #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 128129ba616SKumar Gala 129129ba616SKumar Gala /* These are used when DDR doesn't use SPD. */ 130dc889e86SDave Liu #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 1316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 132dc889e86SDave Liu #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 133dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_3 0x00020000 1346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 0x00260802 135dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 136dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 137dc889e86SDave Liu #define CONFIG_SYS_DDR_MODE_1 0x00440462 1386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x00000000 139dc889e86SDave Liu #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 1406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 141dc889e86SDave Liu #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 1436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 144dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 145dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL2 0x24400000 146129ba616SKumar Gala 1476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 1486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 1496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SBE 0x00010000 150129ba616SKumar Gala 151129ba616SKumar Gala /* 152129ba616SKumar Gala * Make sure required options are set 153129ba616SKumar Gala */ 154129ba616SKumar Gala #ifndef CONFIG_SPD_EEPROM 155129ba616SKumar Gala #error ("CONFIG_SPD_EEPROM is required") 156129ba616SKumar Gala #endif 157129ba616SKumar Gala 158129ba616SKumar Gala #undef CONFIG_CLOCKS_IN_MHZ 159129ba616SKumar Gala 160129ba616SKumar Gala /* 161129ba616SKumar Gala * Memory map 162129ba616SKumar Gala * 163129ba616SKumar Gala * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 164129ba616SKumar Gala * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 165129ba616SKumar Gala * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 166129ba616SKumar Gala * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 167129ba616SKumar Gala * 168129ba616SKumar Gala * Localbus cacheable (TBD) 169129ba616SKumar Gala * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 170129ba616SKumar Gala * 171129ba616SKumar Gala * Localbus non-cacheable 172129ba616SKumar Gala * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 173129ba616SKumar Gala * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 174c013b749SHaiying Wang * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 175129ba616SKumar Gala * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 176129ba616SKumar Gala * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 177129ba616SKumar Gala * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 178129ba616SKumar Gala */ 179129ba616SKumar Gala 180129ba616SKumar Gala /* 181129ba616SKumar Gala * Local Bus Definitions 182129ba616SKumar Gala */ 1836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 18418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 18518af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 18618af1c5fSKumar Gala #else 187c953ddfdSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 18818af1c5fSKumar Gala #endif 189129ba616SKumar Gala 190cb14e93bSKumar Gala 191cb14e93bSKumar Gala #define CONFIG_FLASH_BR_PRELIM \ 1927ee41107STimur Tabi (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 193cb14e93bSKumar Gala #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 194129ba616SKumar Gala 195c953ddfdSKumar Gala #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 1966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 197129ba616SKumar Gala 19818af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 1996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 200129ba616SKumar Gala #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 201129ba616SKumar Gala 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 2046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CHECKSUM 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 207129ba616SKumar Gala 208cb14e93bSKumar Gala #if defined(CONFIG_RAMBOOT_NAND) 209cb14e93bSKumar Gala #define CONFIG_SYS_RAMBOOT 210cb14e93bSKumar Gala #define CONFIG_SYS_EXTRA_ENV_RELOC 211cb14e93bSKumar Gala #else 212cb14e93bSKumar Gala #undef CONFIG_SYS_RAMBOOT 213cb14e93bSKumar Gala #endif 214129ba616SKumar Gala 215129ba616SKumar Gala #define CONFIG_FLASH_CFI_DRIVER 2166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 2176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 2186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 219129ba616SKumar Gala 220129ba616SKumar Gala #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 221129ba616SKumar Gala 222558710b9SKumar Gala #define CONFIG_HWCONFIG /* enable hwconfig */ 223129ba616SKumar Gala #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 224129ba616SKumar Gala #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 22518af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 22618af1c5fSKumar Gala #define PIXIS_BASE_PHYS 0xfffdf0000ull 22718af1c5fSKumar Gala #else 22852b565f5SKumar Gala #define PIXIS_BASE_PHYS PIXIS_BASE 22918af1c5fSKumar Gala #endif 230129ba616SKumar Gala 23152b565f5SKumar Gala #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 2326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 233129ba616SKumar Gala 234129ba616SKumar Gala #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 235129ba616SKumar Gala #define PIXIS_VER 0x1 /* Board version at offset 1 */ 236129ba616SKumar Gala #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 237129ba616SKumar Gala #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 238129ba616SKumar Gala #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 239129ba616SKumar Gala #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 240129ba616SKumar Gala #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 241129ba616SKumar Gala #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 242129ba616SKumar Gala #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 243129ba616SKumar Gala #define PIXIS_VCTL 0x10 /* VELA Control Register */ 244129ba616SKumar Gala #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 245129ba616SKumar Gala #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 246129ba616SKumar Gala #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 247129ba616SKumar Gala #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 248129ba616SKumar Gala #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 2496bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 2506bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 2516bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 2526bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 2536bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 254129ba616SKumar Gala #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 255129ba616SKumar Gala #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 256129ba616SKumar Gala #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 257129ba616SKumar Gala #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 258129ba616SKumar Gala #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 259129ba616SKumar Gala #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 260129ba616SKumar Gala #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 261129ba616SKumar Gala #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 262129ba616SKumar Gala #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 263129ba616SKumar Gala #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 264129ba616SKumar Gala #define PIXIS_LED 0x25 /* LED Register */ 265129ba616SKumar Gala 266cb14e93bSKumar Gala #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 267cb14e93bSKumar Gala 268129ba616SKumar Gala /* old pixis referenced names */ 269129ba616SKumar Gala #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 270129ba616SKumar Gala #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 2716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 2727e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC1SER 0x8 2737e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC2SER 0x4 2747e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC3SER 0x2 2757e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC4SER 0x1 2767e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC1SER 0x20 2777e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC2SER 0x20 2787e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC3SER 0x20 2797e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC4SER 0x20 2807e183cadSLiu Yu #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 2817e183cadSLiu Yu | PIXIS_VSPEED2_TSEC2SER \ 2827e183cadSLiu Yu | PIXIS_VSPEED2_TSEC3SER \ 2837e183cadSLiu Yu | PIXIS_VSPEED2_TSEC4SER) 2847e183cadSLiu Yu #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 2857e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC2SER \ 2867e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC3SER \ 2877e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC4SER) 288129ba616SKumar Gala 2896d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 2906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 291553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 292129ba616SKumar Gala 29325ddd1fbSWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 295129ba616SKumar Gala 2966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 2976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 298129ba616SKumar Gala 299cb14e93bSKumar Gala #ifndef CONFIG_NAND_SPL 300c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE 0xffa00000 30118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 30218af1c5fSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 30318af1c5fSKumar Gala #else 304c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 30518af1c5fSKumar Gala #endif 306cb14e93bSKumar Gala #else 307cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE 0xfff00000 308cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 309cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 310cb14e93bSKumar Gala #else 311cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 312cb14e93bSKumar Gala #endif 313cb14e93bSKumar Gala #endif 314cb14e93bSKumar Gala 315c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 316c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x40000, \ 317c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x80000,\ 318c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0xC0000} 319c013b749SHaiying Wang #define CONFIG_SYS_MAX_NAND_DEVICE 4 320c013b749SHaiying Wang #define CONFIG_MTD_NAND_VERIFY_WRITE 321c013b749SHaiying Wang #define CONFIG_CMD_NAND 1 322c013b749SHaiying Wang #define CONFIG_NAND_FSL_ELBC 1 323c013b749SHaiying Wang #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 32468ec9c85SPrabhakar Kushwaha #define CONFIG_SYS_NAND_MAX_OOBFREE 5 32568ec9c85SPrabhakar Kushwaha #define CONFIG_SYS_NAND_MAX_ECCPOS 56 326c013b749SHaiying Wang 327cb14e93bSKumar Gala /* NAND boot: 4K NAND loader config */ 328cb14e93bSKumar Gala #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 329cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 330cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 331cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_START \ 332cb14e93bSKumar Gala (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 333cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 334cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 335cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 336cb14e93bSKumar Gala 337cb14e93bSKumar Gala 338c013b749SHaiying Wang /* NAND flash config */ 339a3055c58SMatthew McClintock #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 340c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 341c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 342c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 343c013b749SHaiying Wang | BR_V) /* valid */ 344a3055c58SMatthew McClintock #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 345c013b749SHaiying Wang | OR_FCM_PGS /* Large Page*/ \ 346c013b749SHaiying Wang | OR_FCM_CSCT \ 347c013b749SHaiying Wang | OR_FCM_CST \ 348c013b749SHaiying Wang | OR_FCM_CHT \ 349c013b749SHaiying Wang | OR_FCM_SCY_1 \ 350c013b749SHaiying Wang | OR_FCM_TRLX \ 351c013b749SHaiying Wang | OR_FCM_EHTR) 352c013b749SHaiying Wang 353cb14e93bSKumar Gala #ifdef CONFIG_RAMBOOT_NAND 354a3055c58SMatthew McClintock #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 355a3055c58SMatthew McClintock #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 356cb14e93bSKumar Gala #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 357cb14e93bSKumar Gala #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 358cb14e93bSKumar Gala #else 359cb14e93bSKumar Gala #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 360cb14e93bSKumar Gala #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 361a3055c58SMatthew McClintock #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 362a3055c58SMatthew McClintock #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 363cb14e93bSKumar Gala #endif 3647ee41107STimur Tabi #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 365c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 366c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 367c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 368c013b749SHaiying Wang | BR_V) /* valid */ 369a3055c58SMatthew McClintock #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 3707ee41107STimur Tabi #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 371c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 372c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 373c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 374c013b749SHaiying Wang | BR_V) /* valid */ 375a3055c58SMatthew McClintock #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 376c013b749SHaiying Wang 3777ee41107STimur Tabi #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 378c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 379c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 380c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 381c013b749SHaiying Wang | BR_V) /* valid */ 382a3055c58SMatthew McClintock #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 383c013b749SHaiying Wang 384c013b749SHaiying Wang 385129ba616SKumar Gala /* Serial Port - controlled on board with jumper J8 386129ba616SKumar Gala * open - index 2 387129ba616SKumar Gala * shorted - index 1 388129ba616SKumar Gala */ 389129ba616SKumar Gala #define CONFIG_CONS_INDEX 1 3906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 394cb14e93bSKumar Gala #ifdef CONFIG_NAND_SPL 395cb14e93bSKumar Gala #define CONFIG_NS16550_MIN_FUNCTIONS 396cb14e93bSKumar Gala #endif 397129ba616SKumar Gala 3986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 399129ba616SKumar Gala {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 400129ba616SKumar Gala 4016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 4026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 403129ba616SKumar Gala 404129ba616SKumar Gala /* Use the HUSH parser */ 4056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 406129ba616SKumar Gala 407129ba616SKumar Gala /* 408129ba616SKumar Gala * Pass open firmware flat tree 409129ba616SKumar Gala */ 410129ba616SKumar Gala #define CONFIG_OF_LIBFDT 1 411129ba616SKumar Gala #define CONFIG_OF_BOARD_SETUP 1 412129ba616SKumar Gala #define CONFIG_OF_STDOUT_VIA_ALIAS 1 413129ba616SKumar Gala 414129ba616SKumar Gala /* new uImage format support */ 415129ba616SKumar Gala #define CONFIG_FIT 1 416129ba616SKumar Gala #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 417129ba616SKumar Gala 418129ba616SKumar Gala /* I2C */ 41900f792e0SHeiko Schocher #define CONFIG_SYS_I2C 42000f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 42100f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 42200f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 42300f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 42400f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 42500f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 42600f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 42700f792e0SHeiko Schocher #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 4286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 429129ba616SKumar Gala 430129ba616SKumar Gala /* 431445a7b38SHaiying Wang * I2C2 EEPROM 432445a7b38SHaiying Wang */ 433445a7b38SHaiying Wang #define CONFIG_ID_EEPROM 434445a7b38SHaiying Wang #ifdef CONFIG_ID_EEPROM 4356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_NXID 436445a7b38SHaiying Wang #endif 4376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 4386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 4396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_EEPROM_BUS_NUM 1 440445a7b38SHaiying Wang 441445a7b38SHaiying Wang /* 442129ba616SKumar Gala * General PCI 443129ba616SKumar Gala * Memory space is mapped 1-1, but I/O space must start from 0. 444129ba616SKumar Gala */ 445129ba616SKumar Gala 446129ba616SKumar Gala /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 44718ea5551SKumar Gala #define CONFIG_SYS_PCIE3_NAME "ULI" 4485af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 44918af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 450156984a3SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 45118af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 45218af1c5fSKumar Gala #else 453ad97dce1SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 4545af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 45518af1c5fSKumar Gala #endif 4566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 457aca5f018SKumar Gala #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 4585f91ef6aSKumar Gala #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 45918af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 46018af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 46118af1c5fSKumar Gala #else 4626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 46318af1c5fSKumar Gala #endif 4646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 465129ba616SKumar Gala 466129ba616SKumar Gala /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 46718ea5551SKumar Gala #define CONFIG_SYS_PCIE2_NAME "Slot 1" 4685af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 46918af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 470156984a3SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 47118af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 47218af1c5fSKumar Gala #else 473ad97dce1SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 4745af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 47518af1c5fSKumar Gala #endif 4766d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 477aca5f018SKumar Gala #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 4785f91ef6aSKumar Gala #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 47918af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 48018af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 48118af1c5fSKumar Gala #else 4826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 48318af1c5fSKumar Gala #endif 4846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 485129ba616SKumar Gala 486129ba616SKumar Gala /* controller 1, Slot 1, tgtid 1, Base address a000 */ 48718ea5551SKumar Gala #define CONFIG_SYS_PCIE1_NAME "Slot 2" 4885af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 48918af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 490156984a3SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 49118af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 49218af1c5fSKumar Gala #else 493ad97dce1SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 4945af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 49518af1c5fSKumar Gala #endif 4966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 497aca5f018SKumar Gala #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 4985f91ef6aSKumar Gala #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 49918af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 50018af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 50118af1c5fSKumar Gala #else 5026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 50318af1c5fSKumar Gala #endif 5046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 505129ba616SKumar Gala 506129ba616SKumar Gala #if defined(CONFIG_PCI) 507129ba616SKumar Gala 508129ba616SKumar Gala /*PCIE video card used*/ 509aca5f018SKumar Gala #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 510129ba616SKumar Gala 511129ba616SKumar Gala /* video */ 512129ba616SKumar Gala #define CONFIG_VIDEO 513129ba616SKumar Gala 514129ba616SKumar Gala #if defined(CONFIG_VIDEO) 515129ba616SKumar Gala #define CONFIG_BIOSEMU 516129ba616SKumar Gala #define CONFIG_CFB_CONSOLE 517129ba616SKumar Gala #define CONFIG_VIDEO_SW_CURSOR 518129ba616SKumar Gala #define CONFIG_VGA_AS_SINGLE_DEVICE 519129ba616SKumar Gala #define CONFIG_ATI_RADEON_FB 520129ba616SKumar Gala #define CONFIG_VIDEO_LOGO 521129ba616SKumar Gala /*#define CONFIG_CONSOLE_CURSOR*/ 5226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 523129ba616SKumar Gala #endif 524129ba616SKumar Gala 525129ba616SKumar Gala #define CONFIG_PCI_PNP /* do pci plug-and-play */ 526129ba616SKumar Gala 527129ba616SKumar Gala #undef CONFIG_EEPRO100 528129ba616SKumar Gala #undef CONFIG_TULIP 529129ba616SKumar Gala #undef CONFIG_RTL8139 53016855ec1SKumar Gala #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 531129ba616SKumar Gala 532129ba616SKumar Gala #ifndef CONFIG_PCI_PNP 5335f91ef6aSKumar Gala #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 5345f91ef6aSKumar Gala #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 535129ba616SKumar Gala #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 536129ba616SKumar Gala #endif 537129ba616SKumar Gala 538129ba616SKumar Gala #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 539129ba616SKumar Gala #define CONFIG_DOS_PARTITION 540129ba616SKumar Gala #define CONFIG_SCSI_AHCI 541129ba616SKumar Gala 542129ba616SKumar Gala #ifdef CONFIG_SCSI_AHCI 543344ca0b4SRob Herring #define CONFIG_LIBATA 544129ba616SKumar Gala #define CONFIG_SATA_ULI5288 5456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 5466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_LUN 1 5476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 5486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 549129ba616SKumar Gala #endif /* SCSI */ 550129ba616SKumar Gala 551129ba616SKumar Gala #endif /* CONFIG_PCI */ 552129ba616SKumar Gala 553129ba616SKumar Gala 554129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 555129ba616SKumar Gala 556129ba616SKumar Gala #define CONFIG_MII 1 /* MII PHY management */ 557129ba616SKumar Gala #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 558129ba616SKumar Gala #define CONFIG_TSEC1 1 559129ba616SKumar Gala #define CONFIG_TSEC1_NAME "eTSEC1" 560129ba616SKumar Gala #define CONFIG_TSEC2 1 561129ba616SKumar Gala #define CONFIG_TSEC2_NAME "eTSEC2" 562129ba616SKumar Gala #define CONFIG_TSEC3 1 563129ba616SKumar Gala #define CONFIG_TSEC3_NAME "eTSEC3" 564129ba616SKumar Gala #define CONFIG_TSEC4 1 565129ba616SKumar Gala #define CONFIG_TSEC4_NAME "eTSEC4" 566129ba616SKumar Gala 5677e183cadSLiu Yu #define CONFIG_PIXIS_SGMII_CMD 5687e183cadSLiu Yu #define CONFIG_FSL_SGMII_RISER 1 5697e183cadSLiu Yu #define SGMII_RISER_PHY_OFFSET 0x1c 5707e183cadSLiu Yu 5717e183cadSLiu Yu #ifdef CONFIG_FSL_SGMII_RISER 5727e183cadSLiu Yu #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 5737e183cadSLiu Yu #endif 5747e183cadSLiu Yu 575129ba616SKumar Gala #define TSEC1_PHY_ADDR 0 576129ba616SKumar Gala #define TSEC2_PHY_ADDR 1 577129ba616SKumar Gala #define TSEC3_PHY_ADDR 2 578129ba616SKumar Gala #define TSEC4_PHY_ADDR 3 579129ba616SKumar Gala 580129ba616SKumar Gala #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 581129ba616SKumar Gala #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 582129ba616SKumar Gala #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 583129ba616SKumar Gala #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 584129ba616SKumar Gala 585129ba616SKumar Gala #define TSEC1_PHYIDX 0 586129ba616SKumar Gala #define TSEC2_PHYIDX 0 587129ba616SKumar Gala #define TSEC3_PHYIDX 0 588129ba616SKumar Gala #define TSEC4_PHYIDX 0 589129ba616SKumar Gala 590129ba616SKumar Gala #define CONFIG_ETHPRIME "eTSEC1" 591129ba616SKumar Gala 592129ba616SKumar Gala #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 593129ba616SKumar Gala #endif /* CONFIG_TSEC_ENET */ 594129ba616SKumar Gala 595129ba616SKumar Gala /* 596129ba616SKumar Gala * Environment 597129ba616SKumar Gala */ 598cb14e93bSKumar Gala 599cb14e93bSKumar Gala #if defined(CONFIG_SYS_RAMBOOT) 600cb14e93bSKumar Gala #if defined(CONFIG_RAMBOOT_NAND) 601cb14e93bSKumar Gala #define CONFIG_ENV_IS_IN_NAND 1 602cb14e93bSKumar Gala #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 603cb14e93bSKumar Gala #define CONFIG_ENV_OFFSET ((512 * 1024)\ 604cb14e93bSKumar Gala + CONFIG_SYS_NAND_BLOCK_SIZE) 605cb14e93bSKumar Gala #endif 606cb14e93bSKumar Gala 607cb14e93bSKumar Gala #else 6085a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 6096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 6100e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR 0xfff80000 611129ba616SKumar Gala #else 6126fc110bdSHaiying Wang #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 613129ba616SKumar Gala #endif 6140e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 6150e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 616cb14e93bSKumar Gala #endif 617129ba616SKumar Gala 618129ba616SKumar Gala #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 6196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 620129ba616SKumar Gala 621129ba616SKumar Gala /* 622129ba616SKumar Gala * Command line configuration. 623129ba616SKumar Gala */ 624129ba616SKumar Gala #include <config_cmd_default.h> 625129ba616SKumar Gala 62667f94476SYork Sun #define CONFIG_CMD_ERRATA 627129ba616SKumar Gala #define CONFIG_CMD_IRQ 628129ba616SKumar Gala #define CONFIG_CMD_PING 629129ba616SKumar Gala #define CONFIG_CMD_I2C 630129ba616SKumar Gala #define CONFIG_CMD_MII 631129ba616SKumar Gala #define CONFIG_CMD_ELF 6321c9aa76bSKumar Gala #define CONFIG_CMD_SETEXPR 633199e262eSBecky Bruce #define CONFIG_CMD_REGINFO 634129ba616SKumar Gala 635129ba616SKumar Gala #if defined(CONFIG_PCI) 636129ba616SKumar Gala #define CONFIG_CMD_PCI 637129ba616SKumar Gala #define CONFIG_CMD_NET 638129ba616SKumar Gala #define CONFIG_CMD_SCSI 639129ba616SKumar Gala #define CONFIG_CMD_EXT2 640129ba616SKumar Gala #endif 641129ba616SKumar Gala 642863a3eacSZhao Chenhui /* 643863a3eacSZhao Chenhui * USB 644863a3eacSZhao Chenhui */ 645863a3eacSZhao Chenhui #define CONFIG_USB_EHCI 646863a3eacSZhao Chenhui 647863a3eacSZhao Chenhui #ifdef CONFIG_USB_EHCI 648863a3eacSZhao Chenhui #define CONFIG_CMD_USB 649863a3eacSZhao Chenhui #define CONFIG_USB_EHCI_PCI 650863a3eacSZhao Chenhui #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 651863a3eacSZhao Chenhui #define CONFIG_USB_STORAGE 652863a3eacSZhao Chenhui #define CONFIG_PCI_EHCI_DEVICE 0 653863a3eacSZhao Chenhui #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 654863a3eacSZhao Chenhui #endif 655863a3eacSZhao Chenhui 656129ba616SKumar Gala #undef CONFIG_WATCHDOG /* watchdog disabled */ 657129ba616SKumar Gala 658129ba616SKumar Gala /* 659129ba616SKumar Gala * Miscellaneous configurable options 660129ba616SKumar Gala */ 6616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 662129ba616SKumar Gala #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 6635be58f5fSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 6646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 665129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 6666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 667129ba616SKumar Gala #else 6686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 669129ba616SKumar Gala #endif 6706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 6716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 6726d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 673129ba616SKumar Gala 674129ba616SKumar Gala /* 675129ba616SKumar Gala * For booting Linux, the board info and command line data 676a832ac41SKumar Gala * have to be in the first 64 MB of memory, since this is 677129ba616SKumar Gala * the maximum mapped by the Linux kernel during initialization. 678129ba616SKumar Gala */ 679a832ac41SKumar Gala #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 680a832ac41SKumar Gala #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 681129ba616SKumar Gala 682129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 683129ba616SKumar Gala #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 684129ba616SKumar Gala #endif 685129ba616SKumar Gala 686129ba616SKumar Gala /* 687129ba616SKumar Gala * Environment Configuration 688129ba616SKumar Gala */ 689129ba616SKumar Gala 690129ba616SKumar Gala /* The mac addresses for all ethernet interface */ 691129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 692129ba616SKumar Gala #define CONFIG_HAS_ETH0 693129ba616SKumar Gala #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 694129ba616SKumar Gala #define CONFIG_HAS_ETH1 695129ba616SKumar Gala #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 696129ba616SKumar Gala #define CONFIG_HAS_ETH2 697129ba616SKumar Gala #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 698129ba616SKumar Gala #define CONFIG_HAS_ETH3 699129ba616SKumar Gala #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 700129ba616SKumar Gala #endif 701129ba616SKumar Gala 702129ba616SKumar Gala #define CONFIG_IPADDR 192.168.1.254 703129ba616SKumar Gala 704129ba616SKumar Gala #define CONFIG_HOSTNAME unknown 7058b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/opt/nfsroot" 706b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 707129ba616SKumar Gala #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 708129ba616SKumar Gala 709129ba616SKumar Gala #define CONFIG_SERVERIP 192.168.1.1 710129ba616SKumar Gala #define CONFIG_GATEWAYIP 192.168.1.1 711129ba616SKumar Gala #define CONFIG_NETMASK 255.255.255.0 712129ba616SKumar Gala 713129ba616SKumar Gala /* default location for tftp and bootm */ 714129ba616SKumar Gala #define CONFIG_LOADADDR 1000000 715129ba616SKumar Gala 716129ba616SKumar Gala #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 717129ba616SKumar Gala #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 718129ba616SKumar Gala 719129ba616SKumar Gala #define CONFIG_BAUDRATE 115200 720129ba616SKumar Gala 721129ba616SKumar Gala #define CONFIG_EXTRA_ENV_SETTINGS \ 722238e1467SHongtao Jia "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 723129ba616SKumar Gala "netdev=eth0\0" \ 7245368c55dSMarek Vasut "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 725129ba616SKumar Gala "tftpflash=tftpboot $loadaddr $uboot; " \ 7265368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 7275368c55dSMarek Vasut " +$filesize; " \ 7285368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 7295368c55dSMarek Vasut " +$filesize; " \ 7305368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7315368c55dSMarek Vasut " $filesize; " \ 7325368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 7335368c55dSMarek Vasut " +$filesize; " \ 7345368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7355368c55dSMarek Vasut " $filesize\0" \ 736129ba616SKumar Gala "consoledev=ttyS0\0" \ 737129ba616SKumar Gala "ramdiskaddr=2000000\0" \ 738129ba616SKumar Gala "ramdiskfile=8572ds/ramdisk.uboot\0" \ 739129ba616SKumar Gala "fdtaddr=c00000\0" \ 740129ba616SKumar Gala "fdtfile=8572ds/mpc8572ds.dtb\0" \ 741129ba616SKumar Gala "bdev=sda3\0" 742129ba616SKumar Gala 743129ba616SKumar Gala #define CONFIG_HDBOOT \ 744129ba616SKumar Gala "setenv bootargs root=/dev/$bdev rw " \ 745129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 746129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 747129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 748129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 749129ba616SKumar Gala 750129ba616SKumar Gala #define CONFIG_NFSBOOTCOMMAND \ 751129ba616SKumar Gala "setenv bootargs root=/dev/nfs rw " \ 752129ba616SKumar Gala "nfsroot=$serverip:$rootpath " \ 753129ba616SKumar Gala "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 754129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 755129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 756129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 757129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 758129ba616SKumar Gala 759129ba616SKumar Gala #define CONFIG_RAMBOOTCOMMAND \ 760129ba616SKumar Gala "setenv bootargs root=/dev/ram rw " \ 761129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 762129ba616SKumar Gala "tftp $ramdiskaddr $ramdiskfile;" \ 763129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 764129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 765129ba616SKumar Gala "bootm $loadaddr $ramdiskaddr $fdtaddr" 766129ba616SKumar Gala 767129ba616SKumar Gala #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 768129ba616SKumar Gala 769129ba616SKumar Gala #endif /* __CONFIG_H */ 770