1129ba616SKumar Gala /* 2129ba616SKumar Gala * Copyright 2007-2008 Freescale Semiconductor, Inc. 3129ba616SKumar Gala * 4129ba616SKumar Gala * See file CREDITS for list of people who contributed to this 5129ba616SKumar Gala * project. 6129ba616SKumar Gala * 7129ba616SKumar Gala * This program is free software; you can redistribute it and/or 8129ba616SKumar Gala * modify it under the terms of the GNU General Public License as 9129ba616SKumar Gala * published by the Free Software Foundation; either version 2 of 10129ba616SKumar Gala * the License, or (at your option) any later version. 11129ba616SKumar Gala * 12129ba616SKumar Gala * This program is distributed in the hope that it will be useful, 13129ba616SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 14129ba616SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15129ba616SKumar Gala * GNU General Public License for more details. 16129ba616SKumar Gala * 17129ba616SKumar Gala * You should have received a copy of the GNU General Public License 18129ba616SKumar Gala * along with this program; if not, write to the Free Software 19129ba616SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20129ba616SKumar Gala * MA 02111-1307 USA 21129ba616SKumar Gala */ 22129ba616SKumar Gala 23129ba616SKumar Gala /* 24129ba616SKumar Gala * mpc8572ds board configuration file 25129ba616SKumar Gala * 26129ba616SKumar Gala */ 27129ba616SKumar Gala #ifndef __CONFIG_H 28129ba616SKumar Gala #define __CONFIG_H 29129ba616SKumar Gala 30f9edcc10SKumar Gala #ifdef CONFIG_MK_36BIT 31f9edcc10SKumar Gala #define CONFIG_PHYS_64BIT 32f9edcc10SKumar Gala #endif 33f9edcc10SKumar Gala 34129ba616SKumar Gala /* High Level Configuration Options */ 35129ba616SKumar Gala #define CONFIG_BOOKE 1 /* BOOKE */ 36129ba616SKumar Gala #define CONFIG_E500 1 /* BOOKE e500 family */ 37129ba616SKumar Gala #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 38129ba616SKumar Gala #define CONFIG_MPC8572 1 39129ba616SKumar Gala #define CONFIG_MPC8572DS 1 40129ba616SKumar Gala #define CONFIG_MP 1 /* support multiple processors */ 41129ba616SKumar Gala 42c51fc5d5SKumar Gala #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 43129ba616SKumar Gala #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 44129ba616SKumar Gala #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 45129ba616SKumar Gala #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 46129ba616SKumar Gala #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 47129ba616SKumar Gala #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 48129ba616SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 490151cbacSKumar Gala #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 50129ba616SKumar Gala 51129ba616SKumar Gala #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 52129ba616SKumar Gala 53129ba616SKumar Gala #define CONFIG_TSEC_ENET /* tsec ethernet support */ 54129ba616SKumar Gala #define CONFIG_ENV_OVERWRITE 55129ba616SKumar Gala 56129ba616SKumar Gala #ifndef __ASSEMBLY__ 57129ba616SKumar Gala extern unsigned long get_board_sys_clk(unsigned long dummy); 58129ba616SKumar Gala extern unsigned long get_board_ddr_clk(unsigned long dummy); 59129ba616SKumar Gala #endif 60129ba616SKumar Gala #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 61129ba616SKumar Gala #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 624ca06607SHaiying Wang #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 63129ba616SKumar Gala #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 64129ba616SKumar Gala from ICS307 instead of switches */ 65129ba616SKumar Gala 66129ba616SKumar Gala /* 67129ba616SKumar Gala * These can be toggled for performance analysis, otherwise use default. 68129ba616SKumar Gala */ 69129ba616SKumar Gala #define CONFIG_L2_CACHE /* toggle L2 cache */ 70129ba616SKumar Gala #define CONFIG_BTB /* toggle branch predition */ 71129ba616SKumar Gala 72129ba616SKumar Gala #define CONFIG_ENABLE_36BIT_PHYS 1 73129ba616SKumar Gala 7418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 7518af1c5fSKumar Gala #define CONFIG_ADDR_MAP 1 7618af1c5fSKumar Gala #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 7718af1c5fSKumar Gala #endif 7818af1c5fSKumar Gala 796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x7fffffff 81129ba616SKumar Gala #define CONFIG_PANIC_HANG /* do not reset board on panic */ 82129ba616SKumar Gala 83129ba616SKumar Gala /* 84129ba616SKumar Gala * Base addresses -- Note these are effective addresses where the 85129ba616SKumar Gala * actual resources get mapped (not physical addresses) 86129ba616SKumar Gala */ 876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 8918af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 9018af1c5fSKumar Gala #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 9118af1c5fSKumar Gala #else 926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 9318af1c5fSKumar Gala #endif 946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 95129ba616SKumar Gala 966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) 986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 99129ba616SKumar Gala 100129ba616SKumar Gala /* DDR Setup */ 101f8523cb0SKumar Gala #define CONFIG_VERY_BIG_RAM 102129ba616SKumar Gala #define CONFIG_FSL_DDR2 103129ba616SKumar Gala #undef CONFIG_FSL_DDR_INTERACTIVE 104129ba616SKumar Gala #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 105129ba616SKumar Gala #define CONFIG_DDR_SPD 106129ba616SKumar Gala #undef CONFIG_DDR_DLL 107129ba616SKumar Gala 1089b0ad1b1SDave Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 109129ba616SKumar Gala #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 110129ba616SKumar Gala 1116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 113129ba616SKumar Gala 114129ba616SKumar Gala #define CONFIG_NUM_DDR_CONTROLLERS 2 115129ba616SKumar Gala #define CONFIG_DIMM_SLOTS_PER_CTLR 1 116129ba616SKumar Gala #define CONFIG_CHIP_SELECTS_PER_CTRL 2 117129ba616SKumar Gala 118129ba616SKumar Gala /* I2C addresses of SPD EEPROMs */ 1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 120129ba616SKumar Gala #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 121129ba616SKumar Gala #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 122129ba616SKumar Gala 123129ba616SKumar Gala /* These are used when DDR doesn't use SPD. */ 124dc889e86SDave Liu #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 126dc889e86SDave Liu #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 127dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_3 0x00020000 1286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 0x00260802 129dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 130dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 131dc889e86SDave Liu #define CONFIG_SYS_DDR_MODE_1 0x00440462 1326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x00000000 133dc889e86SDave Liu #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 1346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 135dc889e86SDave Liu #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 1366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 1376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 138dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 139dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL2 0x24400000 140129ba616SKumar Gala 1416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 1426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 1436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SBE 0x00010000 144129ba616SKumar Gala 145129ba616SKumar Gala /* 146129ba616SKumar Gala * Make sure required options are set 147129ba616SKumar Gala */ 148129ba616SKumar Gala #ifndef CONFIG_SPD_EEPROM 149129ba616SKumar Gala #error ("CONFIG_SPD_EEPROM is required") 150129ba616SKumar Gala #endif 151129ba616SKumar Gala 152129ba616SKumar Gala #undef CONFIG_CLOCKS_IN_MHZ 153129ba616SKumar Gala 154129ba616SKumar Gala /* 155129ba616SKumar Gala * Memory map 156129ba616SKumar Gala * 157129ba616SKumar Gala * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 158129ba616SKumar Gala * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 159129ba616SKumar Gala * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 160129ba616SKumar Gala * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 161129ba616SKumar Gala * 162129ba616SKumar Gala * Localbus cacheable (TBD) 163129ba616SKumar Gala * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 164129ba616SKumar Gala * 165129ba616SKumar Gala * Localbus non-cacheable 166129ba616SKumar Gala * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 167129ba616SKumar Gala * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 168c013b749SHaiying Wang * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 169129ba616SKumar Gala * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 170129ba616SKumar Gala * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 171129ba616SKumar Gala * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 172129ba616SKumar Gala */ 173129ba616SKumar Gala 174129ba616SKumar Gala /* 175129ba616SKumar Gala * Local Bus Definitions 176129ba616SKumar Gala */ 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 17818af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 17918af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 18018af1c5fSKumar Gala #else 181c953ddfdSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 18218af1c5fSKumar Gala #endif 183129ba616SKumar Gala 184c953ddfdSKumar Gala #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) 1856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 186129ba616SKumar Gala 187c953ddfdSKumar Gala #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 1886d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 189129ba616SKumar Gala 19018af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 1916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 192129ba616SKumar Gala #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 193129ba616SKumar Gala 1946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 1956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 1966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CHECKSUM 1976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 1986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 199129ba616SKumar Gala 2006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 201129ba616SKumar Gala 202129ba616SKumar Gala #define CONFIG_FLASH_CFI_DRIVER 2036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 2046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 206129ba616SKumar Gala 207129ba616SKumar Gala #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 208129ba616SKumar Gala 209129ba616SKumar Gala #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 210129ba616SKumar Gala #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 21118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 21218af1c5fSKumar Gala #define PIXIS_BASE_PHYS 0xfffdf0000ull 21318af1c5fSKumar Gala #else 21452b565f5SKumar Gala #define PIXIS_BASE_PHYS PIXIS_BASE 21518af1c5fSKumar Gala #endif 216129ba616SKumar Gala 21752b565f5SKumar Gala #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 2186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 219129ba616SKumar Gala 220129ba616SKumar Gala #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 221129ba616SKumar Gala #define PIXIS_VER 0x1 /* Board version at offset 1 */ 222129ba616SKumar Gala #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 223129ba616SKumar Gala #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 224129ba616SKumar Gala #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 225129ba616SKumar Gala #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 226129ba616SKumar Gala #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 227129ba616SKumar Gala #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 228129ba616SKumar Gala #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 229129ba616SKumar Gala #define PIXIS_VCTL 0x10 /* VELA Control Register */ 230129ba616SKumar Gala #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 231129ba616SKumar Gala #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 232129ba616SKumar Gala #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 233129ba616SKumar Gala #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 234129ba616SKumar Gala #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 2356bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 2366bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 2376bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 2386bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 2396bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 240129ba616SKumar Gala #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 241129ba616SKumar Gala #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 242129ba616SKumar Gala #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 243129ba616SKumar Gala #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 244129ba616SKumar Gala #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 245129ba616SKumar Gala #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 246129ba616SKumar Gala #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 247129ba616SKumar Gala #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 248129ba616SKumar Gala #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 249129ba616SKumar Gala #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 250129ba616SKumar Gala #define PIXIS_LED 0x25 /* LED Register */ 251129ba616SKumar Gala 252129ba616SKumar Gala /* old pixis referenced names */ 253129ba616SKumar Gala #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 254129ba616SKumar Gala #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 2556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 2567e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC1SER 0x8 2577e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC2SER 0x4 2587e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC3SER 0x2 2597e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC4SER 0x1 2607e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC1SER 0x20 2617e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC2SER 0x20 2627e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC3SER 0x20 2637e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC4SER 0x20 2647e183cadSLiu Yu #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 2657e183cadSLiu Yu | PIXIS_VSPEED2_TSEC2SER \ 2667e183cadSLiu Yu | PIXIS_VSPEED2_TSEC3SER \ 2677e183cadSLiu Yu | PIXIS_VSPEED2_TSEC4SER) 2687e183cadSLiu Yu #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 2697e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC2SER \ 2707e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC3SER \ 2717e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC4SER) 272129ba616SKumar Gala 2736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 2746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 2756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 276129ba616SKumar Gala 2776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 2786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 2796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 280129ba616SKumar Gala 2816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 2826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 283129ba616SKumar Gala 284c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE 0xffa00000 28518af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 28618af1c5fSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 28718af1c5fSKumar Gala #else 288c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 28918af1c5fSKumar Gala #endif 290c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 291c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x40000, \ 292c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x80000,\ 293c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0xC0000} 294c013b749SHaiying Wang #define CONFIG_SYS_MAX_NAND_DEVICE 4 295c013b749SHaiying Wang #define CONFIG_MTD_NAND_VERIFY_WRITE 296c013b749SHaiying Wang #define CONFIG_CMD_NAND 1 297c013b749SHaiying Wang #define CONFIG_NAND_FSL_ELBC 1 298c013b749SHaiying Wang #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 299c013b749SHaiying Wang 300c013b749SHaiying Wang /* NAND flash config */ 30172a9414aSKumar Gala #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 302c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 303c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 304c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 305c013b749SHaiying Wang | BR_V) /* valid */ 306c013b749SHaiying Wang #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 307c013b749SHaiying Wang | OR_FCM_PGS /* Large Page*/ \ 308c013b749SHaiying Wang | OR_FCM_CSCT \ 309c013b749SHaiying Wang | OR_FCM_CST \ 310c013b749SHaiying Wang | OR_FCM_CHT \ 311c013b749SHaiying Wang | OR_FCM_SCY_1 \ 312c013b749SHaiying Wang | OR_FCM_TRLX \ 313c013b749SHaiying Wang | OR_FCM_EHTR) 314c013b749SHaiying Wang 315c013b749SHaiying Wang #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 316c013b749SHaiying Wang #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 317c013b749SHaiying Wang 31872a9414aSKumar Gala #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 319c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 320c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 321c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 322c013b749SHaiying Wang | BR_V) /* valid */ 323c013b749SHaiying Wang #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 32472a9414aSKumar Gala #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 325c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 326c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 327c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 328c013b749SHaiying Wang | BR_V) /* valid */ 329c013b749SHaiying Wang #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 330c013b749SHaiying Wang 33172a9414aSKumar Gala #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 332c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 333c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 334c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 335c013b749SHaiying Wang | BR_V) /* valid */ 336c013b749SHaiying Wang #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 337c013b749SHaiying Wang 338c013b749SHaiying Wang 339129ba616SKumar Gala /* Serial Port - controlled on board with jumper J8 340129ba616SKumar Gala * open - index 2 341129ba616SKumar Gala * shorted - index 1 342129ba616SKumar Gala */ 343129ba616SKumar Gala #define CONFIG_CONS_INDEX 1 344129ba616SKumar Gala #undef CONFIG_SERIAL_SOFTWARE_FIFO 3456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 349129ba616SKumar Gala 3506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 351129ba616SKumar Gala {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 352129ba616SKumar Gala 3536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 3546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 355129ba616SKumar Gala 356129ba616SKumar Gala /* Use the HUSH parser */ 3576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 3586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_HUSH_PARSER 3596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 360129ba616SKumar Gala #endif 361129ba616SKumar Gala 362129ba616SKumar Gala /* 363129ba616SKumar Gala * Pass open firmware flat tree 364129ba616SKumar Gala */ 365129ba616SKumar Gala #define CONFIG_OF_LIBFDT 1 366129ba616SKumar Gala #define CONFIG_OF_BOARD_SETUP 1 367129ba616SKumar Gala #define CONFIG_OF_STDOUT_VIA_ALIAS 1 368129ba616SKumar Gala 369129ba616SKumar Gala /* new uImage format support */ 370129ba616SKumar Gala #define CONFIG_FIT 1 371129ba616SKumar Gala #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 372129ba616SKumar Gala 373129ba616SKumar Gala /* I2C */ 374129ba616SKumar Gala #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 375129ba616SKumar Gala #define CONFIG_HARD_I2C /* I2C with hardware support */ 376129ba616SKumar Gala #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 3771f3ba317SHaiying Wang #define CONFIG_I2C_MULTI_BUS 3786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 3796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 3806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 3816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 3826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 3836d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 384129ba616SKumar Gala 385129ba616SKumar Gala /* 386445a7b38SHaiying Wang * I2C2 EEPROM 387445a7b38SHaiying Wang */ 388445a7b38SHaiying Wang #define CONFIG_ID_EEPROM 389445a7b38SHaiying Wang #ifdef CONFIG_ID_EEPROM 3906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_NXID 391445a7b38SHaiying Wang #endif 3926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 3936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 3946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_EEPROM_BUS_NUM 1 395445a7b38SHaiying Wang 396445a7b38SHaiying Wang /* 397129ba616SKumar Gala * General PCI 398129ba616SKumar Gala * Memory space is mapped 1-1, but I/O space must start from 0. 399129ba616SKumar Gala */ 400129ba616SKumar Gala 401129ba616SKumar Gala /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 4025af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 40318af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 404156984a3SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 40518af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 40618af1c5fSKumar Gala #else 407ad97dce1SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 4085af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 40918af1c5fSKumar Gala #endif 4106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 411aca5f018SKumar Gala #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 4125f91ef6aSKumar Gala #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 41318af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 41418af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 41518af1c5fSKumar Gala #else 4166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 41718af1c5fSKumar Gala #endif 4186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 419129ba616SKumar Gala 420129ba616SKumar Gala /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 4215af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 42218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 423156984a3SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 42418af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 42518af1c5fSKumar Gala #else 426ad97dce1SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 4275af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 42818af1c5fSKumar Gala #endif 4296d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 430aca5f018SKumar Gala #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 4315f91ef6aSKumar Gala #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 43218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 43318af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 43418af1c5fSKumar Gala #else 4356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 43618af1c5fSKumar Gala #endif 4376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 438129ba616SKumar Gala 439129ba616SKumar Gala /* controller 1, Slot 1, tgtid 1, Base address a000 */ 4405af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 44118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 442156984a3SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 44318af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 44418af1c5fSKumar Gala #else 445ad97dce1SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 4465af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 44718af1c5fSKumar Gala #endif 4486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 449aca5f018SKumar Gala #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 4505f91ef6aSKumar Gala #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 45118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 45218af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 45318af1c5fSKumar Gala #else 4546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 45518af1c5fSKumar Gala #endif 4566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 457129ba616SKumar Gala 458129ba616SKumar Gala #if defined(CONFIG_PCI) 459129ba616SKumar Gala 460129ba616SKumar Gala /*PCIE video card used*/ 461aca5f018SKumar Gala #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 462129ba616SKumar Gala 463129ba616SKumar Gala /* video */ 464129ba616SKumar Gala #define CONFIG_VIDEO 465129ba616SKumar Gala 466129ba616SKumar Gala #if defined(CONFIG_VIDEO) 467129ba616SKumar Gala #define CONFIG_BIOSEMU 468129ba616SKumar Gala #define CONFIG_CFB_CONSOLE 469129ba616SKumar Gala #define CONFIG_VIDEO_SW_CURSOR 470129ba616SKumar Gala #define CONFIG_VGA_AS_SINGLE_DEVICE 471129ba616SKumar Gala #define CONFIG_ATI_RADEON_FB 472129ba616SKumar Gala #define CONFIG_VIDEO_LOGO 473129ba616SKumar Gala /*#define CONFIG_CONSOLE_CURSOR*/ 4746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 475129ba616SKumar Gala #endif 476129ba616SKumar Gala 477129ba616SKumar Gala #define CONFIG_NET_MULTI 478129ba616SKumar Gala #define CONFIG_PCI_PNP /* do pci plug-and-play */ 479129ba616SKumar Gala 480129ba616SKumar Gala #undef CONFIG_EEPRO100 481129ba616SKumar Gala #undef CONFIG_TULIP 482129ba616SKumar Gala #undef CONFIG_RTL8139 483129ba616SKumar Gala 484129ba616SKumar Gala #ifndef CONFIG_PCI_PNP 4855f91ef6aSKumar Gala #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 4865f91ef6aSKumar Gala #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 487129ba616SKumar Gala #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 488129ba616SKumar Gala #endif 489129ba616SKumar Gala 490129ba616SKumar Gala #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 491129ba616SKumar Gala #define CONFIG_DOS_PARTITION 492129ba616SKumar Gala #define CONFIG_SCSI_AHCI 493129ba616SKumar Gala 494129ba616SKumar Gala #ifdef CONFIG_SCSI_AHCI 495129ba616SKumar Gala #define CONFIG_SATA_ULI5288 4966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 4976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_LUN 1 4986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 4996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 500129ba616SKumar Gala #endif /* SCSI */ 501129ba616SKumar Gala 502129ba616SKumar Gala #endif /* CONFIG_PCI */ 503129ba616SKumar Gala 504129ba616SKumar Gala 505129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 506129ba616SKumar Gala 507129ba616SKumar Gala #ifndef CONFIG_NET_MULTI 508129ba616SKumar Gala #define CONFIG_NET_MULTI 1 509129ba616SKumar Gala #endif 510129ba616SKumar Gala 511129ba616SKumar Gala #define CONFIG_MII 1 /* MII PHY management */ 512129ba616SKumar Gala #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 513129ba616SKumar Gala #define CONFIG_TSEC1 1 514129ba616SKumar Gala #define CONFIG_TSEC1_NAME "eTSEC1" 515129ba616SKumar Gala #define CONFIG_TSEC2 1 516129ba616SKumar Gala #define CONFIG_TSEC2_NAME "eTSEC2" 517129ba616SKumar Gala #define CONFIG_TSEC3 1 518129ba616SKumar Gala #define CONFIG_TSEC3_NAME "eTSEC3" 519129ba616SKumar Gala #define CONFIG_TSEC4 1 520129ba616SKumar Gala #define CONFIG_TSEC4_NAME "eTSEC4" 521129ba616SKumar Gala 5227e183cadSLiu Yu #define CONFIG_PIXIS_SGMII_CMD 5237e183cadSLiu Yu #define CONFIG_FSL_SGMII_RISER 1 5247e183cadSLiu Yu #define SGMII_RISER_PHY_OFFSET 0x1c 5257e183cadSLiu Yu 5267e183cadSLiu Yu #ifdef CONFIG_FSL_SGMII_RISER 5277e183cadSLiu Yu #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 5287e183cadSLiu Yu #endif 5297e183cadSLiu Yu 530129ba616SKumar Gala #define TSEC1_PHY_ADDR 0 531129ba616SKumar Gala #define TSEC2_PHY_ADDR 1 532129ba616SKumar Gala #define TSEC3_PHY_ADDR 2 533129ba616SKumar Gala #define TSEC4_PHY_ADDR 3 534129ba616SKumar Gala 535129ba616SKumar Gala #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 536129ba616SKumar Gala #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 537129ba616SKumar Gala #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 538129ba616SKumar Gala #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 539129ba616SKumar Gala 540129ba616SKumar Gala #define TSEC1_PHYIDX 0 541129ba616SKumar Gala #define TSEC2_PHYIDX 0 542129ba616SKumar Gala #define TSEC3_PHYIDX 0 543129ba616SKumar Gala #define TSEC4_PHYIDX 0 544129ba616SKumar Gala 545129ba616SKumar Gala #define CONFIG_ETHPRIME "eTSEC1" 546129ba616SKumar Gala 547129ba616SKumar Gala #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 548129ba616SKumar Gala #endif /* CONFIG_TSEC_ENET */ 549129ba616SKumar Gala 550129ba616SKumar Gala /* 551129ba616SKumar Gala * Environment 552129ba616SKumar Gala */ 5535a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 5546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 5550e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR 0xfff80000 556129ba616SKumar Gala #else 5576fc110bdSHaiying Wang #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 558129ba616SKumar Gala #endif 5590e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 5600e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 561129ba616SKumar Gala 562129ba616SKumar Gala #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 5636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 564129ba616SKumar Gala 565129ba616SKumar Gala /* 566129ba616SKumar Gala * Command line configuration. 567129ba616SKumar Gala */ 568129ba616SKumar Gala #include <config_cmd_default.h> 569129ba616SKumar Gala 570129ba616SKumar Gala #define CONFIG_CMD_IRQ 571129ba616SKumar Gala #define CONFIG_CMD_PING 572129ba616SKumar Gala #define CONFIG_CMD_I2C 573129ba616SKumar Gala #define CONFIG_CMD_MII 574129ba616SKumar Gala #define CONFIG_CMD_ELF 5751c9aa76bSKumar Gala #define CONFIG_CMD_IRQ 5761c9aa76bSKumar Gala #define CONFIG_CMD_SETEXPR 577*199e262eSBecky Bruce #define CONFIG_CMD_REGINFO 578129ba616SKumar Gala 579129ba616SKumar Gala #if defined(CONFIG_PCI) 580129ba616SKumar Gala #define CONFIG_CMD_PCI 581129ba616SKumar Gala #define CONFIG_CMD_NET 582129ba616SKumar Gala #define CONFIG_CMD_SCSI 583129ba616SKumar Gala #define CONFIG_CMD_EXT2 584129ba616SKumar Gala #endif 585129ba616SKumar Gala 586129ba616SKumar Gala #undef CONFIG_WATCHDOG /* watchdog disabled */ 587129ba616SKumar Gala 588129ba616SKumar Gala /* 589129ba616SKumar Gala * Miscellaneous configurable options 590129ba616SKumar Gala */ 5916d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 592129ba616SKumar Gala #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 5936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 5946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 595129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 5966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 597129ba616SKumar Gala #else 5986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 599129ba616SKumar Gala #endif 6006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 6016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 6026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 6036d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 604129ba616SKumar Gala 605129ba616SKumar Gala /* 606129ba616SKumar Gala * For booting Linux, the board info and command line data 60789188a62SKumar Gala * have to be in the first 16 MB of memory, since this is 608129ba616SKumar Gala * the maximum mapped by the Linux kernel during initialization. 609129ba616SKumar Gala */ 61089188a62SKumar Gala #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 611129ba616SKumar Gala 612129ba616SKumar Gala /* 613129ba616SKumar Gala * Internal Definitions 614129ba616SKumar Gala * 615129ba616SKumar Gala * Boot Flags 616129ba616SKumar Gala */ 617129ba616SKumar Gala #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 618129ba616SKumar Gala #define BOOTFLAG_WARM 0x02 /* Software reboot */ 619129ba616SKumar Gala 620129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 621129ba616SKumar Gala #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 622129ba616SKumar Gala #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 623129ba616SKumar Gala #endif 624129ba616SKumar Gala 625129ba616SKumar Gala /* 626129ba616SKumar Gala * Environment Configuration 627129ba616SKumar Gala */ 628129ba616SKumar Gala 629129ba616SKumar Gala /* The mac addresses for all ethernet interface */ 630129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 631129ba616SKumar Gala #define CONFIG_HAS_ETH0 632129ba616SKumar Gala #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 633129ba616SKumar Gala #define CONFIG_HAS_ETH1 634129ba616SKumar Gala #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 635129ba616SKumar Gala #define CONFIG_HAS_ETH2 636129ba616SKumar Gala #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 637129ba616SKumar Gala #define CONFIG_HAS_ETH3 638129ba616SKumar Gala #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 639129ba616SKumar Gala #endif 640129ba616SKumar Gala 641129ba616SKumar Gala #define CONFIG_IPADDR 192.168.1.254 642129ba616SKumar Gala 643129ba616SKumar Gala #define CONFIG_HOSTNAME unknown 644129ba616SKumar Gala #define CONFIG_ROOTPATH /opt/nfsroot 645129ba616SKumar Gala #define CONFIG_BOOTFILE uImage 646129ba616SKumar Gala #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 647129ba616SKumar Gala 648129ba616SKumar Gala #define CONFIG_SERVERIP 192.168.1.1 649129ba616SKumar Gala #define CONFIG_GATEWAYIP 192.168.1.1 650129ba616SKumar Gala #define CONFIG_NETMASK 255.255.255.0 651129ba616SKumar Gala 652129ba616SKumar Gala /* default location for tftp and bootm */ 653129ba616SKumar Gala #define CONFIG_LOADADDR 1000000 654129ba616SKumar Gala 655129ba616SKumar Gala #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 656129ba616SKumar Gala #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 657129ba616SKumar Gala 658129ba616SKumar Gala #define CONFIG_BAUDRATE 115200 659129ba616SKumar Gala 660129ba616SKumar Gala #define CONFIG_EXTRA_ENV_SETTINGS \ 6614ca06607SHaiying Wang "memctl_intlv_ctl=2\0" \ 662129ba616SKumar Gala "netdev=eth0\0" \ 663129ba616SKumar Gala "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 664129ba616SKumar Gala "tftpflash=tftpboot $loadaddr $uboot; " \ 665129ba616SKumar Gala "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 666129ba616SKumar Gala "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 667129ba616SKumar Gala "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 668129ba616SKumar Gala "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 669129ba616SKumar Gala "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 670129ba616SKumar Gala "consoledev=ttyS0\0" \ 671129ba616SKumar Gala "ramdiskaddr=2000000\0" \ 672129ba616SKumar Gala "ramdiskfile=8572ds/ramdisk.uboot\0" \ 673129ba616SKumar Gala "fdtaddr=c00000\0" \ 674129ba616SKumar Gala "fdtfile=8572ds/mpc8572ds.dtb\0" \ 675129ba616SKumar Gala "bdev=sda3\0" 676129ba616SKumar Gala 677129ba616SKumar Gala #define CONFIG_HDBOOT \ 678129ba616SKumar Gala "setenv bootargs root=/dev/$bdev rw " \ 679129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 680129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 681129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 682129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 683129ba616SKumar Gala 684129ba616SKumar Gala #define CONFIG_NFSBOOTCOMMAND \ 685129ba616SKumar Gala "setenv bootargs root=/dev/nfs rw " \ 686129ba616SKumar Gala "nfsroot=$serverip:$rootpath " \ 687129ba616SKumar Gala "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 688129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 689129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 690129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 691129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 692129ba616SKumar Gala 693129ba616SKumar Gala #define CONFIG_RAMBOOTCOMMAND \ 694129ba616SKumar Gala "setenv bootargs root=/dev/ram rw " \ 695129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 696129ba616SKumar Gala "tftp $ramdiskaddr $ramdiskfile;" \ 697129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 698129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 699129ba616SKumar Gala "bootm $loadaddr $ramdiskaddr $fdtaddr" 700129ba616SKumar Gala 701129ba616SKumar Gala #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 702129ba616SKumar Gala 703129ba616SKumar Gala #endif /* __CONFIG_H */ 704