1129ba616SKumar Gala /* 2509c4c4cSKumar Gala * Copyright 2007-2008,2010 Freescale Semiconductor, Inc. 3129ba616SKumar Gala * 4129ba616SKumar Gala * See file CREDITS for list of people who contributed to this 5129ba616SKumar Gala * project. 6129ba616SKumar Gala * 7129ba616SKumar Gala * This program is free software; you can redistribute it and/or 8129ba616SKumar Gala * modify it under the terms of the GNU General Public License as 9129ba616SKumar Gala * published by the Free Software Foundation; either version 2 of 10129ba616SKumar Gala * the License, or (at your option) any later version. 11129ba616SKumar Gala * 12129ba616SKumar Gala * This program is distributed in the hope that it will be useful, 13129ba616SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 14129ba616SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15129ba616SKumar Gala * GNU General Public License for more details. 16129ba616SKumar Gala * 17129ba616SKumar Gala * You should have received a copy of the GNU General Public License 18129ba616SKumar Gala * along with this program; if not, write to the Free Software 19129ba616SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20129ba616SKumar Gala * MA 02111-1307 USA 21129ba616SKumar Gala */ 22129ba616SKumar Gala 23129ba616SKumar Gala /* 24129ba616SKumar Gala * mpc8572ds board configuration file 25129ba616SKumar Gala * 26129ba616SKumar Gala */ 27129ba616SKumar Gala #ifndef __CONFIG_H 28129ba616SKumar Gala #define __CONFIG_H 29129ba616SKumar Gala 30509c4c4cSKumar Gala #include "../board/freescale/common/ics307_clk.h" 31509c4c4cSKumar Gala 32d24f2d32SWolfgang Denk #ifdef CONFIG_36BIT 33f9edcc10SKumar Gala #define CONFIG_PHYS_64BIT 34f9edcc10SKumar Gala #endif 35f9edcc10SKumar Gala 36cb14e93bSKumar Gala #ifdef CONFIG_NAND 37cb14e93bSKumar Gala #define CONFIG_NAND_U_BOOT 38cb14e93bSKumar Gala #define CONFIG_RAMBOOT_NAND 39cb14e93bSKumar Gala #ifdef CONFIG_NAND_SPL 40cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 41cb14e93bSKumar Gala #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 42cb14e93bSKumar Gala #else 43cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE 0xf8f82000 44cb14e93bSKumar Gala #endif /* CONFIG_NAND_SPL */ 45cb14e93bSKumar Gala #endif 46cb14e93bSKumar Gala 47cb14e93bSKumar Gala #ifndef CONFIG_SYS_TEXT_BASE 48cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE 0xeff80000 49cb14e93bSKumar Gala #endif 50cb14e93bSKumar Gala 51cb14e93bSKumar Gala #ifndef CONFIG_SYS_MONITOR_BASE 52cb14e93bSKumar Gala #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 53cb14e93bSKumar Gala #endif 54cb14e93bSKumar Gala 55129ba616SKumar Gala /* High Level Configuration Options */ 56129ba616SKumar Gala #define CONFIG_BOOKE 1 /* BOOKE */ 57129ba616SKumar Gala #define CONFIG_E500 1 /* BOOKE e500 family */ 58129ba616SKumar Gala #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 59129ba616SKumar Gala #define CONFIG_MPC8572 1 60129ba616SKumar Gala #define CONFIG_MPC8572DS 1 61129ba616SKumar Gala #define CONFIG_MP 1 /* support multiple processors */ 62129ba616SKumar Gala 63c51fc5d5SKumar Gala #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 64129ba616SKumar Gala #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 65129ba616SKumar Gala #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 66129ba616SKumar Gala #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 67129ba616SKumar Gala #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 68129ba616SKumar Gala #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 69129ba616SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 700151cbacSKumar Gala #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 71129ba616SKumar Gala 72129ba616SKumar Gala #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 73129ba616SKumar Gala 74129ba616SKumar Gala #define CONFIG_TSEC_ENET /* tsec ethernet support */ 75129ba616SKumar Gala #define CONFIG_ENV_OVERWRITE 76129ba616SKumar Gala 77509c4c4cSKumar Gala #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 78509c4c4cSKumar Gala #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 794ca06607SHaiying Wang #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 80129ba616SKumar Gala 81129ba616SKumar Gala /* 82129ba616SKumar Gala * These can be toggled for performance analysis, otherwise use default. 83129ba616SKumar Gala */ 84129ba616SKumar Gala #define CONFIG_L2_CACHE /* toggle L2 cache */ 85129ba616SKumar Gala #define CONFIG_BTB /* toggle branch predition */ 86129ba616SKumar Gala 87129ba616SKumar Gala #define CONFIG_ENABLE_36BIT_PHYS 1 88129ba616SKumar Gala 8918af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 9018af1c5fSKumar Gala #define CONFIG_ADDR_MAP 1 9118af1c5fSKumar Gala #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 9218af1c5fSKumar Gala #endif 9318af1c5fSKumar Gala 946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x7fffffff 96129ba616SKumar Gala #define CONFIG_PANIC_HANG /* do not reset board on panic */ 97129ba616SKumar Gala 98129ba616SKumar Gala /* 99cb14e93bSKumar Gala * Config the L2 Cache as L2 SRAM 100cb14e93bSKumar Gala */ 101cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 102cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 103cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 104cb14e93bSKumar Gala #else 105cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 106cb14e93bSKumar Gala #endif 107cb14e93bSKumar Gala #define CONFIG_SYS_L2_SIZE (512 << 10) 108cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 109cb14e93bSKumar Gala 110cb14e93bSKumar Gala /* 111129ba616SKumar Gala * Base addresses -- Note these are effective addresses where the 112129ba616SKumar Gala * actual resources get mapped (not physical addresses) 113129ba616SKumar Gala */ 1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 11518af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 11618af1c5fSKumar Gala #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ 11718af1c5fSKumar Gala #else 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 11918af1c5fSKumar Gala #endif 1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 121129ba616SKumar Gala 122cb14e93bSKumar Gala #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) 123cb14e93bSKumar Gala #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR 124cb14e93bSKumar Gala #else 125cb14e93bSKumar Gala #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 126cb14e93bSKumar Gala #endif 127cb14e93bSKumar Gala 128129ba616SKumar Gala /* DDR Setup */ 129f8523cb0SKumar Gala #define CONFIG_VERY_BIG_RAM 130129ba616SKumar Gala #define CONFIG_FSL_DDR2 131129ba616SKumar Gala #undef CONFIG_FSL_DDR_INTERACTIVE 132129ba616SKumar Gala #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 133129ba616SKumar Gala #define CONFIG_DDR_SPD 134129ba616SKumar Gala 1359b0ad1b1SDave Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 136129ba616SKumar Gala #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 137129ba616SKumar Gala 1386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 1396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 140129ba616SKumar Gala 141129ba616SKumar Gala #define CONFIG_NUM_DDR_CONTROLLERS 2 142129ba616SKumar Gala #define CONFIG_DIMM_SLOTS_PER_CTLR 1 143129ba616SKumar Gala #define CONFIG_CHIP_SELECTS_PER_CTRL 2 144129ba616SKumar Gala 145129ba616SKumar Gala /* I2C addresses of SPD EEPROMs */ 1466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 147129ba616SKumar Gala #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 148129ba616SKumar Gala #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 149129ba616SKumar Gala 150129ba616SKumar Gala /* These are used when DDR doesn't use SPD. */ 151dc889e86SDave Liu #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 1526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 153dc889e86SDave Liu #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 154dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_3 0x00020000 1556d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 0x00260802 156dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 157dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 158dc889e86SDave Liu #define CONFIG_SYS_DDR_MODE_1 0x00440462 1596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x00000000 160dc889e86SDave Liu #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 1616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 162dc889e86SDave Liu #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 1636d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 1646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 165dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 166dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL2 0x24400000 167129ba616SKumar Gala 1686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 1696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 1706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SBE 0x00010000 171129ba616SKumar Gala 172129ba616SKumar Gala /* 173129ba616SKumar Gala * Make sure required options are set 174129ba616SKumar Gala */ 175129ba616SKumar Gala #ifndef CONFIG_SPD_EEPROM 176129ba616SKumar Gala #error ("CONFIG_SPD_EEPROM is required") 177129ba616SKumar Gala #endif 178129ba616SKumar Gala 179129ba616SKumar Gala #undef CONFIG_CLOCKS_IN_MHZ 180129ba616SKumar Gala 181129ba616SKumar Gala /* 182129ba616SKumar Gala * Memory map 183129ba616SKumar Gala * 184129ba616SKumar Gala * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 185129ba616SKumar Gala * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 186129ba616SKumar Gala * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 187129ba616SKumar Gala * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 188129ba616SKumar Gala * 189129ba616SKumar Gala * Localbus cacheable (TBD) 190129ba616SKumar Gala * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 191129ba616SKumar Gala * 192129ba616SKumar Gala * Localbus non-cacheable 193129ba616SKumar Gala * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 194129ba616SKumar Gala * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 195c013b749SHaiying Wang * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 196129ba616SKumar Gala * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 197129ba616SKumar Gala * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 198129ba616SKumar Gala * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 199129ba616SKumar Gala */ 200129ba616SKumar Gala 201129ba616SKumar Gala /* 202129ba616SKumar Gala * Local Bus Definitions 203129ba616SKumar Gala */ 2046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 20518af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 20618af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 20718af1c5fSKumar Gala #else 208c953ddfdSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 20918af1c5fSKumar Gala #endif 210129ba616SKumar Gala 211cb14e93bSKumar Gala 212cb14e93bSKumar Gala #define CONFIG_FLASH_BR_PRELIM \ 213cb14e93bSKumar Gala (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ 214cb14e93bSKumar Gala | BR_PS_16 | BR_V) 215cb14e93bSKumar Gala #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 216129ba616SKumar Gala 217c953ddfdSKumar Gala #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 2186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 219129ba616SKumar Gala 22018af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 222129ba616SKumar Gala #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 223129ba616SKumar Gala 2246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 2256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 2266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CHECKSUM 2276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 229129ba616SKumar Gala 230cb14e93bSKumar Gala #if defined(CONFIG_RAMBOOT_NAND) 231cb14e93bSKumar Gala #define CONFIG_SYS_RAMBOOT 232cb14e93bSKumar Gala #define CONFIG_SYS_EXTRA_ENV_RELOC 233cb14e93bSKumar Gala #else 234cb14e93bSKumar Gala #undef CONFIG_SYS_RAMBOOT 235cb14e93bSKumar Gala #endif 236129ba616SKumar Gala 237129ba616SKumar Gala #define CONFIG_FLASH_CFI_DRIVER 2386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 2396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 2406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 241129ba616SKumar Gala 242129ba616SKumar Gala #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 243129ba616SKumar Gala 244558710b9SKumar Gala #define CONFIG_HWCONFIG /* enable hwconfig */ 245129ba616SKumar Gala #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 246129ba616SKumar Gala #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 24718af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 24818af1c5fSKumar Gala #define PIXIS_BASE_PHYS 0xfffdf0000ull 24918af1c5fSKumar Gala #else 25052b565f5SKumar Gala #define PIXIS_BASE_PHYS PIXIS_BASE 25118af1c5fSKumar Gala #endif 252129ba616SKumar Gala 25352b565f5SKumar Gala #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 2546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 255129ba616SKumar Gala 256129ba616SKumar Gala #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 257129ba616SKumar Gala #define PIXIS_VER 0x1 /* Board version at offset 1 */ 258129ba616SKumar Gala #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 259129ba616SKumar Gala #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 260129ba616SKumar Gala #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 261129ba616SKumar Gala #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 262129ba616SKumar Gala #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 263129ba616SKumar Gala #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 264129ba616SKumar Gala #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 265129ba616SKumar Gala #define PIXIS_VCTL 0x10 /* VELA Control Register */ 266129ba616SKumar Gala #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 267129ba616SKumar Gala #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 268129ba616SKumar Gala #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 269129ba616SKumar Gala #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 270129ba616SKumar Gala #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 2716bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 2726bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 2736bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 2746bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 2756bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 276129ba616SKumar Gala #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 277129ba616SKumar Gala #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 278129ba616SKumar Gala #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 279129ba616SKumar Gala #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 280129ba616SKumar Gala #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 281129ba616SKumar Gala #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 282129ba616SKumar Gala #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 283129ba616SKumar Gala #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 284129ba616SKumar Gala #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 285129ba616SKumar Gala #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 286129ba616SKumar Gala #define PIXIS_LED 0x25 /* LED Register */ 287129ba616SKumar Gala 288cb14e93bSKumar Gala #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 289cb14e93bSKumar Gala 290129ba616SKumar Gala /* old pixis referenced names */ 291129ba616SKumar Gala #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 292129ba616SKumar Gala #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 2936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 2947e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC1SER 0x8 2957e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC2SER 0x4 2967e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC3SER 0x2 2977e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC4SER 0x1 2987e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC1SER 0x20 2997e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC2SER 0x20 3007e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC3SER 0x20 3017e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC4SER 0x20 3027e183cadSLiu Yu #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 3037e183cadSLiu Yu | PIXIS_VSPEED2_TSEC2SER \ 3047e183cadSLiu Yu | PIXIS_VSPEED2_TSEC3SER \ 3057e183cadSLiu Yu | PIXIS_VSPEED2_TSEC4SER) 3067e183cadSLiu Yu #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 3077e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC2SER \ 3087e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC3SER \ 3097e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC4SER) 310129ba616SKumar Gala 3116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 3126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 313553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 314129ba616SKumar Gala 31525ddd1fbSWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 3166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 317129ba616SKumar Gala 3186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 3196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 320129ba616SKumar Gala 321cb14e93bSKumar Gala #ifndef CONFIG_NAND_SPL 322c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE 0xffa00000 32318af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 32418af1c5fSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 32518af1c5fSKumar Gala #else 326c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 32718af1c5fSKumar Gala #endif 328cb14e93bSKumar Gala #else 329cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE 0xfff00000 330cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 331cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 332cb14e93bSKumar Gala #else 333cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 334cb14e93bSKumar Gala #endif 335cb14e93bSKumar Gala #endif 336cb14e93bSKumar Gala 337c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 338c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x40000, \ 339c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x80000,\ 340c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0xC0000} 341c013b749SHaiying Wang #define CONFIG_SYS_MAX_NAND_DEVICE 4 342c013b749SHaiying Wang #define CONFIG_MTD_NAND_VERIFY_WRITE 343c013b749SHaiying Wang #define CONFIG_CMD_NAND 1 344c013b749SHaiying Wang #define CONFIG_NAND_FSL_ELBC 1 345c013b749SHaiying Wang #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 346c013b749SHaiying Wang 347cb14e93bSKumar Gala /* NAND boot: 4K NAND loader config */ 348cb14e93bSKumar Gala #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 349cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 350cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 351cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_START \ 352cb14e93bSKumar Gala (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 353cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 354cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 355cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 356cb14e93bSKumar Gala 357cb14e93bSKumar Gala 358c013b749SHaiying Wang /* NAND flash config */ 35972a9414aSKumar Gala #define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 360c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 361c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 362c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 363c013b749SHaiying Wang | BR_V) /* valid */ 364c013b749SHaiying Wang #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 365c013b749SHaiying Wang | OR_FCM_PGS /* Large Page*/ \ 366c013b749SHaiying Wang | OR_FCM_CSCT \ 367c013b749SHaiying Wang | OR_FCM_CST \ 368c013b749SHaiying Wang | OR_FCM_CHT \ 369c013b749SHaiying Wang | OR_FCM_SCY_1 \ 370c013b749SHaiying Wang | OR_FCM_TRLX \ 371c013b749SHaiying Wang | OR_FCM_EHTR) 372c013b749SHaiying Wang 373cb14e93bSKumar Gala #ifdef CONFIG_RAMBOOT_NAND 374cb14e93bSKumar Gala #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 375cb14e93bSKumar Gala #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 376cb14e93bSKumar Gala #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 377cb14e93bSKumar Gala #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 378cb14e93bSKumar Gala #else 379cb14e93bSKumar Gala #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 380cb14e93bSKumar Gala #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 381c013b749SHaiying Wang #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 382c013b749SHaiying Wang #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 383cb14e93bSKumar Gala #endif 38472a9414aSKumar Gala #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ 385c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 386c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 387c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 388c013b749SHaiying Wang | BR_V) /* valid */ 389c013b749SHaiying Wang #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 39072a9414aSKumar Gala #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ 391c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 392c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 393c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 394c013b749SHaiying Wang | BR_V) /* valid */ 395c013b749SHaiying Wang #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 396c013b749SHaiying Wang 39772a9414aSKumar Gala #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ 398c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 399c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 400c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 401c013b749SHaiying Wang | BR_V) /* valid */ 402c013b749SHaiying Wang #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 403c013b749SHaiying Wang 404c013b749SHaiying Wang 405129ba616SKumar Gala /* Serial Port - controlled on board with jumper J8 406129ba616SKumar Gala * open - index 2 407129ba616SKumar Gala * shorted - index 1 408129ba616SKumar Gala */ 409129ba616SKumar Gala #define CONFIG_CONS_INDEX 1 4106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 4116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 4126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 4136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 414cb14e93bSKumar Gala #ifdef CONFIG_NAND_SPL 415cb14e93bSKumar Gala #define CONFIG_NS16550_MIN_FUNCTIONS 416cb14e93bSKumar Gala #endif 417129ba616SKumar Gala 4186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 419129ba616SKumar Gala {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 420129ba616SKumar Gala 4216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 4226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 423129ba616SKumar Gala 424129ba616SKumar Gala /* Use the HUSH parser */ 4256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 4266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_HUSH_PARSER 4276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 428129ba616SKumar Gala #endif 429129ba616SKumar Gala 430129ba616SKumar Gala /* 431129ba616SKumar Gala * Pass open firmware flat tree 432129ba616SKumar Gala */ 433129ba616SKumar Gala #define CONFIG_OF_LIBFDT 1 434129ba616SKumar Gala #define CONFIG_OF_BOARD_SETUP 1 435129ba616SKumar Gala #define CONFIG_OF_STDOUT_VIA_ALIAS 1 436129ba616SKumar Gala 437129ba616SKumar Gala /* new uImage format support */ 438129ba616SKumar Gala #define CONFIG_FIT 1 439129ba616SKumar Gala #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 440129ba616SKumar Gala 441129ba616SKumar Gala /* I2C */ 442129ba616SKumar Gala #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 443129ba616SKumar Gala #define CONFIG_HARD_I2C /* I2C with hardware support */ 444129ba616SKumar Gala #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 4451f3ba317SHaiying Wang #define CONFIG_I2C_MULTI_BUS 4466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 4476d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 4486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_SLAVE 0x7F 4496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ 4506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_OFFSET 0x3000 4516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C2_OFFSET 0x3100 452129ba616SKumar Gala 453129ba616SKumar Gala /* 454445a7b38SHaiying Wang * I2C2 EEPROM 455445a7b38SHaiying Wang */ 456445a7b38SHaiying Wang #define CONFIG_ID_EEPROM 457445a7b38SHaiying Wang #ifdef CONFIG_ID_EEPROM 4586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_NXID 459445a7b38SHaiying Wang #endif 4606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 4616d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 4626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_EEPROM_BUS_NUM 1 463445a7b38SHaiying Wang 464445a7b38SHaiying Wang /* 465129ba616SKumar Gala * General PCI 466129ba616SKumar Gala * Memory space is mapped 1-1, but I/O space must start from 0. 467129ba616SKumar Gala */ 468129ba616SKumar Gala 469129ba616SKumar Gala /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 470*18ea5551SKumar Gala #define CONFIG_SYS_PCIE3_NAME "ULI" 4715af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 47218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 473156984a3SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 47418af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 47518af1c5fSKumar Gala #else 476ad97dce1SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 4775af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 47818af1c5fSKumar Gala #endif 4796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 480aca5f018SKumar Gala #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 4815f91ef6aSKumar Gala #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 48218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 48318af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 48418af1c5fSKumar Gala #else 4856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 48618af1c5fSKumar Gala #endif 4876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 488129ba616SKumar Gala 489129ba616SKumar Gala /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 490*18ea5551SKumar Gala #define CONFIG_SYS_PCIE2_NAME "Slot 1" 4915af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 49218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 493156984a3SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 49418af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 49518af1c5fSKumar Gala #else 496ad97dce1SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 4975af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 49818af1c5fSKumar Gala #endif 4996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 500aca5f018SKumar Gala #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 5015f91ef6aSKumar Gala #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 50218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 50318af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 50418af1c5fSKumar Gala #else 5056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 50618af1c5fSKumar Gala #endif 5076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 508129ba616SKumar Gala 509129ba616SKumar Gala /* controller 1, Slot 1, tgtid 1, Base address a000 */ 510*18ea5551SKumar Gala #define CONFIG_SYS_PCIE1_NAME "Slot 2" 5115af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 51218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 513156984a3SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 51418af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 51518af1c5fSKumar Gala #else 516ad97dce1SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 5175af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 51818af1c5fSKumar Gala #endif 5196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 520aca5f018SKumar Gala #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 5215f91ef6aSKumar Gala #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 52218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 52318af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 52418af1c5fSKumar Gala #else 5256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 52618af1c5fSKumar Gala #endif 5276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 528129ba616SKumar Gala 529129ba616SKumar Gala #if defined(CONFIG_PCI) 530129ba616SKumar Gala 531129ba616SKumar Gala /*PCIE video card used*/ 532aca5f018SKumar Gala #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 533129ba616SKumar Gala 534129ba616SKumar Gala /* video */ 535129ba616SKumar Gala #define CONFIG_VIDEO 536129ba616SKumar Gala 537129ba616SKumar Gala #if defined(CONFIG_VIDEO) 538129ba616SKumar Gala #define CONFIG_BIOSEMU 539129ba616SKumar Gala #define CONFIG_CFB_CONSOLE 540129ba616SKumar Gala #define CONFIG_VIDEO_SW_CURSOR 541129ba616SKumar Gala #define CONFIG_VGA_AS_SINGLE_DEVICE 542129ba616SKumar Gala #define CONFIG_ATI_RADEON_FB 543129ba616SKumar Gala #define CONFIG_VIDEO_LOGO 544129ba616SKumar Gala /*#define CONFIG_CONSOLE_CURSOR*/ 5456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 546129ba616SKumar Gala #endif 547129ba616SKumar Gala 548129ba616SKumar Gala #define CONFIG_NET_MULTI 549129ba616SKumar Gala #define CONFIG_PCI_PNP /* do pci plug-and-play */ 550129ba616SKumar Gala 551129ba616SKumar Gala #undef CONFIG_EEPRO100 552129ba616SKumar Gala #undef CONFIG_TULIP 553129ba616SKumar Gala #undef CONFIG_RTL8139 55416855ec1SKumar Gala #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 555129ba616SKumar Gala 556129ba616SKumar Gala #ifndef CONFIG_PCI_PNP 5575f91ef6aSKumar Gala #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 5585f91ef6aSKumar Gala #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 559129ba616SKumar Gala #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 560129ba616SKumar Gala #endif 561129ba616SKumar Gala 562129ba616SKumar Gala #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 563129ba616SKumar Gala #define CONFIG_DOS_PARTITION 564129ba616SKumar Gala #define CONFIG_SCSI_AHCI 565129ba616SKumar Gala 566129ba616SKumar Gala #ifdef CONFIG_SCSI_AHCI 567129ba616SKumar Gala #define CONFIG_SATA_ULI5288 5686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 5696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_LUN 1 5706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 5716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 572129ba616SKumar Gala #endif /* SCSI */ 573129ba616SKumar Gala 574129ba616SKumar Gala #endif /* CONFIG_PCI */ 575129ba616SKumar Gala 576129ba616SKumar Gala 577129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 578129ba616SKumar Gala 579129ba616SKumar Gala #ifndef CONFIG_NET_MULTI 580129ba616SKumar Gala #define CONFIG_NET_MULTI 1 581129ba616SKumar Gala #endif 582129ba616SKumar Gala 583129ba616SKumar Gala #define CONFIG_MII 1 /* MII PHY management */ 584129ba616SKumar Gala #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 585129ba616SKumar Gala #define CONFIG_TSEC1 1 586129ba616SKumar Gala #define CONFIG_TSEC1_NAME "eTSEC1" 587129ba616SKumar Gala #define CONFIG_TSEC2 1 588129ba616SKumar Gala #define CONFIG_TSEC2_NAME "eTSEC2" 589129ba616SKumar Gala #define CONFIG_TSEC3 1 590129ba616SKumar Gala #define CONFIG_TSEC3_NAME "eTSEC3" 591129ba616SKumar Gala #define CONFIG_TSEC4 1 592129ba616SKumar Gala #define CONFIG_TSEC4_NAME "eTSEC4" 593129ba616SKumar Gala 5947e183cadSLiu Yu #define CONFIG_PIXIS_SGMII_CMD 5957e183cadSLiu Yu #define CONFIG_FSL_SGMII_RISER 1 5967e183cadSLiu Yu #define SGMII_RISER_PHY_OFFSET 0x1c 5977e183cadSLiu Yu 5987e183cadSLiu Yu #ifdef CONFIG_FSL_SGMII_RISER 5997e183cadSLiu Yu #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 6007e183cadSLiu Yu #endif 6017e183cadSLiu Yu 602129ba616SKumar Gala #define TSEC1_PHY_ADDR 0 603129ba616SKumar Gala #define TSEC2_PHY_ADDR 1 604129ba616SKumar Gala #define TSEC3_PHY_ADDR 2 605129ba616SKumar Gala #define TSEC4_PHY_ADDR 3 606129ba616SKumar Gala 607129ba616SKumar Gala #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 608129ba616SKumar Gala #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 609129ba616SKumar Gala #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 610129ba616SKumar Gala #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 611129ba616SKumar Gala 612129ba616SKumar Gala #define TSEC1_PHYIDX 0 613129ba616SKumar Gala #define TSEC2_PHYIDX 0 614129ba616SKumar Gala #define TSEC3_PHYIDX 0 615129ba616SKumar Gala #define TSEC4_PHYIDX 0 616129ba616SKumar Gala 617129ba616SKumar Gala #define CONFIG_ETHPRIME "eTSEC1" 618129ba616SKumar Gala 619129ba616SKumar Gala #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 620129ba616SKumar Gala #endif /* CONFIG_TSEC_ENET */ 621129ba616SKumar Gala 622129ba616SKumar Gala /* 623129ba616SKumar Gala * Environment 624129ba616SKumar Gala */ 625cb14e93bSKumar Gala 626cb14e93bSKumar Gala #if defined(CONFIG_SYS_RAMBOOT) 627cb14e93bSKumar Gala #if defined(CONFIG_RAMBOOT_NAND) 628cb14e93bSKumar Gala #define CONFIG_ENV_IS_IN_NAND 1 629cb14e93bSKumar Gala #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 630cb14e93bSKumar Gala #define CONFIG_ENV_OFFSET ((512 * 1024)\ 631cb14e93bSKumar Gala + CONFIG_SYS_NAND_BLOCK_SIZE) 632cb14e93bSKumar Gala #endif 633cb14e93bSKumar Gala 634cb14e93bSKumar Gala #else 6355a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 6366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 6370e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR 0xfff80000 638129ba616SKumar Gala #else 6396fc110bdSHaiying Wang #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 640129ba616SKumar Gala #endif 6410e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 6420e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 643cb14e93bSKumar Gala #endif 644129ba616SKumar Gala 645129ba616SKumar Gala #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 6466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 647129ba616SKumar Gala 648129ba616SKumar Gala /* 649129ba616SKumar Gala * Command line configuration. 650129ba616SKumar Gala */ 651129ba616SKumar Gala #include <config_cmd_default.h> 652129ba616SKumar Gala 653129ba616SKumar Gala #define CONFIG_CMD_IRQ 654129ba616SKumar Gala #define CONFIG_CMD_PING 655129ba616SKumar Gala #define CONFIG_CMD_I2C 656129ba616SKumar Gala #define CONFIG_CMD_MII 657129ba616SKumar Gala #define CONFIG_CMD_ELF 6581c9aa76bSKumar Gala #define CONFIG_CMD_IRQ 6591c9aa76bSKumar Gala #define CONFIG_CMD_SETEXPR 660199e262eSBecky Bruce #define CONFIG_CMD_REGINFO 661129ba616SKumar Gala 662129ba616SKumar Gala #if defined(CONFIG_PCI) 663129ba616SKumar Gala #define CONFIG_CMD_PCI 664129ba616SKumar Gala #define CONFIG_CMD_NET 665129ba616SKumar Gala #define CONFIG_CMD_SCSI 666129ba616SKumar Gala #define CONFIG_CMD_EXT2 667129ba616SKumar Gala #endif 668129ba616SKumar Gala 669129ba616SKumar Gala #undef CONFIG_WATCHDOG /* watchdog disabled */ 670129ba616SKumar Gala 671129ba616SKumar Gala /* 672129ba616SKumar Gala * Miscellaneous configurable options 673129ba616SKumar Gala */ 6746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 675129ba616SKumar Gala #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 6765be58f5fSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 6776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 6786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 679129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 6806d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 681129ba616SKumar Gala #else 6826d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 683129ba616SKumar Gala #endif 6846d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 6856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 6866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 6876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 688129ba616SKumar Gala 689129ba616SKumar Gala /* 690129ba616SKumar Gala * For booting Linux, the board info and command line data 69189188a62SKumar Gala * have to be in the first 16 MB of memory, since this is 692129ba616SKumar Gala * the maximum mapped by the Linux kernel during initialization. 693129ba616SKumar Gala */ 69489188a62SKumar Gala #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 695129ba616SKumar Gala 696129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 697129ba616SKumar Gala #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 698129ba616SKumar Gala #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 699129ba616SKumar Gala #endif 700129ba616SKumar Gala 701129ba616SKumar Gala /* 702129ba616SKumar Gala * Environment Configuration 703129ba616SKumar Gala */ 704129ba616SKumar Gala 705129ba616SKumar Gala /* The mac addresses for all ethernet interface */ 706129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 707129ba616SKumar Gala #define CONFIG_HAS_ETH0 708129ba616SKumar Gala #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 709129ba616SKumar Gala #define CONFIG_HAS_ETH1 710129ba616SKumar Gala #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 711129ba616SKumar Gala #define CONFIG_HAS_ETH2 712129ba616SKumar Gala #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 713129ba616SKumar Gala #define CONFIG_HAS_ETH3 714129ba616SKumar Gala #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 715129ba616SKumar Gala #endif 716129ba616SKumar Gala 717129ba616SKumar Gala #define CONFIG_IPADDR 192.168.1.254 718129ba616SKumar Gala 719129ba616SKumar Gala #define CONFIG_HOSTNAME unknown 720129ba616SKumar Gala #define CONFIG_ROOTPATH /opt/nfsroot 721129ba616SKumar Gala #define CONFIG_BOOTFILE uImage 722129ba616SKumar Gala #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 723129ba616SKumar Gala 724129ba616SKumar Gala #define CONFIG_SERVERIP 192.168.1.1 725129ba616SKumar Gala #define CONFIG_GATEWAYIP 192.168.1.1 726129ba616SKumar Gala #define CONFIG_NETMASK 255.255.255.0 727129ba616SKumar Gala 728129ba616SKumar Gala /* default location for tftp and bootm */ 729129ba616SKumar Gala #define CONFIG_LOADADDR 1000000 730129ba616SKumar Gala 731129ba616SKumar Gala #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 732129ba616SKumar Gala #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 733129ba616SKumar Gala 734129ba616SKumar Gala #define CONFIG_BAUDRATE 115200 735129ba616SKumar Gala 736129ba616SKumar Gala #define CONFIG_EXTRA_ENV_SETTINGS \ 7374ca06607SHaiying Wang "memctl_intlv_ctl=2\0" \ 738129ba616SKumar Gala "netdev=eth0\0" \ 739129ba616SKumar Gala "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 740129ba616SKumar Gala "tftpflash=tftpboot $loadaddr $uboot; " \ 74114d0a02aSWolfgang Denk "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 74214d0a02aSWolfgang Denk "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 74314d0a02aSWolfgang Denk "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ 74414d0a02aSWolfgang Denk "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ 74514d0a02aSWolfgang Denk "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ 746129ba616SKumar Gala "consoledev=ttyS0\0" \ 747129ba616SKumar Gala "ramdiskaddr=2000000\0" \ 748129ba616SKumar Gala "ramdiskfile=8572ds/ramdisk.uboot\0" \ 749129ba616SKumar Gala "fdtaddr=c00000\0" \ 750129ba616SKumar Gala "fdtfile=8572ds/mpc8572ds.dtb\0" \ 751129ba616SKumar Gala "bdev=sda3\0" 752129ba616SKumar Gala 753129ba616SKumar Gala #define CONFIG_HDBOOT \ 754129ba616SKumar Gala "setenv bootargs root=/dev/$bdev rw " \ 755129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 756129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 757129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 758129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 759129ba616SKumar Gala 760129ba616SKumar Gala #define CONFIG_NFSBOOTCOMMAND \ 761129ba616SKumar Gala "setenv bootargs root=/dev/nfs rw " \ 762129ba616SKumar Gala "nfsroot=$serverip:$rootpath " \ 763129ba616SKumar Gala "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 764129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 765129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 766129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 767129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 768129ba616SKumar Gala 769129ba616SKumar Gala #define CONFIG_RAMBOOTCOMMAND \ 770129ba616SKumar Gala "setenv bootargs root=/dev/ram rw " \ 771129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 772129ba616SKumar Gala "tftp $ramdiskaddr $ramdiskfile;" \ 773129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 774129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 775129ba616SKumar Gala "bootm $loadaddr $ramdiskaddr $fdtaddr" 776129ba616SKumar Gala 777129ba616SKumar Gala #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 778129ba616SKumar Gala 779129ba616SKumar Gala #endif /* __CONFIG_H */ 780