1129ba616SKumar Gala /* 27c57f3e8SKumar Gala * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 3129ba616SKumar Gala * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 5129ba616SKumar Gala */ 6129ba616SKumar Gala 7129ba616SKumar Gala /* 8129ba616SKumar Gala * mpc8572ds board configuration file 9129ba616SKumar Gala * 10129ba616SKumar Gala */ 11129ba616SKumar Gala #ifndef __CONFIG_H 12129ba616SKumar Gala #define __CONFIG_H 13129ba616SKumar Gala 14*15672c6dSYork Sun #define CONFIG_SYS_GENERIC_BOARD 15*15672c6dSYork Sun #define CONFIG_DISPLAY_BOARDINFO 16*15672c6dSYork Sun 17509c4c4cSKumar Gala #include "../board/freescale/common/ics307_clk.h" 18509c4c4cSKumar Gala 19d24f2d32SWolfgang Denk #ifdef CONFIG_36BIT 20f9edcc10SKumar Gala #define CONFIG_PHYS_64BIT 21f9edcc10SKumar Gala #endif 22f9edcc10SKumar Gala 23cb14e93bSKumar Gala #ifdef CONFIG_NAND 24cb14e93bSKumar Gala #define CONFIG_NAND_U_BOOT 25cb14e93bSKumar Gala #define CONFIG_RAMBOOT_NAND 26cb14e93bSKumar Gala #ifdef CONFIG_NAND_SPL 27cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 28cb14e93bSKumar Gala #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 29cb14e93bSKumar Gala #else 304a377552SMasahiro Yamada #define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds 31cb14e93bSKumar Gala #define CONFIG_SYS_TEXT_BASE 0xf8f82000 32cb14e93bSKumar Gala #endif /* CONFIG_NAND_SPL */ 33cb14e93bSKumar Gala #endif 34cb14e93bSKumar Gala 35cb14e93bSKumar Gala #ifndef CONFIG_SYS_TEXT_BASE 3618025756SYork Sun #define CONFIG_SYS_TEXT_BASE 0xeff40000 37cb14e93bSKumar Gala #endif 38cb14e93bSKumar Gala 397a577fdaSKumar Gala #ifndef CONFIG_RESET_VECTOR_ADDRESS 407a577fdaSKumar Gala #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 417a577fdaSKumar Gala #endif 427a577fdaSKumar Gala 43cb14e93bSKumar Gala #ifndef CONFIG_SYS_MONITOR_BASE 44cb14e93bSKumar Gala #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 45cb14e93bSKumar Gala #endif 46cb14e93bSKumar Gala 47129ba616SKumar Gala /* High Level Configuration Options */ 48129ba616SKumar Gala #define CONFIG_BOOKE 1 /* BOOKE */ 49129ba616SKumar Gala #define CONFIG_E500 1 /* BOOKE e500 family */ 50129ba616SKumar Gala #define CONFIG_MPC8572 1 51129ba616SKumar Gala #define CONFIG_MPC8572DS 1 52129ba616SKumar Gala #define CONFIG_MP 1 /* support multiple processors */ 53129ba616SKumar Gala 54c51fc5d5SKumar Gala #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ 55129ba616SKumar Gala #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 56129ba616SKumar Gala #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 57129ba616SKumar Gala #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 58129ba616SKumar Gala #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 59129ba616SKumar Gala #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 60842033e6SGabor Juhos #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 61129ba616SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 620151cbacSKumar Gala #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 63129ba616SKumar Gala 64129ba616SKumar Gala #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 65129ba616SKumar Gala 66129ba616SKumar Gala #define CONFIG_TSEC_ENET /* tsec ethernet support */ 67129ba616SKumar Gala #define CONFIG_ENV_OVERWRITE 68129ba616SKumar Gala 69509c4c4cSKumar Gala #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 70509c4c4cSKumar Gala #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 714ca06607SHaiying Wang #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 72129ba616SKumar Gala 73129ba616SKumar Gala /* 74129ba616SKumar Gala * These can be toggled for performance analysis, otherwise use default. 75129ba616SKumar Gala */ 76129ba616SKumar Gala #define CONFIG_L2_CACHE /* toggle L2 cache */ 77129ba616SKumar Gala #define CONFIG_BTB /* toggle branch predition */ 78129ba616SKumar Gala 79129ba616SKumar Gala #define CONFIG_ENABLE_36BIT_PHYS 1 80129ba616SKumar Gala 8118af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 8218af1c5fSKumar Gala #define CONFIG_ADDR_MAP 1 8318af1c5fSKumar Gala #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 8418af1c5fSKumar Gala #endif 8518af1c5fSKumar Gala 866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ 876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x7fffffff 88129ba616SKumar Gala #define CONFIG_PANIC_HANG /* do not reset board on panic */ 89129ba616SKumar Gala 90129ba616SKumar Gala /* 91cb14e93bSKumar Gala * Config the L2 Cache as L2 SRAM 92cb14e93bSKumar Gala */ 93cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 94cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 95cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 96cb14e93bSKumar Gala #else 97cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 98cb14e93bSKumar Gala #endif 99cb14e93bSKumar Gala #define CONFIG_SYS_L2_SIZE (512 << 10) 100cb14e93bSKumar Gala #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 101cb14e93bSKumar Gala 102e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR 0xffe00000 103e46fedfeSTimur Tabi #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 104129ba616SKumar Gala 1058d22ddcaSKumar Gala #if defined(CONFIG_NAND_SPL) 106e46fedfeSTimur Tabi #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 107cb14e93bSKumar Gala #endif 108cb14e93bSKumar Gala 109129ba616SKumar Gala /* DDR Setup */ 110f8523cb0SKumar Gala #define CONFIG_VERY_BIG_RAM 1115614e71bSYork Sun #define CONFIG_SYS_FSL_DDR2 112129ba616SKumar Gala #undef CONFIG_FSL_DDR_INTERACTIVE 113129ba616SKumar Gala #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 114129ba616SKumar Gala #define CONFIG_DDR_SPD 115129ba616SKumar Gala 116d34897d3SYork Sun #define CONFIG_DDR_ECC 1179b0ad1b1SDave Liu #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 118129ba616SKumar Gala #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 119129ba616SKumar Gala 1206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 1216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 122129ba616SKumar Gala 123129ba616SKumar Gala #define CONFIG_NUM_DDR_CONTROLLERS 2 124129ba616SKumar Gala #define CONFIG_DIMM_SLOTS_PER_CTLR 1 125129ba616SKumar Gala #define CONFIG_CHIP_SELECTS_PER_CTRL 2 126129ba616SKumar Gala 127129ba616SKumar Gala /* I2C addresses of SPD EEPROMs */ 1286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 129129ba616SKumar Gala #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 130129ba616SKumar Gala #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 131129ba616SKumar Gala 132129ba616SKumar Gala /* These are used when DDR doesn't use SPD. */ 133dc889e86SDave Liu #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 1346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 135dc889e86SDave Liu #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 136dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_3 0x00020000 1376d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_TIMING_0 0x00260802 138dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 139dc889e86SDave Liu #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 140dc889e86SDave Liu #define CONFIG_SYS_DDR_MODE_1 0x00440462 1416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_MODE_2 0x00000000 142dc889e86SDave Liu #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 1436d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 144dc889e86SDave Liu #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 1456d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 1466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 147dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 148dc889e86SDave Liu #define CONFIG_SYS_DDR_CONTROL2 0x24400000 149129ba616SKumar Gala 1506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 1516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 1526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DDR_SBE 0x00010000 153129ba616SKumar Gala 154129ba616SKumar Gala /* 155129ba616SKumar Gala * Make sure required options are set 156129ba616SKumar Gala */ 157129ba616SKumar Gala #ifndef CONFIG_SPD_EEPROM 158129ba616SKumar Gala #error ("CONFIG_SPD_EEPROM is required") 159129ba616SKumar Gala #endif 160129ba616SKumar Gala 161129ba616SKumar Gala #undef CONFIG_CLOCKS_IN_MHZ 162129ba616SKumar Gala 163129ba616SKumar Gala /* 164129ba616SKumar Gala * Memory map 165129ba616SKumar Gala * 166129ba616SKumar Gala * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 167129ba616SKumar Gala * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 168129ba616SKumar Gala * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 169129ba616SKumar Gala * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 170129ba616SKumar Gala * 171129ba616SKumar Gala * Localbus cacheable (TBD) 172129ba616SKumar Gala * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 173129ba616SKumar Gala * 174129ba616SKumar Gala * Localbus non-cacheable 175129ba616SKumar Gala * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 176129ba616SKumar Gala * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 177c013b749SHaiying Wang * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 178129ba616SKumar Gala * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 179129ba616SKumar Gala * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 180129ba616SKumar Gala * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 181129ba616SKumar Gala */ 182129ba616SKumar Gala 183129ba616SKumar Gala /* 184129ba616SKumar Gala * Local Bus Definitions 185129ba616SKumar Gala */ 1866d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 18718af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 18818af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 18918af1c5fSKumar Gala #else 190c953ddfdSKumar Gala #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 19118af1c5fSKumar Gala #endif 192129ba616SKumar Gala 193cb14e93bSKumar Gala 194cb14e93bSKumar Gala #define CONFIG_FLASH_BR_PRELIM \ 1957ee41107STimur Tabi (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 196cb14e93bSKumar Gala #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 197129ba616SKumar Gala 198c953ddfdSKumar Gala #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 1996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 200129ba616SKumar Gala 20118af1c5fSKumar Gala #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 2026d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_QUIET_TEST 203129ba616SKumar Gala #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 204129ba616SKumar Gala 2056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 2066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 2076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_FLASH_CHECKSUM 2086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 2096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 210129ba616SKumar Gala 211cb14e93bSKumar Gala #if defined(CONFIG_RAMBOOT_NAND) 212cb14e93bSKumar Gala #define CONFIG_SYS_RAMBOOT 213cb14e93bSKumar Gala #define CONFIG_SYS_EXTRA_ENV_RELOC 214cb14e93bSKumar Gala #else 215cb14e93bSKumar Gala #undef CONFIG_SYS_RAMBOOT 216cb14e93bSKumar Gala #endif 217129ba616SKumar Gala 218129ba616SKumar Gala #define CONFIG_FLASH_CFI_DRIVER 2196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_CFI 2206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_EMPTY_INFO 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 222129ba616SKumar Gala 223129ba616SKumar Gala #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 224129ba616SKumar Gala 225558710b9SKumar Gala #define CONFIG_HWCONFIG /* enable hwconfig */ 226129ba616SKumar Gala #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 227129ba616SKumar Gala #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 22818af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 22918af1c5fSKumar Gala #define PIXIS_BASE_PHYS 0xfffdf0000ull 23018af1c5fSKumar Gala #else 23152b565f5SKumar Gala #define PIXIS_BASE_PHYS PIXIS_BASE 23218af1c5fSKumar Gala #endif 233129ba616SKumar Gala 23452b565f5SKumar Gala #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 2356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 236129ba616SKumar Gala 237129ba616SKumar Gala #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 238129ba616SKumar Gala #define PIXIS_VER 0x1 /* Board version at offset 1 */ 239129ba616SKumar Gala #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 240129ba616SKumar Gala #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 241129ba616SKumar Gala #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 242129ba616SKumar Gala #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 243129ba616SKumar Gala #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 244129ba616SKumar Gala #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 245129ba616SKumar Gala #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 246129ba616SKumar Gala #define PIXIS_VCTL 0x10 /* VELA Control Register */ 247129ba616SKumar Gala #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 248129ba616SKumar Gala #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 249129ba616SKumar Gala #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 250129ba616SKumar Gala #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 251129ba616SKumar Gala #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 2526bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 2536bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 2546bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 2556bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 2566bb5b412SKumar Gala #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 257129ba616SKumar Gala #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 258129ba616SKumar Gala #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 259129ba616SKumar Gala #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 260129ba616SKumar Gala #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 261129ba616SKumar Gala #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 262129ba616SKumar Gala #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 263129ba616SKumar Gala #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 264129ba616SKumar Gala #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 265129ba616SKumar Gala #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 266129ba616SKumar Gala #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 267129ba616SKumar Gala #define PIXIS_LED 0x25 /* LED Register */ 268129ba616SKumar Gala 269cb14e93bSKumar Gala #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 270cb14e93bSKumar Gala 271129ba616SKumar Gala /* old pixis referenced names */ 272129ba616SKumar Gala #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 273129ba616SKumar Gala #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 2746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 2757e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC1SER 0x8 2767e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC2SER 0x4 2777e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC3SER 0x2 2787e183cadSLiu Yu #define PIXIS_VSPEED2_TSEC4SER 0x1 2797e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC1SER 0x20 2807e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC2SER 0x20 2817e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC3SER 0x20 2827e183cadSLiu Yu #define PIXIS_VCFGEN1_TSEC4SER 0x20 2837e183cadSLiu Yu #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 2847e183cadSLiu Yu | PIXIS_VSPEED2_TSEC2SER \ 2857e183cadSLiu Yu | PIXIS_VSPEED2_TSEC3SER \ 2867e183cadSLiu Yu | PIXIS_VSPEED2_TSEC4SER) 2877e183cadSLiu Yu #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 2887e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC2SER \ 2897e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC3SER \ 2907e183cadSLiu Yu | PIXIS_VCFGEN1_TSEC4SER) 291129ba616SKumar Gala 2926d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_LOCK 1 2936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 294553f0982SWolfgang Denk #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 295129ba616SKumar Gala 29625ddd1fbSWolfgang Denk #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 2976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 298129ba616SKumar Gala 2996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 3006d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 301129ba616SKumar Gala 302cb14e93bSKumar Gala #ifndef CONFIG_NAND_SPL 303c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE 0xffa00000 30418af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 30518af1c5fSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 30618af1c5fSKumar Gala #else 307c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 30818af1c5fSKumar Gala #endif 309cb14e93bSKumar Gala #else 310cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE 0xfff00000 311cb14e93bSKumar Gala #ifdef CONFIG_PHYS_64BIT 312cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 313cb14e93bSKumar Gala #else 314cb14e93bSKumar Gala #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 315cb14e93bSKumar Gala #endif 316cb14e93bSKumar Gala #endif 317cb14e93bSKumar Gala 318c013b749SHaiying Wang #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 319c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x40000, \ 320c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0x80000,\ 321c013b749SHaiying Wang CONFIG_SYS_NAND_BASE + 0xC0000} 322c013b749SHaiying Wang #define CONFIG_SYS_MAX_NAND_DEVICE 4 323c013b749SHaiying Wang #define CONFIG_MTD_NAND_VERIFY_WRITE 324c013b749SHaiying Wang #define CONFIG_CMD_NAND 1 325c013b749SHaiying Wang #define CONFIG_NAND_FSL_ELBC 1 326c013b749SHaiying Wang #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 32768ec9c85SPrabhakar Kushwaha #define CONFIG_SYS_NAND_MAX_OOBFREE 5 32868ec9c85SPrabhakar Kushwaha #define CONFIG_SYS_NAND_MAX_ECCPOS 56 329c013b749SHaiying Wang 330cb14e93bSKumar Gala /* NAND boot: 4K NAND loader config */ 331cb14e93bSKumar Gala #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 332cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 333cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 334cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_START \ 335cb14e93bSKumar Gala (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 336cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 337cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 338cb14e93bSKumar Gala #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 339cb14e93bSKumar Gala 340cb14e93bSKumar Gala 341c013b749SHaiying Wang /* NAND flash config */ 342a3055c58SMatthew McClintock #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 343c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 344c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 345c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 346c013b749SHaiying Wang | BR_V) /* valid */ 347a3055c58SMatthew McClintock #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 348c013b749SHaiying Wang | OR_FCM_PGS /* Large Page*/ \ 349c013b749SHaiying Wang | OR_FCM_CSCT \ 350c013b749SHaiying Wang | OR_FCM_CST \ 351c013b749SHaiying Wang | OR_FCM_CHT \ 352c013b749SHaiying Wang | OR_FCM_SCY_1 \ 353c013b749SHaiying Wang | OR_FCM_TRLX \ 354c013b749SHaiying Wang | OR_FCM_EHTR) 355c013b749SHaiying Wang 356cb14e93bSKumar Gala #ifdef CONFIG_RAMBOOT_NAND 357a3055c58SMatthew McClintock #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 358a3055c58SMatthew McClintock #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 359cb14e93bSKumar Gala #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 360cb14e93bSKumar Gala #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 361cb14e93bSKumar Gala #else 362cb14e93bSKumar Gala #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 363cb14e93bSKumar Gala #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 364a3055c58SMatthew McClintock #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 365a3055c58SMatthew McClintock #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 366cb14e93bSKumar Gala #endif 3677ee41107STimur Tabi #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 368c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 369c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 370c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 371c013b749SHaiying Wang | BR_V) /* valid */ 372a3055c58SMatthew McClintock #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 3737ee41107STimur Tabi #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 374c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 375c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 376c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 377c013b749SHaiying Wang | BR_V) /* valid */ 378a3055c58SMatthew McClintock #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 379c013b749SHaiying Wang 3807ee41107STimur Tabi #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 381c013b749SHaiying Wang | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 382c013b749SHaiying Wang | BR_PS_8 /* Port Size = 8 bit */ \ 383c013b749SHaiying Wang | BR_MS_FCM /* MSEL = FCM */ \ 384c013b749SHaiying Wang | BR_V) /* valid */ 385a3055c58SMatthew McClintock #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 386c013b749SHaiying Wang 387c013b749SHaiying Wang 388129ba616SKumar Gala /* Serial Port - controlled on board with jumper J8 389129ba616SKumar Gala * open - index 2 390129ba616SKumar Gala * shorted - index 1 391129ba616SKumar Gala */ 392129ba616SKumar Gala #define CONFIG_CONS_INDEX 1 3936d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550 3946d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_SERIAL 3956d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_REG_SIZE 1 3966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 397cb14e93bSKumar Gala #ifdef CONFIG_NAND_SPL 398cb14e93bSKumar Gala #define CONFIG_NS16550_MIN_FUNCTIONS 399cb14e93bSKumar Gala #endif 400129ba616SKumar Gala 4016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE \ 402129ba616SKumar Gala {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 403129ba616SKumar Gala 4046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 4056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 406129ba616SKumar Gala 407129ba616SKumar Gala /* Use the HUSH parser */ 4086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HUSH_PARSER 409129ba616SKumar Gala 410129ba616SKumar Gala /* 411129ba616SKumar Gala * Pass open firmware flat tree 412129ba616SKumar Gala */ 413129ba616SKumar Gala #define CONFIG_OF_LIBFDT 1 414129ba616SKumar Gala #define CONFIG_OF_BOARD_SETUP 1 415129ba616SKumar Gala #define CONFIG_OF_STDOUT_VIA_ALIAS 1 416129ba616SKumar Gala 417129ba616SKumar Gala /* new uImage format support */ 418129ba616SKumar Gala #define CONFIG_FIT 1 419129ba616SKumar Gala #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 420129ba616SKumar Gala 421129ba616SKumar Gala /* I2C */ 42200f792e0SHeiko Schocher #define CONFIG_SYS_I2C 42300f792e0SHeiko Schocher #define CONFIG_SYS_I2C_FSL 42400f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SPEED 400000 42500f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 42600f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 42700f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SPEED 400000 42800f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 42900f792e0SHeiko Schocher #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 43000f792e0SHeiko Schocher #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 4316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 432129ba616SKumar Gala 433129ba616SKumar Gala /* 434445a7b38SHaiying Wang * I2C2 EEPROM 435445a7b38SHaiying Wang */ 436445a7b38SHaiying Wang #define CONFIG_ID_EEPROM 437445a7b38SHaiying Wang #ifdef CONFIG_ID_EEPROM 4386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_NXID 439445a7b38SHaiying Wang #endif 4406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 4416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 4426d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_EEPROM_BUS_NUM 1 443445a7b38SHaiying Wang 444445a7b38SHaiying Wang /* 445129ba616SKumar Gala * General PCI 446129ba616SKumar Gala * Memory space is mapped 1-1, but I/O space must start from 0. 447129ba616SKumar Gala */ 448129ba616SKumar Gala 449129ba616SKumar Gala /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 45018ea5551SKumar Gala #define CONFIG_SYS_PCIE3_NAME "ULI" 4515af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 45218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 453156984a3SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 45418af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 45518af1c5fSKumar Gala #else 456ad97dce1SKumar Gala #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 4575af0fdd8SKumar Gala #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 45818af1c5fSKumar Gala #endif 4596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 460aca5f018SKumar Gala #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 4615f91ef6aSKumar Gala #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 46218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 46318af1c5fSKumar Gala #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 46418af1c5fSKumar Gala #else 4656d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 46618af1c5fSKumar Gala #endif 4676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 468129ba616SKumar Gala 469129ba616SKumar Gala /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 47018ea5551SKumar Gala #define CONFIG_SYS_PCIE2_NAME "Slot 1" 4715af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 47218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 473156984a3SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 47418af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 47518af1c5fSKumar Gala #else 476ad97dce1SKumar Gala #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 4775af0fdd8SKumar Gala #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 47818af1c5fSKumar Gala #endif 4796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 480aca5f018SKumar Gala #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 4815f91ef6aSKumar Gala #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 48218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 48318af1c5fSKumar Gala #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 48418af1c5fSKumar Gala #else 4856d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 48618af1c5fSKumar Gala #endif 4876d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 488129ba616SKumar Gala 489129ba616SKumar Gala /* controller 1, Slot 1, tgtid 1, Base address a000 */ 49018ea5551SKumar Gala #define CONFIG_SYS_PCIE1_NAME "Slot 2" 4915af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 49218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 493156984a3SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 49418af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 49518af1c5fSKumar Gala #else 496ad97dce1SKumar Gala #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 4975af0fdd8SKumar Gala #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 49818af1c5fSKumar Gala #endif 4996d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 500aca5f018SKumar Gala #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 5015f91ef6aSKumar Gala #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 50218af1c5fSKumar Gala #ifdef CONFIG_PHYS_64BIT 50318af1c5fSKumar Gala #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 50418af1c5fSKumar Gala #else 5056d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 50618af1c5fSKumar Gala #endif 5076d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 508129ba616SKumar Gala 509129ba616SKumar Gala #if defined(CONFIG_PCI) 510129ba616SKumar Gala 511129ba616SKumar Gala /*PCIE video card used*/ 512aca5f018SKumar Gala #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 513129ba616SKumar Gala 514129ba616SKumar Gala /* video */ 515129ba616SKumar Gala #define CONFIG_VIDEO 516129ba616SKumar Gala 517129ba616SKumar Gala #if defined(CONFIG_VIDEO) 518129ba616SKumar Gala #define CONFIG_BIOSEMU 519129ba616SKumar Gala #define CONFIG_CFB_CONSOLE 520129ba616SKumar Gala #define CONFIG_VIDEO_SW_CURSOR 521129ba616SKumar Gala #define CONFIG_VGA_AS_SINGLE_DEVICE 522129ba616SKumar Gala #define CONFIG_ATI_RADEON_FB 523129ba616SKumar Gala #define CONFIG_VIDEO_LOGO 524129ba616SKumar Gala /*#define CONFIG_CONSOLE_CURSOR*/ 5256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 526129ba616SKumar Gala #endif 527129ba616SKumar Gala 528129ba616SKumar Gala #define CONFIG_PCI_PNP /* do pci plug-and-play */ 529129ba616SKumar Gala 530129ba616SKumar Gala #undef CONFIG_EEPRO100 531129ba616SKumar Gala #undef CONFIG_TULIP 532129ba616SKumar Gala #undef CONFIG_RTL8139 53316855ec1SKumar Gala #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 534129ba616SKumar Gala 535129ba616SKumar Gala #ifndef CONFIG_PCI_PNP 5365f91ef6aSKumar Gala #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 5375f91ef6aSKumar Gala #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 538129ba616SKumar Gala #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 539129ba616SKumar Gala #endif 540129ba616SKumar Gala 541129ba616SKumar Gala #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 542129ba616SKumar Gala #define CONFIG_DOS_PARTITION 543129ba616SKumar Gala #define CONFIG_SCSI_AHCI 544129ba616SKumar Gala 545129ba616SKumar Gala #ifdef CONFIG_SCSI_AHCI 546344ca0b4SRob Herring #define CONFIG_LIBATA 547129ba616SKumar Gala #define CONFIG_SATA_ULI5288 5486d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 5496d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_LUN 1 5506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 5516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE 552129ba616SKumar Gala #endif /* SCSI */ 553129ba616SKumar Gala 554129ba616SKumar Gala #endif /* CONFIG_PCI */ 555129ba616SKumar Gala 556129ba616SKumar Gala 557129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 558129ba616SKumar Gala 559129ba616SKumar Gala #define CONFIG_MII 1 /* MII PHY management */ 560129ba616SKumar Gala #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 561129ba616SKumar Gala #define CONFIG_TSEC1 1 562129ba616SKumar Gala #define CONFIG_TSEC1_NAME "eTSEC1" 563129ba616SKumar Gala #define CONFIG_TSEC2 1 564129ba616SKumar Gala #define CONFIG_TSEC2_NAME "eTSEC2" 565129ba616SKumar Gala #define CONFIG_TSEC3 1 566129ba616SKumar Gala #define CONFIG_TSEC3_NAME "eTSEC3" 567129ba616SKumar Gala #define CONFIG_TSEC4 1 568129ba616SKumar Gala #define CONFIG_TSEC4_NAME "eTSEC4" 569129ba616SKumar Gala 5707e183cadSLiu Yu #define CONFIG_PIXIS_SGMII_CMD 5717e183cadSLiu Yu #define CONFIG_FSL_SGMII_RISER 1 5727e183cadSLiu Yu #define SGMII_RISER_PHY_OFFSET 0x1c 5737e183cadSLiu Yu 5747e183cadSLiu Yu #ifdef CONFIG_FSL_SGMII_RISER 5757e183cadSLiu Yu #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 5767e183cadSLiu Yu #endif 5777e183cadSLiu Yu 578129ba616SKumar Gala #define TSEC1_PHY_ADDR 0 579129ba616SKumar Gala #define TSEC2_PHY_ADDR 1 580129ba616SKumar Gala #define TSEC3_PHY_ADDR 2 581129ba616SKumar Gala #define TSEC4_PHY_ADDR 3 582129ba616SKumar Gala 583129ba616SKumar Gala #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 584129ba616SKumar Gala #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 585129ba616SKumar Gala #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 586129ba616SKumar Gala #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 587129ba616SKumar Gala 588129ba616SKumar Gala #define TSEC1_PHYIDX 0 589129ba616SKumar Gala #define TSEC2_PHYIDX 0 590129ba616SKumar Gala #define TSEC3_PHYIDX 0 591129ba616SKumar Gala #define TSEC4_PHYIDX 0 592129ba616SKumar Gala 593129ba616SKumar Gala #define CONFIG_ETHPRIME "eTSEC1" 594129ba616SKumar Gala 595129ba616SKumar Gala #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 596129ba616SKumar Gala #endif /* CONFIG_TSEC_ENET */ 597129ba616SKumar Gala 598129ba616SKumar Gala /* 599129ba616SKumar Gala * Environment 600129ba616SKumar Gala */ 601cb14e93bSKumar Gala 602cb14e93bSKumar Gala #if defined(CONFIG_SYS_RAMBOOT) 603cb14e93bSKumar Gala #if defined(CONFIG_RAMBOOT_NAND) 604cb14e93bSKumar Gala #define CONFIG_ENV_IS_IN_NAND 1 605cb14e93bSKumar Gala #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 606cb14e93bSKumar Gala #define CONFIG_ENV_OFFSET ((512 * 1024)\ 607cb14e93bSKumar Gala + CONFIG_SYS_NAND_BLOCK_SIZE) 608cb14e93bSKumar Gala #endif 609cb14e93bSKumar Gala 610cb14e93bSKumar Gala #else 6115a1aceb0SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_FLASH 1 6126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 6130e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR 0xfff80000 614129ba616SKumar Gala #else 6156fc110bdSHaiying Wang #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 616129ba616SKumar Gala #endif 6170e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x2000 6180e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 619cb14e93bSKumar Gala #endif 620129ba616SKumar Gala 621129ba616SKumar Gala #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 6226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 623129ba616SKumar Gala 624129ba616SKumar Gala /* 625129ba616SKumar Gala * Command line configuration. 626129ba616SKumar Gala */ 627129ba616SKumar Gala #include <config_cmd_default.h> 628129ba616SKumar Gala 62967f94476SYork Sun #define CONFIG_CMD_ERRATA 630129ba616SKumar Gala #define CONFIG_CMD_IRQ 631129ba616SKumar Gala #define CONFIG_CMD_PING 632129ba616SKumar Gala #define CONFIG_CMD_I2C 633129ba616SKumar Gala #define CONFIG_CMD_MII 634129ba616SKumar Gala #define CONFIG_CMD_ELF 6351c9aa76bSKumar Gala #define CONFIG_CMD_SETEXPR 636199e262eSBecky Bruce #define CONFIG_CMD_REGINFO 637129ba616SKumar Gala 638129ba616SKumar Gala #if defined(CONFIG_PCI) 639129ba616SKumar Gala #define CONFIG_CMD_PCI 640129ba616SKumar Gala #define CONFIG_CMD_NET 641129ba616SKumar Gala #define CONFIG_CMD_SCSI 642129ba616SKumar Gala #define CONFIG_CMD_EXT2 643129ba616SKumar Gala #endif 644129ba616SKumar Gala 645863a3eacSZhao Chenhui /* 646863a3eacSZhao Chenhui * USB 647863a3eacSZhao Chenhui */ 648863a3eacSZhao Chenhui #define CONFIG_USB_EHCI 649863a3eacSZhao Chenhui 650863a3eacSZhao Chenhui #ifdef CONFIG_USB_EHCI 651863a3eacSZhao Chenhui #define CONFIG_CMD_USB 652863a3eacSZhao Chenhui #define CONFIG_USB_EHCI_PCI 653863a3eacSZhao Chenhui #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 654863a3eacSZhao Chenhui #define CONFIG_USB_STORAGE 655863a3eacSZhao Chenhui #define CONFIG_PCI_EHCI_DEVICE 0 656863a3eacSZhao Chenhui #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 657863a3eacSZhao Chenhui #endif 658863a3eacSZhao Chenhui 659129ba616SKumar Gala #undef CONFIG_WATCHDOG /* watchdog disabled */ 660129ba616SKumar Gala 661129ba616SKumar Gala /* 662129ba616SKumar Gala * Miscellaneous configurable options 663129ba616SKumar Gala */ 6646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP /* undef to save memory */ 665129ba616SKumar Gala #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 6665be58f5fSKim Phillips #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 6676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 668129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 6696d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 670129ba616SKumar Gala #else 6716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 672129ba616SKumar Gala #endif 6736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 6746d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 6756d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 676129ba616SKumar Gala 677129ba616SKumar Gala /* 678129ba616SKumar Gala * For booting Linux, the board info and command line data 679a832ac41SKumar Gala * have to be in the first 64 MB of memory, since this is 680129ba616SKumar Gala * the maximum mapped by the Linux kernel during initialization. 681129ba616SKumar Gala */ 682a832ac41SKumar Gala #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 683a832ac41SKumar Gala #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 684129ba616SKumar Gala 685129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 686129ba616SKumar Gala #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 687129ba616SKumar Gala #endif 688129ba616SKumar Gala 689129ba616SKumar Gala /* 690129ba616SKumar Gala * Environment Configuration 691129ba616SKumar Gala */ 692129ba616SKumar Gala 693129ba616SKumar Gala /* The mac addresses for all ethernet interface */ 694129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 695129ba616SKumar Gala #define CONFIG_HAS_ETH0 696129ba616SKumar Gala #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 697129ba616SKumar Gala #define CONFIG_HAS_ETH1 698129ba616SKumar Gala #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 699129ba616SKumar Gala #define CONFIG_HAS_ETH2 700129ba616SKumar Gala #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 701129ba616SKumar Gala #define CONFIG_HAS_ETH3 702129ba616SKumar Gala #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 703129ba616SKumar Gala #endif 704129ba616SKumar Gala 705129ba616SKumar Gala #define CONFIG_IPADDR 192.168.1.254 706129ba616SKumar Gala 707129ba616SKumar Gala #define CONFIG_HOSTNAME unknown 7088b3637c6SJoe Hershberger #define CONFIG_ROOTPATH "/opt/nfsroot" 709b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 710129ba616SKumar Gala #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 711129ba616SKumar Gala 712129ba616SKumar Gala #define CONFIG_SERVERIP 192.168.1.1 713129ba616SKumar Gala #define CONFIG_GATEWAYIP 192.168.1.1 714129ba616SKumar Gala #define CONFIG_NETMASK 255.255.255.0 715129ba616SKumar Gala 716129ba616SKumar Gala /* default location for tftp and bootm */ 717129ba616SKumar Gala #define CONFIG_LOADADDR 1000000 718129ba616SKumar Gala 719129ba616SKumar Gala #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 720129ba616SKumar Gala #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 721129ba616SKumar Gala 722129ba616SKumar Gala #define CONFIG_BAUDRATE 115200 723129ba616SKumar Gala 724129ba616SKumar Gala #define CONFIG_EXTRA_ENV_SETTINGS \ 725238e1467SHongtao Jia "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 726129ba616SKumar Gala "netdev=eth0\0" \ 7275368c55dSMarek Vasut "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 728129ba616SKumar Gala "tftpflash=tftpboot $loadaddr $uboot; " \ 7295368c55dSMarek Vasut "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 7305368c55dSMarek Vasut " +$filesize; " \ 7315368c55dSMarek Vasut "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 7325368c55dSMarek Vasut " +$filesize; " \ 7335368c55dSMarek Vasut "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7345368c55dSMarek Vasut " $filesize; " \ 7355368c55dSMarek Vasut "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 7365368c55dSMarek Vasut " +$filesize; " \ 7375368c55dSMarek Vasut "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 7385368c55dSMarek Vasut " $filesize\0" \ 739129ba616SKumar Gala "consoledev=ttyS0\0" \ 740129ba616SKumar Gala "ramdiskaddr=2000000\0" \ 741129ba616SKumar Gala "ramdiskfile=8572ds/ramdisk.uboot\0" \ 742129ba616SKumar Gala "fdtaddr=c00000\0" \ 743129ba616SKumar Gala "fdtfile=8572ds/mpc8572ds.dtb\0" \ 744129ba616SKumar Gala "bdev=sda3\0" 745129ba616SKumar Gala 746129ba616SKumar Gala #define CONFIG_HDBOOT \ 747129ba616SKumar Gala "setenv bootargs root=/dev/$bdev rw " \ 748129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 749129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 750129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 751129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 752129ba616SKumar Gala 753129ba616SKumar Gala #define CONFIG_NFSBOOTCOMMAND \ 754129ba616SKumar Gala "setenv bootargs root=/dev/nfs rw " \ 755129ba616SKumar Gala "nfsroot=$serverip:$rootpath " \ 756129ba616SKumar Gala "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 757129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 758129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 759129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 760129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 761129ba616SKumar Gala 762129ba616SKumar Gala #define CONFIG_RAMBOOTCOMMAND \ 763129ba616SKumar Gala "setenv bootargs root=/dev/ram rw " \ 764129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 765129ba616SKumar Gala "tftp $ramdiskaddr $ramdiskfile;" \ 766129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 767129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 768129ba616SKumar Gala "bootm $loadaddr $ramdiskaddr $fdtaddr" 769129ba616SKumar Gala 770129ba616SKumar Gala #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 771129ba616SKumar Gala 772129ba616SKumar Gala #endif /* __CONFIG_H */ 773