1*129ba616SKumar Gala /* 2*129ba616SKumar Gala * Copyright 2007-2008 Freescale Semiconductor, Inc. 3*129ba616SKumar Gala * 4*129ba616SKumar Gala * See file CREDITS for list of people who contributed to this 5*129ba616SKumar Gala * project. 6*129ba616SKumar Gala * 7*129ba616SKumar Gala * This program is free software; you can redistribute it and/or 8*129ba616SKumar Gala * modify it under the terms of the GNU General Public License as 9*129ba616SKumar Gala * published by the Free Software Foundation; either version 2 of 10*129ba616SKumar Gala * the License, or (at your option) any later version. 11*129ba616SKumar Gala * 12*129ba616SKumar Gala * This program is distributed in the hope that it will be useful, 13*129ba616SKumar Gala * but WITHOUT ANY WARRANTY; without even the implied warranty of 14*129ba616SKumar Gala * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15*129ba616SKumar Gala * GNU General Public License for more details. 16*129ba616SKumar Gala * 17*129ba616SKumar Gala * You should have received a copy of the GNU General Public License 18*129ba616SKumar Gala * along with this program; if not, write to the Free Software 19*129ba616SKumar Gala * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20*129ba616SKumar Gala * MA 02111-1307 USA 21*129ba616SKumar Gala */ 22*129ba616SKumar Gala 23*129ba616SKumar Gala /* 24*129ba616SKumar Gala * mpc8572ds board configuration file 25*129ba616SKumar Gala * 26*129ba616SKumar Gala */ 27*129ba616SKumar Gala #ifndef __CONFIG_H 28*129ba616SKumar Gala #define __CONFIG_H 29*129ba616SKumar Gala 30*129ba616SKumar Gala /* High Level Configuration Options */ 31*129ba616SKumar Gala #define CONFIG_BOOKE 1 /* BOOKE */ 32*129ba616SKumar Gala #define CONFIG_E500 1 /* BOOKE e500 family */ 33*129ba616SKumar Gala #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ 34*129ba616SKumar Gala #define CONFIG_MPC8572 1 35*129ba616SKumar Gala #define CONFIG_MPC8572DS 1 36*129ba616SKumar Gala #define CONFIG_MP 1 /* support multiple processors */ 37*129ba616SKumar Gala #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ 38*129ba616SKumar Gala 39*129ba616SKumar Gala #define CONFIG_PCI 1 /* Enable PCI/PCIE */ 40*129ba616SKumar Gala #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ 41*129ba616SKumar Gala #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ 42*129ba616SKumar Gala #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ 43*129ba616SKumar Gala #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 44*129ba616SKumar Gala #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 45*129ba616SKumar Gala 46*129ba616SKumar Gala #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 47*129ba616SKumar Gala 48*129ba616SKumar Gala #define CONFIG_TSEC_ENET /* tsec ethernet support */ 49*129ba616SKumar Gala #define CONFIG_ENV_OVERWRITE 50*129ba616SKumar Gala 51*129ba616SKumar Gala /* 52*129ba616SKumar Gala * When initializing flash, if we cannot find the manufacturer ID, 53*129ba616SKumar Gala * assume this is the AMD flash associated with the CDS board. 54*129ba616SKumar Gala * This allows booting from a promjet. 55*129ba616SKumar Gala */ 56*129ba616SKumar Gala #define CONFIG_ASSUME_AMD_FLASH 57*129ba616SKumar Gala 58*129ba616SKumar Gala #ifndef __ASSEMBLY__ 59*129ba616SKumar Gala extern unsigned long get_board_sys_clk(unsigned long dummy); 60*129ba616SKumar Gala extern unsigned long get_board_ddr_clk(unsigned long dummy); 61*129ba616SKumar Gala #endif 62*129ba616SKumar Gala #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ 63*129ba616SKumar Gala #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ 64*129ba616SKumar Gala #define CONFIG_ICS307_REFCLK_HZ 33333333 /* ICS307 clock chip ref freq */ 65*129ba616SKumar Gala #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq 66*129ba616SKumar Gala from ICS307 instead of switches */ 67*129ba616SKumar Gala 68*129ba616SKumar Gala /* 69*129ba616SKumar Gala * These can be toggled for performance analysis, otherwise use default. 70*129ba616SKumar Gala */ 71*129ba616SKumar Gala #define CONFIG_L2_CACHE /* toggle L2 cache */ 72*129ba616SKumar Gala #define CONFIG_BTB /* toggle branch predition */ 73*129ba616SKumar Gala #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 74*129ba616SKumar Gala 75*129ba616SKumar Gala #define CONFIG_ENABLE_36BIT_PHYS 1 76*129ba616SKumar Gala 77*129ba616SKumar Gala #define CFG_MEMTEST_START 0x00000000 /* memtest works on */ 78*129ba616SKumar Gala #define CFG_MEMTEST_END 0x7fffffff 79*129ba616SKumar Gala #define CONFIG_PANIC_HANG /* do not reset board on panic */ 80*129ba616SKumar Gala 81*129ba616SKumar Gala /* 82*129ba616SKumar Gala * Base addresses -- Note these are effective addresses where the 83*129ba616SKumar Gala * actual resources get mapped (not physical addresses) 84*129ba616SKumar Gala */ 85*129ba616SKumar Gala #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 86*129ba616SKumar Gala #define CFG_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ 87*129ba616SKumar Gala #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ 88*129ba616SKumar Gala #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ 89*129ba616SKumar Gala 90*129ba616SKumar Gala #define CFG_PCIE3_ADDR (CFG_CCSRBAR+0x8000) 91*129ba616SKumar Gala #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) 92*129ba616SKumar Gala #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) 93*129ba616SKumar Gala 94*129ba616SKumar Gala /* DDR Setup */ 95*129ba616SKumar Gala #define CONFIG_FSL_DDR2 96*129ba616SKumar Gala #undef CONFIG_FSL_DDR_INTERACTIVE 97*129ba616SKumar Gala #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 98*129ba616SKumar Gala #define CONFIG_DDR_SPD 99*129ba616SKumar Gala #undef CONFIG_DDR_DLL 100*129ba616SKumar Gala 101*129ba616SKumar Gala #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 102*129ba616SKumar Gala 103*129ba616SKumar Gala #define CFG_DDR_SDRAM_BASE 0x00000000 104*129ba616SKumar Gala #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE 105*129ba616SKumar Gala 106*129ba616SKumar Gala #define CONFIG_NUM_DDR_CONTROLLERS 2 107*129ba616SKumar Gala #define CONFIG_DIMM_SLOTS_PER_CTLR 1 108*129ba616SKumar Gala #define CONFIG_CHIP_SELECTS_PER_CTRL 2 109*129ba616SKumar Gala 110*129ba616SKumar Gala /* I2C addresses of SPD EEPROMs */ 111*129ba616SKumar Gala #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 112*129ba616SKumar Gala #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 113*129ba616SKumar Gala 114*129ba616SKumar Gala /* These are used when DDR doesn't use SPD. */ 115*129ba616SKumar Gala #define CFG_SDRAM_SIZE 256 /* DDR is 256MB */ 116*129ba616SKumar Gala #define CFG_DDR_CS0_BNDS 0x0000001F 117*129ba616SKumar Gala #define CFG_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ 118*129ba616SKumar Gala #define CFG_DDR_TIMING_3 0x00000000 119*129ba616SKumar Gala #define CFG_DDR_TIMING_0 0x00260802 120*129ba616SKumar Gala #define CFG_DDR_TIMING_1 0x3935d322 121*129ba616SKumar Gala #define CFG_DDR_TIMING_2 0x14904cc8 122*129ba616SKumar Gala #define CFG_DDR_MODE_1 0x00480432 123*129ba616SKumar Gala #define CFG_DDR_MODE_2 0x00000000 124*129ba616SKumar Gala #define CFG_DDR_INTERVAL 0x06180100 125*129ba616SKumar Gala #define CFG_DDR_DATA_INIT 0xdeadbeef 126*129ba616SKumar Gala #define CFG_DDR_CLK_CTRL 0x03800000 127*129ba616SKumar Gala #define CFG_DDR_OCD_CTRL 0x00000000 128*129ba616SKumar Gala #define CFG_DDR_OCD_STATUS 0x00000000 129*129ba616SKumar Gala #define CFG_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ 130*129ba616SKumar Gala #define CFG_DDR_CONTROL2 0x04400010 131*129ba616SKumar Gala 132*129ba616SKumar Gala #define CFG_DDR_ERR_INT_EN 0x0000000d 133*129ba616SKumar Gala #define CFG_DDR_ERR_DIS 0x00000000 134*129ba616SKumar Gala #define CFG_DDR_SBE 0x00010000 135*129ba616SKumar Gala 136*129ba616SKumar Gala /* 137*129ba616SKumar Gala * FIXME: Not used in fixed_sdram function 138*129ba616SKumar Gala */ 139*129ba616SKumar Gala #define CFG_DDR_MODE 0x00000022 140*129ba616SKumar Gala #define CFG_DDR_CS1_BNDS 0x00000000 141*129ba616SKumar Gala #define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */ 142*129ba616SKumar Gala #define CFG_DDR_CS3_BNDS 0x00000FFF /* Not done */ 143*129ba616SKumar Gala #define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */ 144*129ba616SKumar Gala #define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */ 145*129ba616SKumar Gala 146*129ba616SKumar Gala /* 147*129ba616SKumar Gala * Make sure required options are set 148*129ba616SKumar Gala */ 149*129ba616SKumar Gala #ifndef CONFIG_SPD_EEPROM 150*129ba616SKumar Gala #error ("CONFIG_SPD_EEPROM is required") 151*129ba616SKumar Gala #endif 152*129ba616SKumar Gala 153*129ba616SKumar Gala #undef CONFIG_CLOCKS_IN_MHZ 154*129ba616SKumar Gala 155*129ba616SKumar Gala /* 156*129ba616SKumar Gala * Memory map 157*129ba616SKumar Gala * 158*129ba616SKumar Gala * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 159*129ba616SKumar Gala * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 160*129ba616SKumar Gala * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 161*129ba616SKumar Gala * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 162*129ba616SKumar Gala * 163*129ba616SKumar Gala * Localbus cacheable (TBD) 164*129ba616SKumar Gala * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 165*129ba616SKumar Gala * 166*129ba616SKumar Gala * Localbus non-cacheable 167*129ba616SKumar Gala * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 168*129ba616SKumar Gala * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 169*129ba616SKumar Gala * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 170*129ba616SKumar Gala * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 171*129ba616SKumar Gala * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 172*129ba616SKumar Gala */ 173*129ba616SKumar Gala 174*129ba616SKumar Gala /* 175*129ba616SKumar Gala * Local Bus Definitions 176*129ba616SKumar Gala */ 177*129ba616SKumar Gala #define CFG_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 178*129ba616SKumar Gala 179*129ba616SKumar Gala #define CFG_BR0_PRELIM 0xe8001001 180*129ba616SKumar Gala #define CFG_OR0_PRELIM 0xf8000ff7 181*129ba616SKumar Gala 182*129ba616SKumar Gala #define CFG_BR1_PRELIM 0xe0001001 183*129ba616SKumar Gala #define CFG_OR1_PRELIM 0xf8000ff7 184*129ba616SKumar Gala 185*129ba616SKumar Gala #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE + 0x8000000, CFG_FLASH_BASE} 186*129ba616SKumar Gala #define CFG_FLASH_QUIET_TEST 187*129ba616SKumar Gala #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 188*129ba616SKumar Gala 189*129ba616SKumar Gala #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ 190*129ba616SKumar Gala #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ 191*129ba616SKumar Gala #undef CFG_FLASH_CHECKSUM 192*129ba616SKumar Gala #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 193*129ba616SKumar Gala #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 194*129ba616SKumar Gala 195*129ba616SKumar Gala #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ 196*129ba616SKumar Gala 197*129ba616SKumar Gala #define CONFIG_FLASH_CFI_DRIVER 198*129ba616SKumar Gala #define CFG_FLASH_CFI 199*129ba616SKumar Gala #define CFG_FLASH_EMPTY_INFO 200*129ba616SKumar Gala #define CFG_FLASH_AMD_CHECK_DQ7 201*129ba616SKumar Gala 202*129ba616SKumar Gala #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 203*129ba616SKumar Gala 204*129ba616SKumar Gala #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 205*129ba616SKumar Gala #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 206*129ba616SKumar Gala 207*129ba616SKumar Gala #define CFG_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ 208*129ba616SKumar Gala #define CFG_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 209*129ba616SKumar Gala 210*129ba616SKumar Gala #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 211*129ba616SKumar Gala #define PIXIS_VER 0x1 /* Board version at offset 1 */ 212*129ba616SKumar Gala #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 213*129ba616SKumar Gala #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 214*129ba616SKumar Gala #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 215*129ba616SKumar Gala #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 216*129ba616SKumar Gala #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 217*129ba616SKumar Gala #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 218*129ba616SKumar Gala #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 219*129ba616SKumar Gala #define PIXIS_VCTL 0x10 /* VELA Control Register */ 220*129ba616SKumar Gala #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 221*129ba616SKumar Gala #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 222*129ba616SKumar Gala #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 223*129ba616SKumar Gala #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 224*129ba616SKumar Gala #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 225*129ba616SKumar Gala #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 226*129ba616SKumar Gala #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 227*129ba616SKumar Gala #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 228*129ba616SKumar Gala #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 229*129ba616SKumar Gala #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 230*129ba616SKumar Gala #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 231*129ba616SKumar Gala #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 232*129ba616SKumar Gala #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 233*129ba616SKumar Gala #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 234*129ba616SKumar Gala #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 235*129ba616SKumar Gala #define PIXIS_LED 0x25 /* LED Register */ 236*129ba616SKumar Gala 237*129ba616SKumar Gala /* old pixis referenced names */ 238*129ba616SKumar Gala #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 239*129ba616SKumar Gala #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 240*129ba616SKumar Gala #define CFG_PIXIS_VBOOT_MASK 0xc0 241*129ba616SKumar Gala 242*129ba616SKumar Gala /* define to use L1 as initial stack */ 243*129ba616SKumar Gala #define CONFIG_L1_INIT_RAM 244*129ba616SKumar Gala #define CFG_INIT_RAM_LOCK 1 245*129ba616SKumar Gala #define CFG_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 246*129ba616SKumar Gala #define CFG_INIT_RAM_END 0x00004000 /* End of used area in RAM */ 247*129ba616SKumar Gala 248*129ba616SKumar Gala #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ 249*129ba616SKumar Gala #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 250*129ba616SKumar Gala #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 251*129ba616SKumar Gala 252*129ba616SKumar Gala #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 253*129ba616SKumar Gala #define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 254*129ba616SKumar Gala 255*129ba616SKumar Gala /* Serial Port - controlled on board with jumper J8 256*129ba616SKumar Gala * open - index 2 257*129ba616SKumar Gala * shorted - index 1 258*129ba616SKumar Gala */ 259*129ba616SKumar Gala #define CONFIG_CONS_INDEX 1 260*129ba616SKumar Gala #undef CONFIG_SERIAL_SOFTWARE_FIFO 261*129ba616SKumar Gala #define CFG_NS16550 262*129ba616SKumar Gala #define CFG_NS16550_SERIAL 263*129ba616SKumar Gala #define CFG_NS16550_REG_SIZE 1 264*129ba616SKumar Gala #define CFG_NS16550_CLK get_bus_freq(0) 265*129ba616SKumar Gala 266*129ba616SKumar Gala #define CFG_BAUDRATE_TABLE \ 267*129ba616SKumar Gala {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 268*129ba616SKumar Gala 269*129ba616SKumar Gala #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) 270*129ba616SKumar Gala #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) 271*129ba616SKumar Gala 272*129ba616SKumar Gala /* Use the HUSH parser */ 273*129ba616SKumar Gala #define CFG_HUSH_PARSER 274*129ba616SKumar Gala #ifdef CFG_HUSH_PARSER 275*129ba616SKumar Gala #define CFG_PROMPT_HUSH_PS2 "> " 276*129ba616SKumar Gala #endif 277*129ba616SKumar Gala 278*129ba616SKumar Gala /* 279*129ba616SKumar Gala * Pass open firmware flat tree 280*129ba616SKumar Gala */ 281*129ba616SKumar Gala #define CONFIG_OF_LIBFDT 1 282*129ba616SKumar Gala #define CONFIG_OF_BOARD_SETUP 1 283*129ba616SKumar Gala #define CONFIG_OF_STDOUT_VIA_ALIAS 1 284*129ba616SKumar Gala 285*129ba616SKumar Gala #define CFG_64BIT_VSPRINTF 1 286*129ba616SKumar Gala #define CFG_64BIT_STRTOUL 1 287*129ba616SKumar Gala 288*129ba616SKumar Gala /* new uImage format support */ 289*129ba616SKumar Gala #define CONFIG_FIT 1 290*129ba616SKumar Gala #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ 291*129ba616SKumar Gala 292*129ba616SKumar Gala /* I2C */ 293*129ba616SKumar Gala #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 294*129ba616SKumar Gala #define CONFIG_HARD_I2C /* I2C with hardware support */ 295*129ba616SKumar Gala #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 296*129ba616SKumar Gala #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ 297*129ba616SKumar Gala #define CFG_I2C_EEPROM_ADDR 0x57 298*129ba616SKumar Gala #define CFG_I2C_SLAVE 0x7F 299*129ba616SKumar Gala #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ 300*129ba616SKumar Gala #define CFG_I2C_OFFSET 0x3100 301*129ba616SKumar Gala 302*129ba616SKumar Gala /* 303*129ba616SKumar Gala * General PCI 304*129ba616SKumar Gala * Memory space is mapped 1-1, but I/O space must start from 0. 305*129ba616SKumar Gala */ 306*129ba616SKumar Gala 307*129ba616SKumar Gala /* PCI view of System Memory */ 308*129ba616SKumar Gala #define CFG_PCI_MEMORY_BUS 0x00000000 309*129ba616SKumar Gala #define CFG_PCI_MEMORY_PHYS 0x00000000 310*129ba616SKumar Gala #define CFG_PCI_MEMORY_SIZE 0x80000000 311*129ba616SKumar Gala 312*129ba616SKumar Gala /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 313*129ba616SKumar Gala #define CFG_PCIE3_MEM_BASE 0x80000000 314*129ba616SKumar Gala #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE 315*129ba616SKumar Gala #define CFG_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 316*129ba616SKumar Gala #define CFG_PCIE3_IO_BASE 0x00000000 317*129ba616SKumar Gala #define CFG_PCIE3_IO_PHYS 0xffc00000 318*129ba616SKumar Gala #define CFG_PCIE3_IO_SIZE 0x00010000 /* 64k */ 319*129ba616SKumar Gala 320*129ba616SKumar Gala /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 321*129ba616SKumar Gala #define CFG_PCIE2_MEM_BASE 0xa0000000 322*129ba616SKumar Gala #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE 323*129ba616SKumar Gala #define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 324*129ba616SKumar Gala #define CFG_PCIE2_IO_BASE 0x00000000 325*129ba616SKumar Gala #define CFG_PCIE2_IO_PHYS 0xffc10000 326*129ba616SKumar Gala #define CFG_PCIE2_IO_SIZE 0x00010000 /* 64k */ 327*129ba616SKumar Gala 328*129ba616SKumar Gala /* controller 1, Slot 1, tgtid 1, Base address a000 */ 329*129ba616SKumar Gala #define CFG_PCIE1_MEM_BASE 0xc0000000 330*129ba616SKumar Gala #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE 331*129ba616SKumar Gala #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 332*129ba616SKumar Gala #define CFG_PCIE1_IO_BASE 0x00000000 333*129ba616SKumar Gala #define CFG_PCIE1_IO_PHYS 0xffc20000 334*129ba616SKumar Gala #define CFG_PCIE1_IO_SIZE 0x00010000 /* 64k */ 335*129ba616SKumar Gala 336*129ba616SKumar Gala #if defined(CONFIG_PCI) 337*129ba616SKumar Gala 338*129ba616SKumar Gala /*PCIE video card used*/ 339*129ba616SKumar Gala #define VIDEO_IO_OFFSET CFG_PCIE1_IO_PHYS 340*129ba616SKumar Gala 341*129ba616SKumar Gala /* video */ 342*129ba616SKumar Gala #define CONFIG_VIDEO 343*129ba616SKumar Gala 344*129ba616SKumar Gala #if defined(CONFIG_VIDEO) 345*129ba616SKumar Gala #define CONFIG_BIOSEMU 346*129ba616SKumar Gala #define CONFIG_CFB_CONSOLE 347*129ba616SKumar Gala #define CONFIG_VIDEO_SW_CURSOR 348*129ba616SKumar Gala #define CONFIG_VGA_AS_SINGLE_DEVICE 349*129ba616SKumar Gala #define CONFIG_ATI_RADEON_FB 350*129ba616SKumar Gala #define CONFIG_VIDEO_LOGO 351*129ba616SKumar Gala /*#define CONFIG_CONSOLE_CURSOR*/ 352*129ba616SKumar Gala #define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 353*129ba616SKumar Gala #endif 354*129ba616SKumar Gala 355*129ba616SKumar Gala #define CONFIG_NET_MULTI 356*129ba616SKumar Gala #define CONFIG_PCI_PNP /* do pci plug-and-play */ 357*129ba616SKumar Gala 358*129ba616SKumar Gala #undef CONFIG_EEPRO100 359*129ba616SKumar Gala #undef CONFIG_TULIP 360*129ba616SKumar Gala #undef CONFIG_RTL8139 361*129ba616SKumar Gala 362*129ba616SKumar Gala #ifdef CONFIG_RTL8139 363*129ba616SKumar Gala /* This macro is used by RTL8139 but not defined in PPC architecture */ 364*129ba616SKumar Gala #define KSEG1ADDR(x) (x) 365*129ba616SKumar Gala #define _IO_BASE 0x00000000 366*129ba616SKumar Gala #endif 367*129ba616SKumar Gala 368*129ba616SKumar Gala #ifndef CONFIG_PCI_PNP 369*129ba616SKumar Gala #define PCI_ENET0_IOADDR CFG_PCIE3_IO_BASE 370*129ba616SKumar Gala #define PCI_ENET0_MEMADDR CFG_PCIE3_IO_BASE 371*129ba616SKumar Gala #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 372*129ba616SKumar Gala #endif 373*129ba616SKumar Gala 374*129ba616SKumar Gala #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 375*129ba616SKumar Gala #define CONFIG_DOS_PARTITION 376*129ba616SKumar Gala #define CONFIG_SCSI_AHCI 377*129ba616SKumar Gala 378*129ba616SKumar Gala #ifdef CONFIG_SCSI_AHCI 379*129ba616SKumar Gala #define CONFIG_SATA_ULI5288 380*129ba616SKumar Gala #define CFG_SCSI_MAX_SCSI_ID 4 381*129ba616SKumar Gala #define CFG_SCSI_MAX_LUN 1 382*129ba616SKumar Gala #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) 383*129ba616SKumar Gala #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE 384*129ba616SKumar Gala #endif /* SCSI */ 385*129ba616SKumar Gala 386*129ba616SKumar Gala #endif /* CONFIG_PCI */ 387*129ba616SKumar Gala 388*129ba616SKumar Gala 389*129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 390*129ba616SKumar Gala 391*129ba616SKumar Gala #ifndef CONFIG_NET_MULTI 392*129ba616SKumar Gala #define CONFIG_NET_MULTI 1 393*129ba616SKumar Gala #endif 394*129ba616SKumar Gala 395*129ba616SKumar Gala #define CONFIG_MII 1 /* MII PHY management */ 396*129ba616SKumar Gala #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 397*129ba616SKumar Gala #define CONFIG_TSEC1 1 398*129ba616SKumar Gala #define CONFIG_TSEC1_NAME "eTSEC1" 399*129ba616SKumar Gala #define CONFIG_TSEC2 1 400*129ba616SKumar Gala #define CONFIG_TSEC2_NAME "eTSEC2" 401*129ba616SKumar Gala #define CONFIG_TSEC3 1 402*129ba616SKumar Gala #define CONFIG_TSEC3_NAME "eTSEC3" 403*129ba616SKumar Gala #define CONFIG_TSEC4 1 404*129ba616SKumar Gala #define CONFIG_TSEC4_NAME "eTSEC4" 405*129ba616SKumar Gala 406*129ba616SKumar Gala #define TSEC1_PHY_ADDR 0 407*129ba616SKumar Gala #define TSEC2_PHY_ADDR 1 408*129ba616SKumar Gala #define TSEC3_PHY_ADDR 2 409*129ba616SKumar Gala #define TSEC4_PHY_ADDR 3 410*129ba616SKumar Gala 411*129ba616SKumar Gala #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 412*129ba616SKumar Gala #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 413*129ba616SKumar Gala #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 414*129ba616SKumar Gala #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 415*129ba616SKumar Gala 416*129ba616SKumar Gala #define TSEC1_PHYIDX 0 417*129ba616SKumar Gala #define TSEC2_PHYIDX 0 418*129ba616SKumar Gala #define TSEC3_PHYIDX 0 419*129ba616SKumar Gala #define TSEC4_PHYIDX 0 420*129ba616SKumar Gala 421*129ba616SKumar Gala #define CONFIG_ETHPRIME "eTSEC1" 422*129ba616SKumar Gala 423*129ba616SKumar Gala #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 424*129ba616SKumar Gala #endif /* CONFIG_TSEC_ENET */ 425*129ba616SKumar Gala 426*129ba616SKumar Gala /* 427*129ba616SKumar Gala * Environment 428*129ba616SKumar Gala */ 429*129ba616SKumar Gala #define CFG_ENV_IS_IN_FLASH 1 430*129ba616SKumar Gala #if CFG_MONITOR_BASE > 0xfff80000 431*129ba616SKumar Gala #define CFG_ENV_ADDR 0xfff80000 432*129ba616SKumar Gala #else 433*129ba616SKumar Gala #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x70000) 434*129ba616SKumar Gala #endif 435*129ba616SKumar Gala #define CFG_ENV_SIZE 0x2000 436*129ba616SKumar Gala #define CFG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 437*129ba616SKumar Gala 438*129ba616SKumar Gala #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 439*129ba616SKumar Gala #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 440*129ba616SKumar Gala 441*129ba616SKumar Gala /* 442*129ba616SKumar Gala * Command line configuration. 443*129ba616SKumar Gala */ 444*129ba616SKumar Gala #include <config_cmd_default.h> 445*129ba616SKumar Gala 446*129ba616SKumar Gala #define CONFIG_CMD_IRQ 447*129ba616SKumar Gala #define CONFIG_CMD_PING 448*129ba616SKumar Gala #define CONFIG_CMD_I2C 449*129ba616SKumar Gala #define CONFIG_CMD_MII 450*129ba616SKumar Gala #define CONFIG_CMD_ELF 451*129ba616SKumar Gala 452*129ba616SKumar Gala #if defined(CONFIG_PCI) 453*129ba616SKumar Gala #define CONFIG_CMD_PCI 454*129ba616SKumar Gala #define CONFIG_CMD_BEDBUG 455*129ba616SKumar Gala #define CONFIG_CMD_NET 456*129ba616SKumar Gala #define CONFIG_CMD_SCSI 457*129ba616SKumar Gala #define CONFIG_CMD_EXT2 458*129ba616SKumar Gala #endif 459*129ba616SKumar Gala 460*129ba616SKumar Gala #undef CONFIG_WATCHDOG /* watchdog disabled */ 461*129ba616SKumar Gala 462*129ba616SKumar Gala /* 463*129ba616SKumar Gala * Miscellaneous configurable options 464*129ba616SKumar Gala */ 465*129ba616SKumar Gala #define CFG_LONGHELP /* undef to save memory */ 466*129ba616SKumar Gala #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 467*129ba616SKumar Gala #define CFG_LOAD_ADDR 0x2000000 /* default load address */ 468*129ba616SKumar Gala #define CFG_PROMPT "=> " /* Monitor Command Prompt */ 469*129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 470*129ba616SKumar Gala #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 471*129ba616SKumar Gala #else 472*129ba616SKumar Gala #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 473*129ba616SKumar Gala #endif 474*129ba616SKumar Gala #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 475*129ba616SKumar Gala #define CFG_MAXARGS 16 /* max number of command args */ 476*129ba616SKumar Gala #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 477*129ba616SKumar Gala #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ 478*129ba616SKumar Gala 479*129ba616SKumar Gala /* 480*129ba616SKumar Gala * For booting Linux, the board info and command line data 481*129ba616SKumar Gala * have to be in the first 8 MB of memory, since this is 482*129ba616SKumar Gala * the maximum mapped by the Linux kernel during initialization. 483*129ba616SKumar Gala */ 484*129ba616SKumar Gala #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ 485*129ba616SKumar Gala 486*129ba616SKumar Gala /* 487*129ba616SKumar Gala * Internal Definitions 488*129ba616SKumar Gala * 489*129ba616SKumar Gala * Boot Flags 490*129ba616SKumar Gala */ 491*129ba616SKumar Gala #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 492*129ba616SKumar Gala #define BOOTFLAG_WARM 0x02 /* Software reboot */ 493*129ba616SKumar Gala 494*129ba616SKumar Gala #if defined(CONFIG_CMD_KGDB) 495*129ba616SKumar Gala #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 496*129ba616SKumar Gala #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 497*129ba616SKumar Gala #endif 498*129ba616SKumar Gala 499*129ba616SKumar Gala /* 500*129ba616SKumar Gala * Environment Configuration 501*129ba616SKumar Gala */ 502*129ba616SKumar Gala 503*129ba616SKumar Gala /* The mac addresses for all ethernet interface */ 504*129ba616SKumar Gala #if defined(CONFIG_TSEC_ENET) 505*129ba616SKumar Gala #define CONFIG_HAS_ETH0 506*129ba616SKumar Gala #define CONFIG_ETHADDR 00:E0:0C:02:00:FD 507*129ba616SKumar Gala #define CONFIG_HAS_ETH1 508*129ba616SKumar Gala #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD 509*129ba616SKumar Gala #define CONFIG_HAS_ETH2 510*129ba616SKumar Gala #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD 511*129ba616SKumar Gala #define CONFIG_HAS_ETH3 512*129ba616SKumar Gala #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD 513*129ba616SKumar Gala #endif 514*129ba616SKumar Gala 515*129ba616SKumar Gala #define CONFIG_IPADDR 192.168.1.254 516*129ba616SKumar Gala 517*129ba616SKumar Gala #define CONFIG_HOSTNAME unknown 518*129ba616SKumar Gala #define CONFIG_ROOTPATH /opt/nfsroot 519*129ba616SKumar Gala #define CONFIG_BOOTFILE uImage 520*129ba616SKumar Gala #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 521*129ba616SKumar Gala 522*129ba616SKumar Gala #define CONFIG_SERVERIP 192.168.1.1 523*129ba616SKumar Gala #define CONFIG_GATEWAYIP 192.168.1.1 524*129ba616SKumar Gala #define CONFIG_NETMASK 255.255.255.0 525*129ba616SKumar Gala 526*129ba616SKumar Gala /* default location for tftp and bootm */ 527*129ba616SKumar Gala #define CONFIG_LOADADDR 1000000 528*129ba616SKumar Gala 529*129ba616SKumar Gala #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 530*129ba616SKumar Gala #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ 531*129ba616SKumar Gala 532*129ba616SKumar Gala #define CONFIG_BAUDRATE 115200 533*129ba616SKumar Gala 534*129ba616SKumar Gala #define CONFIG_EXTRA_ENV_SETTINGS \ 535*129ba616SKumar Gala "netdev=eth0\0" \ 536*129ba616SKumar Gala "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 537*129ba616SKumar Gala "tftpflash=tftpboot $loadaddr $uboot; " \ 538*129ba616SKumar Gala "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ 539*129ba616SKumar Gala "erase " MK_STR(TEXT_BASE) " +$filesize; " \ 540*129ba616SKumar Gala "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ 541*129ba616SKumar Gala "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ 542*129ba616SKumar Gala "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ 543*129ba616SKumar Gala "consoledev=ttyS0\0" \ 544*129ba616SKumar Gala "ramdiskaddr=2000000\0" \ 545*129ba616SKumar Gala "ramdiskfile=8572ds/ramdisk.uboot\0" \ 546*129ba616SKumar Gala "fdtaddr=c00000\0" \ 547*129ba616SKumar Gala "fdtfile=8572ds/mpc8572ds.dtb\0" \ 548*129ba616SKumar Gala "bdev=sda3\0" 549*129ba616SKumar Gala 550*129ba616SKumar Gala #define CONFIG_HDBOOT \ 551*129ba616SKumar Gala "setenv bootargs root=/dev/$bdev rw " \ 552*129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 553*129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 554*129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 555*129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 556*129ba616SKumar Gala 557*129ba616SKumar Gala #define CONFIG_NFSBOOTCOMMAND \ 558*129ba616SKumar Gala "setenv bootargs root=/dev/nfs rw " \ 559*129ba616SKumar Gala "nfsroot=$serverip:$rootpath " \ 560*129ba616SKumar Gala "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 561*129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 562*129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 563*129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 564*129ba616SKumar Gala "bootm $loadaddr - $fdtaddr" 565*129ba616SKumar Gala 566*129ba616SKumar Gala #define CONFIG_RAMBOOTCOMMAND \ 567*129ba616SKumar Gala "setenv bootargs root=/dev/ram rw " \ 568*129ba616SKumar Gala "console=$consoledev,$baudrate $othbootargs;" \ 569*129ba616SKumar Gala "tftp $ramdiskaddr $ramdiskfile;" \ 570*129ba616SKumar Gala "tftp $loadaddr $bootfile;" \ 571*129ba616SKumar Gala "tftp $fdtaddr $fdtfile;" \ 572*129ba616SKumar Gala "bootm $loadaddr $ramdiskaddr $fdtaddr" 573*129ba616SKumar Gala 574*129ba616SKumar Gala #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 575*129ba616SKumar Gala 576*129ba616SKumar Gala #endif /* __CONFIG_H */ 577