1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8569mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8569 1 /* MPC8569 specific */ 34 #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ 35 36 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ 37 38 #define CONFIG_SYS_SRIO 39 #define CONFIG_SRIO1 /* SRIO port 1 */ 40 41 #define CONFIG_PCI 1 /* Disable PCI/PCIE */ 42 #define CONFIG_PCIE1 1 /* PCIE controller */ 43 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 44 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 45 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 46 #define CONFIG_QE /* Enable QE */ 47 #define CONFIG_ENV_OVERWRITE 48 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 49 50 #ifndef __ASSEMBLY__ 51 extern unsigned long get_clock_freq(void); 52 #endif 53 /* Replace a call to get_clock_freq (after it is implemented)*/ 54 #define CONFIG_SYS_CLK_FREQ 66666666 55 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 56 57 #ifdef CONFIG_ATM 58 #define CONFIG_PQ_MDS_PIB 59 #define CONFIG_PQ_MDS_PIB_ATM 60 #endif 61 62 /* 63 * These can be toggled for performance analysis, otherwise use default. 64 */ 65 #define CONFIG_L2_CACHE /* toggle L2 cache */ 66 #define CONFIG_BTB /* toggle branch predition */ 67 68 #ifdef CONFIG_NAND 69 #define CONFIG_NAND_U_BOOT 1 70 #define CONFIG_RAMBOOT_NAND 1 71 #ifdef CONFIG_NAND_SPL 72 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 73 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 74 #else 75 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds 76 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 77 #endif 78 #endif 79 80 #ifndef CONFIG_SYS_TEXT_BASE 81 #define CONFIG_SYS_TEXT_BASE 0xfff80000 82 #endif 83 84 #ifndef CONFIG_SYS_MONITOR_BASE 85 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 86 #endif 87 88 /* 89 * Only possible on E500 Version 2 or newer cores. 90 */ 91 #define CONFIG_ENABLE_36BIT_PHYS 1 92 93 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 94 #define CONFIG_BOARD_EARLY_INIT_R 1 95 #define CONFIG_HWCONFIG 96 97 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 98 #define CONFIG_SYS_MEMTEST_END 0x00400000 99 100 /* 101 * Config the L2 Cache as L2 SRAM 102 */ 103 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 104 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 105 #define CONFIG_SYS_L2_SIZE (512 << 10) 106 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 107 108 /* 109 * Base addresses -- Note these are effective addresses where the 110 * actual resources get mapped (not physical addresses) 111 */ 112 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 113 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 114 /* physical addr of CCSRBAR */ 115 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 116 /* PQII uses CONFIG_SYS_IMMR */ 117 118 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) 119 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR 120 #else 121 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 122 #endif 123 124 /* DDR Setup */ 125 #define CONFIG_FSL_DDR3 126 #undef CONFIG_FSL_DDR_INTERACTIVE 127 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 128 #define CONFIG_DDR_SPD 129 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 130 131 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 132 133 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 134 /* DDR is system memory*/ 135 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 136 137 #define CONFIG_NUM_DDR_CONTROLLERS 1 138 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 139 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 140 141 /* I2C addresses of SPD EEPROMs */ 142 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 143 144 /* These are used when DDR doesn't use SPD. */ 145 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 146 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 147 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 148 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 149 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 150 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 151 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 152 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 153 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 154 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 155 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 156 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 157 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 158 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 159 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 160 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 161 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 162 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 163 #define CONFIG_SYS_DDR_CDR_1 0x80040000 164 #define CONFIG_SYS_DDR_CDR_2 0x00000000 165 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 166 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 167 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 168 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 169 170 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 171 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 172 #define CONFIG_SYS_DDR_SBE 0x00010000 173 174 #undef CONFIG_CLOCKS_IN_MHZ 175 176 /* 177 * Local Bus Definitions 178 */ 179 180 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 181 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 182 183 #define CONFIG_SYS_BCSR_BASE 0xf8000000 184 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 185 186 /*Chip select 0 - Flash*/ 187 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 188 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 189 190 /*Chip select 1 - BCSR*/ 191 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 192 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 193 194 /*Chip select 4 - PIB*/ 195 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 196 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 197 198 /*Chip select 5 - PIB*/ 199 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 200 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 201 202 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 203 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 204 #undef CONFIG_SYS_FLASH_CHECKSUM 205 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 206 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 207 208 #if defined(CONFIG_RAMBOOT_NAND) 209 #define CONFIG_SYS_RAMBOOT 210 #define CONFIG_SYS_EXTRA_ENV_RELOC 211 #else 212 #undef CONFIG_SYS_RAMBOOT 213 #endif 214 215 #define CONFIG_FLASH_CFI_DRIVER 216 #define CONFIG_SYS_FLASH_CFI 217 #define CONFIG_SYS_FLASH_EMPTY_INFO 218 219 /* Chip select 3 - NAND */ 220 #ifndef CONFIG_NAND_SPL 221 #define CONFIG_SYS_NAND_BASE 0xFC000000 222 #else 223 #define CONFIG_SYS_NAND_BASE 0xFFF00000 224 #endif 225 226 /* NAND boot: 4K NAND loader config */ 227 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 228 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 229 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 230 #define CONFIG_SYS_NAND_U_BOOT_START \ 231 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 232 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 233 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 234 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 235 236 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 237 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 238 #define CONFIG_SYS_MAX_NAND_DEVICE 1 239 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 240 #define CONFIG_CMD_NAND 1 241 #define CONFIG_NAND_FSL_ELBC 1 242 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 243 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 244 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 245 | BR_PS_8 /* Port Size = 8 bit */ \ 246 | BR_MS_FCM /* MSEL = FCM */ \ 247 | BR_V) /* valid */ 248 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 249 | OR_FCM_CSCT \ 250 | OR_FCM_CST \ 251 | OR_FCM_CHT \ 252 | OR_FCM_SCY_1 \ 253 | OR_FCM_TRLX \ 254 | OR_FCM_EHTR) 255 256 #ifdef CONFIG_RAMBOOT_NAND 257 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 258 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */ 259 #define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 260 #define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 261 #else 262 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 263 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 264 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 265 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 266 #endif 267 268 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 269 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 270 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 271 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 272 273 #define CONFIG_SYS_INIT_RAM_LOCK 1 274 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 275 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 276 277 #define CONFIG_SYS_GBL_DATA_OFFSET \ 278 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 279 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 280 281 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 282 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 283 284 /* Serial Port */ 285 #define CONFIG_CONS_INDEX 1 286 #define CONFIG_SERIAL_MULTI 1 287 #define CONFIG_SYS_NS16550 288 #define CONFIG_SYS_NS16550_SERIAL 289 #define CONFIG_SYS_NS16550_REG_SIZE 1 290 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 291 #ifdef CONFIG_NAND_SPL 292 #define CONFIG_NS16550_MIN_FUNCTIONS 293 #endif 294 295 #define CONFIG_SYS_BAUDRATE_TABLE \ 296 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 297 298 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 299 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 300 301 /* Use the HUSH parser*/ 302 #define CONFIG_SYS_HUSH_PARSER 303 #ifdef CONFIG_SYS_HUSH_PARSER 304 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 305 #endif 306 307 /* pass open firmware flat tree */ 308 #define CONFIG_OF_LIBFDT 1 309 #define CONFIG_OF_BOARD_SETUP 1 310 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 311 312 /* 313 * I2C 314 */ 315 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 316 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 317 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 318 #define CONFIG_I2C_MULTI_BUS 319 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 320 #define CONFIG_SYS_I2C_SLAVE 0x7F 321 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 322 #define CONFIG_SYS_I2C_OFFSET 0x3000 323 #define CONFIG_SYS_I2C2_OFFSET 0x3100 324 325 /* 326 * I2C2 EEPROM 327 */ 328 #define CONFIG_ID_EEPROM 329 #ifdef CONFIG_ID_EEPROM 330 #define CONFIG_SYS_I2C_EEPROM_NXID 331 #endif 332 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 333 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 334 #define CONFIG_SYS_EEPROM_BUS_NUM 1 335 336 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 337 #define PLPPAR1_I2C2_VAL 0x00000000 338 #define PLPPAR1_ESDHC_VAL 0x0000000A 339 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 340 #define PLPDIR1_I2C2_VAL 0x0000000F 341 #define PLPDIR1_ESDHC_VAL 0x00000006 342 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 343 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 344 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 345 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 346 347 /* 348 * General PCI 349 * Memory Addresses are mapped 1-1. I/O is mapped from 0 350 */ 351 #define CONFIG_SYS_PCIE1_NAME "Slot" 352 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 353 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 354 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 355 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 356 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 357 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 358 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 359 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 360 361 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 362 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 363 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 364 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 365 366 #ifdef CONFIG_QE 367 /* 368 * QE UEC ethernet configuration 369 */ 370 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 371 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 372 373 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 374 #define CONFIG_UEC_ETH 375 #define CONFIG_ETHPRIME "UEC0" 376 #define CONFIG_PHY_MODE_NEED_CHANGE 377 378 #define CONFIG_UEC_ETH1 /* GETH1 */ 379 #define CONFIG_HAS_ETH0 380 381 #ifdef CONFIG_UEC_ETH1 382 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 383 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 384 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 385 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 386 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 387 #define CONFIG_SYS_UEC1_PHY_ADDR 7 388 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID 389 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 390 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 391 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 392 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 393 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 394 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII 395 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 396 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 397 #endif /* CONFIG_UEC_ETH1 */ 398 399 #define CONFIG_UEC_ETH2 /* GETH2 */ 400 #define CONFIG_HAS_ETH1 401 402 #ifdef CONFIG_UEC_ETH2 403 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 404 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 405 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 406 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 407 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 408 #define CONFIG_SYS_UEC2_PHY_ADDR 1 409 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID 410 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 411 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 412 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 413 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 414 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 415 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII 416 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 417 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 418 #endif /* CONFIG_UEC_ETH2 */ 419 420 #define CONFIG_UEC_ETH3 /* GETH3 */ 421 #define CONFIG_HAS_ETH2 422 423 #ifdef CONFIG_UEC_ETH3 424 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 425 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 426 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 427 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 428 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 429 #define CONFIG_SYS_UEC3_PHY_ADDR 2 430 #define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID 431 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 432 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 433 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 434 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 435 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 436 #define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII 437 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 438 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 439 #endif /* CONFIG_UEC_ETH3 */ 440 441 #define CONFIG_UEC_ETH4 /* GETH4 */ 442 #define CONFIG_HAS_ETH3 443 444 #ifdef CONFIG_UEC_ETH4 445 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 446 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 447 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 448 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 449 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 450 #define CONFIG_SYS_UEC4_PHY_ADDR 3 451 #define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID 452 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 453 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 454 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 455 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 456 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 457 #define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII 458 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 459 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 460 #endif /* CONFIG_UEC_ETH4 */ 461 462 #undef CONFIG_UEC_ETH6 /* GETH6 */ 463 #define CONFIG_HAS_ETH5 464 465 #ifdef CONFIG_UEC_ETH6 466 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 467 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 468 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 469 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 470 #define CONFIG_SYS_UEC6_PHY_ADDR 4 471 #define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII 472 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 473 #endif /* CONFIG_UEC_ETH6 */ 474 475 #undef CONFIG_UEC_ETH8 /* GETH8 */ 476 #define CONFIG_HAS_ETH7 477 478 #ifdef CONFIG_UEC_ETH8 479 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 480 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 481 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 482 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 483 #define CONFIG_SYS_UEC8_PHY_ADDR 6 484 #define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII 485 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 486 #endif /* CONFIG_UEC_ETH8 */ 487 488 #endif /* CONFIG_QE */ 489 490 #if defined(CONFIG_PCI) 491 492 #define CONFIG_NET_MULTI 493 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 494 495 #undef CONFIG_EEPRO100 496 #undef CONFIG_TULIP 497 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 498 499 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 500 501 #endif /* CONFIG_PCI */ 502 503 #ifndef CONFIG_NET_MULTI 504 #define CONFIG_NET_MULTI 1 505 #endif 506 507 /* 508 * Environment 509 */ 510 #if defined(CONFIG_SYS_RAMBOOT) 511 #if defined(CONFIG_RAMBOOT_NAND) 512 #define CONFIG_ENV_IS_IN_NAND 1 513 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 514 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 515 #endif 516 #else 517 #define CONFIG_ENV_IS_IN_FLASH 1 518 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 519 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 520 #define CONFIG_ENV_SIZE 0x2000 521 #endif 522 523 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 524 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 525 526 /* QE microcode/firmware address */ 527 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 528 529 /* 530 * BOOTP options 531 */ 532 #define CONFIG_BOOTP_BOOTFILESIZE 533 #define CONFIG_BOOTP_BOOTPATH 534 #define CONFIG_BOOTP_GATEWAY 535 #define CONFIG_BOOTP_HOSTNAME 536 537 538 /* 539 * Command line configuration. 540 */ 541 #include <config_cmd_default.h> 542 543 #define CONFIG_CMD_PING 544 #define CONFIG_CMD_I2C 545 #define CONFIG_CMD_MII 546 #define CONFIG_CMD_ELF 547 #define CONFIG_CMD_IRQ 548 #define CONFIG_CMD_SETEXPR 549 #define CONFIG_CMD_REGINFO 550 551 #if defined(CONFIG_PCI) 552 #define CONFIG_CMD_PCI 553 #endif 554 555 556 #undef CONFIG_WATCHDOG /* watchdog disabled */ 557 558 #define CONFIG_MMC 1 559 560 #ifdef CONFIG_MMC 561 #define CONFIG_FSL_ESDHC 562 #define CONFIG_FSL_ESDHC_PIN_MUX 563 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 564 #define CONFIG_CMD_MMC 565 #define CONFIG_GENERIC_MMC 566 #define CONFIG_CMD_EXT2 567 #define CONFIG_CMD_FAT 568 #define CONFIG_DOS_PARTITION 569 #endif 570 571 /* 572 * Miscellaneous configurable options 573 */ 574 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 575 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 576 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 577 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 578 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 579 #if defined(CONFIG_CMD_KGDB) 580 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 581 #else 582 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 583 #endif 584 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 585 /* Print Buffer Size */ 586 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 587 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 588 /* Boot Argument Buffer Size */ 589 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 590 591 /* 592 * For booting Linux, the board info and command line data 593 * have to be in the first 16 MB of memory, since this is 594 * the maximum mapped by the Linux kernel during initialization. 595 */ 596 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 597 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 598 599 #if defined(CONFIG_CMD_KGDB) 600 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 601 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 602 #endif 603 604 /* 605 * Environment Configuration 606 */ 607 #define CONFIG_HOSTNAME mpc8569mds 608 #define CONFIG_ROOTPATH /nfsroot 609 #define CONFIG_BOOTFILE your.uImage 610 611 #define CONFIG_SERVERIP 192.168.1.1 612 #define CONFIG_GATEWAYIP 192.168.1.1 613 #define CONFIG_NETMASK 255.255.255.0 614 615 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 616 617 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 618 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 619 620 #define CONFIG_BAUDRATE 115200 621 622 #define CONFIG_EXTRA_ENV_SETTINGS \ 623 "netdev=eth0\0" \ 624 "consoledev=ttyS0\0" \ 625 "ramdiskaddr=600000\0" \ 626 "ramdiskfile=your.ramdisk.u-boot\0" \ 627 "fdtaddr=400000\0" \ 628 "fdtfile=your.fdt.dtb\0" \ 629 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 630 "nfsroot=$serverip:$rootpath " \ 631 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 632 "console=$consoledev,$baudrate $othbootargs\0" \ 633 "ramargs=setenv bootargs root=/dev/ram rw " \ 634 "console=$consoledev,$baudrate $othbootargs\0" \ 635 636 #define CONFIG_NFSBOOTCOMMAND \ 637 "run nfsargs;" \ 638 "tftp $loadaddr $bootfile;" \ 639 "tftp $fdtaddr $fdtfile;" \ 640 "bootm $loadaddr - $fdtaddr" 641 642 #define CONFIG_RAMBOOTCOMMAND \ 643 "run ramargs;" \ 644 "tftp $ramdiskaddr $ramdiskfile;" \ 645 "tftp $loadaddr $bootfile;" \ 646 "bootm $loadaddr $ramdiskaddr" 647 648 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 649 650 #endif /* __CONFIG_H */ 651