1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2009-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * mpc8569mds board configuration file 8 */ 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #define CONFIG_SYS_SRIO 13 #define CONFIG_SRIO1 /* SRIO port 1 */ 14 15 #define CONFIG_PCIE1 1 /* PCIE controller */ 16 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 17 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 18 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 19 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 20 #define CONFIG_QE /* Enable QE */ 21 #define CONFIG_ENV_OVERWRITE 22 23 #ifndef __ASSEMBLY__ 24 extern unsigned long get_clock_freq(void); 25 #endif 26 /* Replace a call to get_clock_freq (after it is implemented)*/ 27 #define CONFIG_SYS_CLK_FREQ 66666666 28 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 29 30 #ifdef CONFIG_ATM 31 #define CONFIG_PQ_MDS_PIB 32 #define CONFIG_PQ_MDS_PIB_ATM 33 #endif 34 35 /* 36 * These can be toggled for performance analysis, otherwise use default. 37 */ 38 #define CONFIG_L2_CACHE /* toggle L2 cache */ 39 #define CONFIG_BTB /* toggle branch predition */ 40 41 #ifndef CONFIG_SYS_MONITOR_BASE 42 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 43 #endif 44 45 /* 46 * Only possible on E500 Version 2 or newer cores. 47 */ 48 #define CONFIG_ENABLE_36BIT_PHYS 1 49 50 #define CONFIG_HWCONFIG 51 52 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 53 #define CONFIG_SYS_MEMTEST_END 0x00400000 54 55 /* 56 * Config the L2 Cache as L2 SRAM 57 */ 58 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 59 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 60 #define CONFIG_SYS_L2_SIZE (512 << 10) 61 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 62 63 #define CONFIG_SYS_CCSRBAR 0xe0000000 64 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 65 66 #if defined(CONFIG_NAND_SPL) 67 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 68 #endif 69 70 /* DDR Setup */ 71 #undef CONFIG_FSL_DDR_INTERACTIVE 72 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 73 #define CONFIG_DDR_SPD 74 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 75 76 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 77 78 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 79 /* DDR is system memory*/ 80 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 81 82 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 83 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 84 85 /* I2C addresses of SPD EEPROMs */ 86 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 87 88 /* These are used when DDR doesn't use SPD. */ 89 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 90 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 91 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 92 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 93 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 94 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 95 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 96 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 97 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 98 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 99 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 100 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 101 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 102 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 103 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 104 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 105 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 106 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 107 #define CONFIG_SYS_DDR_CDR_1 0x80040000 108 #define CONFIG_SYS_DDR_CDR_2 0x00000000 109 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 110 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 111 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 112 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 113 114 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 115 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 116 #define CONFIG_SYS_DDR_SBE 0x00010000 117 118 #undef CONFIG_CLOCKS_IN_MHZ 119 120 /* 121 * Local Bus Definitions 122 */ 123 124 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 125 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 126 127 #define CONFIG_SYS_BCSR_BASE 0xf8000000 128 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 129 130 /*Chip select 0 - Flash*/ 131 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 132 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 133 134 /*Chip select 1 - BCSR*/ 135 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 136 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 137 138 /*Chip select 4 - PIB*/ 139 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 140 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 141 142 /*Chip select 5 - PIB*/ 143 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 144 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 145 146 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 147 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 148 #undef CONFIG_SYS_FLASH_CHECKSUM 149 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 150 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 151 152 #undef CONFIG_SYS_RAMBOOT 153 154 #define CONFIG_FLASH_CFI_DRIVER 155 #define CONFIG_SYS_FLASH_CFI 156 #define CONFIG_SYS_FLASH_EMPTY_INFO 157 158 /* Chip select 3 - NAND */ 159 #ifndef CONFIG_NAND_SPL 160 #define CONFIG_SYS_NAND_BASE 0xFC000000 161 #else 162 #define CONFIG_SYS_NAND_BASE 0xFFF00000 163 #endif 164 165 /* NAND boot: 4K NAND loader config */ 166 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 167 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 168 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 169 #define CONFIG_SYS_NAND_U_BOOT_START \ 170 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 171 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 172 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 173 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 174 175 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 176 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 177 #define CONFIG_SYS_MAX_NAND_DEVICE 1 178 #define CONFIG_NAND_FSL_ELBC 1 179 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 180 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 181 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 182 | BR_PS_8 /* Port Size = 8 bit */ \ 183 | BR_MS_FCM /* MSEL = FCM */ \ 184 | BR_V) /* valid */ 185 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 186 | OR_FCM_CSCT \ 187 | OR_FCM_CST \ 188 | OR_FCM_CHT \ 189 | OR_FCM_SCY_1 \ 190 | OR_FCM_TRLX \ 191 | OR_FCM_EHTR) 192 193 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 194 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 195 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 196 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 197 198 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 199 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 200 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 201 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 202 203 #define CONFIG_SYS_INIT_RAM_LOCK 1 204 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 205 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 206 207 #define CONFIG_SYS_GBL_DATA_OFFSET \ 208 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 209 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 210 211 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 212 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 213 214 /* Serial Port */ 215 #define CONFIG_SYS_NS16550_SERIAL 216 #define CONFIG_SYS_NS16550_REG_SIZE 1 217 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 218 #ifdef CONFIG_NAND_SPL 219 #define CONFIG_NS16550_MIN_FUNCTIONS 220 #endif 221 222 #define CONFIG_SYS_BAUDRATE_TABLE \ 223 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 224 225 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 226 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 227 228 /* 229 * I2C 230 */ 231 #define CONFIG_SYS_I2C 232 #define CONFIG_SYS_I2C_FSL 233 #define CONFIG_SYS_FSL_I2C_SPEED 400000 234 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 235 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 236 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 237 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 238 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 239 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 240 241 /* 242 * I2C2 EEPROM 243 */ 244 #define CONFIG_ID_EEPROM 245 #ifdef CONFIG_ID_EEPROM 246 #define CONFIG_SYS_I2C_EEPROM_NXID 247 #endif 248 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 249 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 250 #define CONFIG_SYS_EEPROM_BUS_NUM 1 251 252 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 253 #define PLPPAR1_I2C2_VAL 0x00000000 254 #define PLPPAR1_ESDHC_VAL 0x0000000A 255 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 256 #define PLPDIR1_I2C2_VAL 0x0000000F 257 #define PLPDIR1_ESDHC_VAL 0x00000006 258 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 259 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 260 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 261 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 262 263 /* 264 * General PCI 265 * Memory Addresses are mapped 1-1. I/O is mapped from 0 266 */ 267 #define CONFIG_SYS_PCIE1_NAME "Slot" 268 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 269 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 270 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 271 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 272 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 273 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 274 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 275 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 276 277 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 278 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 279 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 280 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 281 282 #ifdef CONFIG_QE 283 /* 284 * QE UEC ethernet configuration 285 */ 286 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 287 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 288 289 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 290 #define CONFIG_UEC_ETH 291 #define CONFIG_ETHPRIME "UEC0" 292 #define CONFIG_PHY_MODE_NEED_CHANGE 293 294 #define CONFIG_UEC_ETH1 /* GETH1 */ 295 #define CONFIG_HAS_ETH0 296 297 #ifdef CONFIG_UEC_ETH1 298 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 299 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 300 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 301 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 302 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 303 #define CONFIG_SYS_UEC1_PHY_ADDR 7 304 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 305 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 306 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 307 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 308 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 309 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 310 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 311 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 312 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 313 #endif /* CONFIG_UEC_ETH1 */ 314 315 #define CONFIG_UEC_ETH2 /* GETH2 */ 316 #define CONFIG_HAS_ETH1 317 318 #ifdef CONFIG_UEC_ETH2 319 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 320 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 321 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 322 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 323 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 324 #define CONFIG_SYS_UEC2_PHY_ADDR 1 325 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 326 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 327 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 328 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 329 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 330 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 331 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 332 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 333 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 334 #endif /* CONFIG_UEC_ETH2 */ 335 336 #define CONFIG_UEC_ETH3 /* GETH3 */ 337 #define CONFIG_HAS_ETH2 338 339 #ifdef CONFIG_UEC_ETH3 340 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 341 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 342 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 343 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 344 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 345 #define CONFIG_SYS_UEC3_PHY_ADDR 2 346 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 347 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 348 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 349 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 350 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 351 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 352 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 353 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 354 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 355 #endif /* CONFIG_UEC_ETH3 */ 356 357 #define CONFIG_UEC_ETH4 /* GETH4 */ 358 #define CONFIG_HAS_ETH3 359 360 #ifdef CONFIG_UEC_ETH4 361 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 362 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 363 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 364 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 365 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 366 #define CONFIG_SYS_UEC4_PHY_ADDR 3 367 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 368 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 369 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 370 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 371 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 372 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 373 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 374 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 375 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 376 #endif /* CONFIG_UEC_ETH4 */ 377 378 #undef CONFIG_UEC_ETH6 /* GETH6 */ 379 #define CONFIG_HAS_ETH5 380 381 #ifdef CONFIG_UEC_ETH6 382 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 383 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 384 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 385 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 386 #define CONFIG_SYS_UEC6_PHY_ADDR 4 387 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 388 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 389 #endif /* CONFIG_UEC_ETH6 */ 390 391 #undef CONFIG_UEC_ETH8 /* GETH8 */ 392 #define CONFIG_HAS_ETH7 393 394 #ifdef CONFIG_UEC_ETH8 395 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 396 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 397 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 398 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 399 #define CONFIG_SYS_UEC8_PHY_ADDR 6 400 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 401 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 402 #endif /* CONFIG_UEC_ETH8 */ 403 404 #endif /* CONFIG_QE */ 405 406 #if defined(CONFIG_PCI) 407 #undef CONFIG_EEPRO100 408 #undef CONFIG_TULIP 409 410 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 411 412 #endif /* CONFIG_PCI */ 413 414 /* 415 * Environment 416 */ 417 #if defined(CONFIG_SYS_RAMBOOT) 418 #else 419 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 420 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 421 #define CONFIG_ENV_SIZE 0x2000 422 #endif 423 424 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 425 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 426 427 /* QE microcode/firmware address */ 428 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 429 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 430 431 /* 432 * BOOTP options 433 */ 434 #define CONFIG_BOOTP_BOOTFILESIZE 435 436 #undef CONFIG_WATCHDOG /* watchdog disabled */ 437 438 #ifdef CONFIG_MMC 439 #define CONFIG_FSL_ESDHC_PIN_MUX 440 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 441 #endif 442 443 /* 444 * Miscellaneous configurable options 445 */ 446 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 447 #if defined(CONFIG_CMD_KGDB) 448 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 449 #else 450 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 451 #endif 452 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 453 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 454 /* Boot Argument Buffer Size */ 455 456 /* 457 * For booting Linux, the board info and command line data 458 * have to be in the first 64 MB of memory, since this is 459 * the maximum mapped by the Linux kernel during initialization. 460 */ 461 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 462 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 463 464 #if defined(CONFIG_CMD_KGDB) 465 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 466 #endif 467 468 /* 469 * Environment Configuration 470 */ 471 #define CONFIG_HOSTNAME "mpc8569mds" 472 #define CONFIG_ROOTPATH "/nfsroot" 473 #define CONFIG_BOOTFILE "your.uImage" 474 475 #define CONFIG_SERVERIP 192.168.1.1 476 #define CONFIG_GATEWAYIP 192.168.1.1 477 #define CONFIG_NETMASK 255.255.255.0 478 479 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 480 481 #define CONFIG_EXTRA_ENV_SETTINGS \ 482 "netdev=eth0\0" \ 483 "consoledev=ttyS0\0" \ 484 "ramdiskaddr=600000\0" \ 485 "ramdiskfile=your.ramdisk.u-boot\0" \ 486 "fdtaddr=400000\0" \ 487 "fdtfile=your.fdt.dtb\0" \ 488 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 489 "nfsroot=$serverip:$rootpath " \ 490 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 491 "console=$consoledev,$baudrate $othbootargs\0" \ 492 "ramargs=setenv bootargs root=/dev/ram rw " \ 493 "console=$consoledev,$baudrate $othbootargs\0" \ 494 495 #define CONFIG_NFSBOOTCOMMAND \ 496 "run nfsargs;" \ 497 "tftp $loadaddr $bootfile;" \ 498 "tftp $fdtaddr $fdtfile;" \ 499 "bootm $loadaddr - $fdtaddr" 500 501 #define CONFIG_RAMBOOTCOMMAND \ 502 "run ramargs;" \ 503 "tftp $ramdiskaddr $ramdiskfile;" \ 504 "tftp $loadaddr $bootfile;" \ 505 "bootm $loadaddr $ramdiskaddr" 506 507 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 508 509 #endif /* __CONFIG_H */ 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