1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8569mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_BOOKE 1 /* BOOKE */ 15 #define CONFIG_E500 1 /* BOOKE e500 family */ 16 #define CONFIG_MPC8569 1 /* MPC8569 specific */ 17 #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ 18 19 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ 20 21 #define CONFIG_SYS_SRIO 22 #define CONFIG_SRIO1 /* SRIO port 1 */ 23 24 #define CONFIG_PCI 1 /* Disable PCI/PCIE */ 25 #define CONFIG_PCIE1 1 /* PCIE controller */ 26 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 27 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 28 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 30 #define CONFIG_QE /* Enable QE */ 31 #define CONFIG_ENV_OVERWRITE 32 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 33 34 #ifndef __ASSEMBLY__ 35 extern unsigned long get_clock_freq(void); 36 #endif 37 /* Replace a call to get_clock_freq (after it is implemented)*/ 38 #define CONFIG_SYS_CLK_FREQ 66666666 39 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 40 41 #ifdef CONFIG_ATM 42 #define CONFIG_PQ_MDS_PIB 43 #define CONFIG_PQ_MDS_PIB_ATM 44 #endif 45 46 /* 47 * These can be toggled for performance analysis, otherwise use default. 48 */ 49 #define CONFIG_L2_CACHE /* toggle L2 cache */ 50 #define CONFIG_BTB /* toggle branch predition */ 51 52 #ifndef CONFIG_SYS_TEXT_BASE 53 #define CONFIG_SYS_TEXT_BASE 0xfff80000 54 #endif 55 56 #ifndef CONFIG_SYS_MONITOR_BASE 57 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 58 #endif 59 60 /* 61 * Only possible on E500 Version 2 or newer cores. 62 */ 63 #define CONFIG_ENABLE_36BIT_PHYS 1 64 65 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 66 #define CONFIG_BOARD_EARLY_INIT_R 1 67 #define CONFIG_HWCONFIG 68 69 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 70 #define CONFIG_SYS_MEMTEST_END 0x00400000 71 72 /* 73 * Config the L2 Cache as L2 SRAM 74 */ 75 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 76 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 77 #define CONFIG_SYS_L2_SIZE (512 << 10) 78 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 79 80 #define CONFIG_SYS_CCSRBAR 0xe0000000 81 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 82 83 #if defined(CONFIG_NAND_SPL) 84 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 85 #endif 86 87 /* DDR Setup */ 88 #define CONFIG_SYS_FSL_DDR3 89 #undef CONFIG_FSL_DDR_INTERACTIVE 90 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 91 #define CONFIG_DDR_SPD 92 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 93 94 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 95 96 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 97 /* DDR is system memory*/ 98 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 99 100 #define CONFIG_NUM_DDR_CONTROLLERS 1 101 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 102 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 103 104 /* I2C addresses of SPD EEPROMs */ 105 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 106 107 /* These are used when DDR doesn't use SPD. */ 108 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 109 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 110 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 111 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 112 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 113 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 114 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 115 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 116 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 117 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 118 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 119 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 120 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 121 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 122 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 123 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 124 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 125 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 126 #define CONFIG_SYS_DDR_CDR_1 0x80040000 127 #define CONFIG_SYS_DDR_CDR_2 0x00000000 128 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 129 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 130 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 131 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 132 133 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 134 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 135 #define CONFIG_SYS_DDR_SBE 0x00010000 136 137 #undef CONFIG_CLOCKS_IN_MHZ 138 139 /* 140 * Local Bus Definitions 141 */ 142 143 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 144 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 145 146 #define CONFIG_SYS_BCSR_BASE 0xf8000000 147 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 148 149 /*Chip select 0 - Flash*/ 150 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 151 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 152 153 /*Chip select 1 - BCSR*/ 154 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 155 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 156 157 /*Chip select 4 - PIB*/ 158 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 159 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 160 161 /*Chip select 5 - PIB*/ 162 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 163 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 164 165 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 166 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 167 #undef CONFIG_SYS_FLASH_CHECKSUM 168 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 169 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 170 171 #undef CONFIG_SYS_RAMBOOT 172 173 #define CONFIG_FLASH_CFI_DRIVER 174 #define CONFIG_SYS_FLASH_CFI 175 #define CONFIG_SYS_FLASH_EMPTY_INFO 176 177 /* Chip select 3 - NAND */ 178 #ifndef CONFIG_NAND_SPL 179 #define CONFIG_SYS_NAND_BASE 0xFC000000 180 #else 181 #define CONFIG_SYS_NAND_BASE 0xFFF00000 182 #endif 183 184 /* NAND boot: 4K NAND loader config */ 185 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 186 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 187 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 188 #define CONFIG_SYS_NAND_U_BOOT_START \ 189 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 190 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 191 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 192 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 193 194 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 195 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 196 #define CONFIG_SYS_MAX_NAND_DEVICE 1 197 #define CONFIG_CMD_NAND 1 198 #define CONFIG_NAND_FSL_ELBC 1 199 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 200 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 201 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 202 | BR_PS_8 /* Port Size = 8 bit */ \ 203 | BR_MS_FCM /* MSEL = FCM */ \ 204 | BR_V) /* valid */ 205 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 206 | OR_FCM_CSCT \ 207 | OR_FCM_CST \ 208 | OR_FCM_CHT \ 209 | OR_FCM_SCY_1 \ 210 | OR_FCM_TRLX \ 211 | OR_FCM_EHTR) 212 213 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 214 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 215 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 216 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 217 218 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 219 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 220 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 221 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 222 223 #define CONFIG_SYS_INIT_RAM_LOCK 1 224 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 225 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 226 227 #define CONFIG_SYS_GBL_DATA_OFFSET \ 228 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 229 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 230 231 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 232 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 233 234 /* Serial Port */ 235 #define CONFIG_CONS_INDEX 1 236 #define CONFIG_SYS_NS16550_SERIAL 237 #define CONFIG_SYS_NS16550_REG_SIZE 1 238 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 239 #ifdef CONFIG_NAND_SPL 240 #define CONFIG_NS16550_MIN_FUNCTIONS 241 #endif 242 243 #define CONFIG_SYS_BAUDRATE_TABLE \ 244 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 245 246 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 247 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 248 249 /* 250 * I2C 251 */ 252 #define CONFIG_SYS_I2C 253 #define CONFIG_SYS_I2C_FSL 254 #define CONFIG_SYS_FSL_I2C_SPEED 400000 255 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 256 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 257 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 258 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 259 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 260 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 261 262 /* 263 * I2C2 EEPROM 264 */ 265 #define CONFIG_ID_EEPROM 266 #ifdef CONFIG_ID_EEPROM 267 #define CONFIG_SYS_I2C_EEPROM_NXID 268 #endif 269 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 270 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 271 #define CONFIG_SYS_EEPROM_BUS_NUM 1 272 273 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 274 #define PLPPAR1_I2C2_VAL 0x00000000 275 #define PLPPAR1_ESDHC_VAL 0x0000000A 276 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 277 #define PLPDIR1_I2C2_VAL 0x0000000F 278 #define PLPDIR1_ESDHC_VAL 0x00000006 279 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 280 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 281 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 282 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 283 284 /* 285 * General PCI 286 * Memory Addresses are mapped 1-1. I/O is mapped from 0 287 */ 288 #define CONFIG_SYS_PCIE1_NAME "Slot" 289 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 290 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 291 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 292 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 293 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 294 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 295 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 296 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 297 298 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 299 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 300 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 301 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 302 303 #ifdef CONFIG_QE 304 /* 305 * QE UEC ethernet configuration 306 */ 307 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 308 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 309 310 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 311 #define CONFIG_UEC_ETH 312 #define CONFIG_ETHPRIME "UEC0" 313 #define CONFIG_PHY_MODE_NEED_CHANGE 314 315 #define CONFIG_UEC_ETH1 /* GETH1 */ 316 #define CONFIG_HAS_ETH0 317 318 #ifdef CONFIG_UEC_ETH1 319 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 320 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 321 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 322 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 323 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 324 #define CONFIG_SYS_UEC1_PHY_ADDR 7 325 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 326 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 327 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 328 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 329 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 330 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 331 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 332 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 333 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 334 #endif /* CONFIG_UEC_ETH1 */ 335 336 #define CONFIG_UEC_ETH2 /* GETH2 */ 337 #define CONFIG_HAS_ETH1 338 339 #ifdef CONFIG_UEC_ETH2 340 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 341 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 342 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 343 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 344 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 345 #define CONFIG_SYS_UEC2_PHY_ADDR 1 346 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 347 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 348 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 349 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 350 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 351 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 352 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 353 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 354 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 355 #endif /* CONFIG_UEC_ETH2 */ 356 357 #define CONFIG_UEC_ETH3 /* GETH3 */ 358 #define CONFIG_HAS_ETH2 359 360 #ifdef CONFIG_UEC_ETH3 361 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 362 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 363 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 364 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 365 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 366 #define CONFIG_SYS_UEC3_PHY_ADDR 2 367 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 368 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 369 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 370 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 371 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 372 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 373 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 374 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 375 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 376 #endif /* CONFIG_UEC_ETH3 */ 377 378 #define CONFIG_UEC_ETH4 /* GETH4 */ 379 #define CONFIG_HAS_ETH3 380 381 #ifdef CONFIG_UEC_ETH4 382 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 383 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 384 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 385 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 386 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 387 #define CONFIG_SYS_UEC4_PHY_ADDR 3 388 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 389 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 390 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 391 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 392 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 393 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 394 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 395 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 396 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 397 #endif /* CONFIG_UEC_ETH4 */ 398 399 #undef CONFIG_UEC_ETH6 /* GETH6 */ 400 #define CONFIG_HAS_ETH5 401 402 #ifdef CONFIG_UEC_ETH6 403 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 404 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 405 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 406 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 407 #define CONFIG_SYS_UEC6_PHY_ADDR 4 408 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 409 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 410 #endif /* CONFIG_UEC_ETH6 */ 411 412 #undef CONFIG_UEC_ETH8 /* GETH8 */ 413 #define CONFIG_HAS_ETH7 414 415 #ifdef CONFIG_UEC_ETH8 416 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 417 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 418 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 419 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 420 #define CONFIG_SYS_UEC8_PHY_ADDR 6 421 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 422 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 423 #endif /* CONFIG_UEC_ETH8 */ 424 425 #endif /* CONFIG_QE */ 426 427 #if defined(CONFIG_PCI) 428 429 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 430 431 #undef CONFIG_EEPRO100 432 #undef CONFIG_TULIP 433 434 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 435 436 #endif /* CONFIG_PCI */ 437 438 /* 439 * Environment 440 */ 441 #if defined(CONFIG_SYS_RAMBOOT) 442 #else 443 #define CONFIG_ENV_IS_IN_FLASH 1 444 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 445 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 446 #define CONFIG_ENV_SIZE 0x2000 447 #endif 448 449 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 450 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 451 452 /* QE microcode/firmware address */ 453 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 454 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 455 456 /* 457 * BOOTP options 458 */ 459 #define CONFIG_BOOTP_BOOTFILESIZE 460 #define CONFIG_BOOTP_BOOTPATH 461 #define CONFIG_BOOTP_GATEWAY 462 #define CONFIG_BOOTP_HOSTNAME 463 464 /* 465 * Command line configuration. 466 */ 467 #define CONFIG_CMD_IRQ 468 #define CONFIG_CMD_REGINFO 469 470 #if defined(CONFIG_PCI) 471 #define CONFIG_CMD_PCI 472 #endif 473 474 #undef CONFIG_WATCHDOG /* watchdog disabled */ 475 476 #define CONFIG_MMC 1 477 478 #ifdef CONFIG_MMC 479 #define CONFIG_FSL_ESDHC 480 #define CONFIG_FSL_ESDHC_PIN_MUX 481 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 482 #define CONFIG_GENERIC_MMC 483 #define CONFIG_DOS_PARTITION 484 #endif 485 486 /* 487 * Miscellaneous configurable options 488 */ 489 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 490 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 491 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 492 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 493 #if defined(CONFIG_CMD_KGDB) 494 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 495 #else 496 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 497 #endif 498 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 499 /* Print Buffer Size */ 500 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 501 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 502 /* Boot Argument Buffer Size */ 503 504 /* 505 * For booting Linux, the board info and command line data 506 * have to be in the first 64 MB of memory, since this is 507 * the maximum mapped by the Linux kernel during initialization. 508 */ 509 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 510 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 511 512 #if defined(CONFIG_CMD_KGDB) 513 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 514 #endif 515 516 /* 517 * Environment Configuration 518 */ 519 #define CONFIG_HOSTNAME mpc8569mds 520 #define CONFIG_ROOTPATH "/nfsroot" 521 #define CONFIG_BOOTFILE "your.uImage" 522 523 #define CONFIG_SERVERIP 192.168.1.1 524 #define CONFIG_GATEWAYIP 192.168.1.1 525 #define CONFIG_NETMASK 255.255.255.0 526 527 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 528 529 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 530 531 #define CONFIG_BAUDRATE 115200 532 533 #define CONFIG_EXTRA_ENV_SETTINGS \ 534 "netdev=eth0\0" \ 535 "consoledev=ttyS0\0" \ 536 "ramdiskaddr=600000\0" \ 537 "ramdiskfile=your.ramdisk.u-boot\0" \ 538 "fdtaddr=400000\0" \ 539 "fdtfile=your.fdt.dtb\0" \ 540 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 541 "nfsroot=$serverip:$rootpath " \ 542 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 543 "console=$consoledev,$baudrate $othbootargs\0" \ 544 "ramargs=setenv bootargs root=/dev/ram rw " \ 545 "console=$consoledev,$baudrate $othbootargs\0" \ 546 547 #define CONFIG_NFSBOOTCOMMAND \ 548 "run nfsargs;" \ 549 "tftp $loadaddr $bootfile;" \ 550 "tftp $fdtaddr $fdtfile;" \ 551 "bootm $loadaddr - $fdtaddr" 552 553 #define CONFIG_RAMBOOTCOMMAND \ 554 "run ramargs;" \ 555 "tftp $ramdiskaddr $ramdiskfile;" \ 556 "tftp $loadaddr $bootfile;" \ 557 "bootm $loadaddr $ramdiskaddr" 558 559 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 560 561 #endif /* __CONFIG_H */ 562