1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8569mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_BOOKE 1 /* BOOKE */ 15 #define CONFIG_E500 1 /* BOOKE e500 family */ 16 #define CONFIG_MPC8569 1 /* MPC8569 specific */ 17 #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ 18 19 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ 20 21 #define CONFIG_SYS_SRIO 22 #define CONFIG_SRIO1 /* SRIO port 1 */ 23 24 #define CONFIG_PCI 1 /* Disable PCI/PCIE */ 25 #define CONFIG_PCIE1 1 /* PCIE controller */ 26 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 27 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 28 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 30 #define CONFIG_QE /* Enable QE */ 31 #define CONFIG_ENV_OVERWRITE 32 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 33 34 #ifndef __ASSEMBLY__ 35 extern unsigned long get_clock_freq(void); 36 #endif 37 /* Replace a call to get_clock_freq (after it is implemented)*/ 38 #define CONFIG_SYS_CLK_FREQ 66666666 39 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 40 41 #ifdef CONFIG_ATM 42 #define CONFIG_PQ_MDS_PIB 43 #define CONFIG_PQ_MDS_PIB_ATM 44 #endif 45 46 /* 47 * These can be toggled for performance analysis, otherwise use default. 48 */ 49 #define CONFIG_L2_CACHE /* toggle L2 cache */ 50 #define CONFIG_BTB /* toggle branch predition */ 51 52 #ifdef CONFIG_NAND 53 #define CONFIG_NAND_U_BOOT 1 54 #define CONFIG_RAMBOOT_NAND 1 55 #ifdef CONFIG_NAND_SPL 56 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 57 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 58 #else 59 #define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds 60 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 61 #endif 62 #endif 63 64 #ifndef CONFIG_SYS_TEXT_BASE 65 #define CONFIG_SYS_TEXT_BASE 0xfff80000 66 #endif 67 68 #ifndef CONFIG_SYS_MONITOR_BASE 69 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 70 #endif 71 72 /* 73 * Only possible on E500 Version 2 or newer cores. 74 */ 75 #define CONFIG_ENABLE_36BIT_PHYS 1 76 77 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 78 #define CONFIG_BOARD_EARLY_INIT_R 1 79 #define CONFIG_HWCONFIG 80 81 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 82 #define CONFIG_SYS_MEMTEST_END 0x00400000 83 84 /* 85 * Config the L2 Cache as L2 SRAM 86 */ 87 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 88 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 89 #define CONFIG_SYS_L2_SIZE (512 << 10) 90 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 91 92 #define CONFIG_SYS_CCSRBAR 0xe0000000 93 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 94 95 #if defined(CONFIG_NAND_SPL) 96 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 97 #endif 98 99 /* DDR Setup */ 100 #define CONFIG_SYS_FSL_DDR3 101 #undef CONFIG_FSL_DDR_INTERACTIVE 102 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 103 #define CONFIG_DDR_SPD 104 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 105 106 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 107 108 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 109 /* DDR is system memory*/ 110 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 111 112 #define CONFIG_NUM_DDR_CONTROLLERS 1 113 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 114 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 115 116 /* I2C addresses of SPD EEPROMs */ 117 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 118 119 /* These are used when DDR doesn't use SPD. */ 120 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 121 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 122 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 123 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 124 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 125 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 126 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 127 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 128 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 129 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 130 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 131 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 132 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 133 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 134 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 135 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 136 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 137 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 138 #define CONFIG_SYS_DDR_CDR_1 0x80040000 139 #define CONFIG_SYS_DDR_CDR_2 0x00000000 140 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 141 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 142 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 143 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 144 145 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 146 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 147 #define CONFIG_SYS_DDR_SBE 0x00010000 148 149 #undef CONFIG_CLOCKS_IN_MHZ 150 151 /* 152 * Local Bus Definitions 153 */ 154 155 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 156 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 157 158 #define CONFIG_SYS_BCSR_BASE 0xf8000000 159 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 160 161 /*Chip select 0 - Flash*/ 162 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 163 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 164 165 /*Chip select 1 - BCSR*/ 166 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 167 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 168 169 /*Chip select 4 - PIB*/ 170 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 171 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 172 173 /*Chip select 5 - PIB*/ 174 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 175 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 176 177 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 178 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 179 #undef CONFIG_SYS_FLASH_CHECKSUM 180 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 181 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 182 183 #if defined(CONFIG_RAMBOOT_NAND) 184 #define CONFIG_SYS_RAMBOOT 185 #define CONFIG_SYS_EXTRA_ENV_RELOC 186 #else 187 #undef CONFIG_SYS_RAMBOOT 188 #endif 189 190 #define CONFIG_FLASH_CFI_DRIVER 191 #define CONFIG_SYS_FLASH_CFI 192 #define CONFIG_SYS_FLASH_EMPTY_INFO 193 194 /* Chip select 3 - NAND */ 195 #ifndef CONFIG_NAND_SPL 196 #define CONFIG_SYS_NAND_BASE 0xFC000000 197 #else 198 #define CONFIG_SYS_NAND_BASE 0xFFF00000 199 #endif 200 201 /* NAND boot: 4K NAND loader config */ 202 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 203 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 204 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 205 #define CONFIG_SYS_NAND_U_BOOT_START \ 206 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 207 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 208 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 209 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 210 211 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 212 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 213 #define CONFIG_SYS_MAX_NAND_DEVICE 1 214 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 215 #define CONFIG_CMD_NAND 1 216 #define CONFIG_NAND_FSL_ELBC 1 217 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 218 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 219 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 220 | BR_PS_8 /* Port Size = 8 bit */ \ 221 | BR_MS_FCM /* MSEL = FCM */ \ 222 | BR_V) /* valid */ 223 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 224 | OR_FCM_CSCT \ 225 | OR_FCM_CST \ 226 | OR_FCM_CHT \ 227 | OR_FCM_SCY_1 \ 228 | OR_FCM_TRLX \ 229 | OR_FCM_EHTR) 230 231 #ifdef CONFIG_RAMBOOT_NAND 232 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 233 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */ 234 #define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 235 #define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 236 #else 237 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 238 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 239 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 240 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 241 #endif 242 243 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 244 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 245 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 246 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 247 248 #define CONFIG_SYS_INIT_RAM_LOCK 1 249 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 250 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 251 252 #define CONFIG_SYS_GBL_DATA_OFFSET \ 253 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 254 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 255 256 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 257 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 258 259 /* Serial Port */ 260 #define CONFIG_CONS_INDEX 1 261 #define CONFIG_SYS_NS16550 262 #define CONFIG_SYS_NS16550_SERIAL 263 #define CONFIG_SYS_NS16550_REG_SIZE 1 264 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 265 #ifdef CONFIG_NAND_SPL 266 #define CONFIG_NS16550_MIN_FUNCTIONS 267 #endif 268 269 #define CONFIG_SYS_BAUDRATE_TABLE \ 270 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 271 272 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 273 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 274 275 /* Use the HUSH parser*/ 276 #define CONFIG_SYS_HUSH_PARSER 277 #ifdef CONFIG_SYS_HUSH_PARSER 278 #endif 279 280 /* pass open firmware flat tree */ 281 #define CONFIG_OF_LIBFDT 1 282 #define CONFIG_OF_BOARD_SETUP 1 283 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 284 285 /* 286 * I2C 287 */ 288 #define CONFIG_SYS_I2C 289 #define CONFIG_SYS_I2C_FSL 290 #define CONFIG_SYS_FSL_I2C_SPEED 400000 291 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 292 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 293 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 294 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 295 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 296 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 297 298 /* 299 * I2C2 EEPROM 300 */ 301 #define CONFIG_ID_EEPROM 302 #ifdef CONFIG_ID_EEPROM 303 #define CONFIG_SYS_I2C_EEPROM_NXID 304 #endif 305 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 306 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 307 #define CONFIG_SYS_EEPROM_BUS_NUM 1 308 309 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 310 #define PLPPAR1_I2C2_VAL 0x00000000 311 #define PLPPAR1_ESDHC_VAL 0x0000000A 312 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 313 #define PLPDIR1_I2C2_VAL 0x0000000F 314 #define PLPDIR1_ESDHC_VAL 0x00000006 315 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 316 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 317 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 318 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 319 320 /* 321 * General PCI 322 * Memory Addresses are mapped 1-1. I/O is mapped from 0 323 */ 324 #define CONFIG_SYS_PCIE1_NAME "Slot" 325 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 326 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 327 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 328 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 329 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 330 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 331 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 332 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 333 334 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 335 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 336 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 337 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 338 339 #ifdef CONFIG_QE 340 /* 341 * QE UEC ethernet configuration 342 */ 343 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 344 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 345 346 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 347 #define CONFIG_UEC_ETH 348 #define CONFIG_ETHPRIME "UEC0" 349 #define CONFIG_PHY_MODE_NEED_CHANGE 350 351 #define CONFIG_UEC_ETH1 /* GETH1 */ 352 #define CONFIG_HAS_ETH0 353 354 #ifdef CONFIG_UEC_ETH1 355 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 356 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 357 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 358 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 359 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 360 #define CONFIG_SYS_UEC1_PHY_ADDR 7 361 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 362 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 363 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 364 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 365 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 366 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 367 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 368 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 369 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 370 #endif /* CONFIG_UEC_ETH1 */ 371 372 #define CONFIG_UEC_ETH2 /* GETH2 */ 373 #define CONFIG_HAS_ETH1 374 375 #ifdef CONFIG_UEC_ETH2 376 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 377 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 378 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 379 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 380 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 381 #define CONFIG_SYS_UEC2_PHY_ADDR 1 382 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 383 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 384 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 385 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 386 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 387 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 388 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 389 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 390 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 391 #endif /* CONFIG_UEC_ETH2 */ 392 393 #define CONFIG_UEC_ETH3 /* GETH3 */ 394 #define CONFIG_HAS_ETH2 395 396 #ifdef CONFIG_UEC_ETH3 397 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 398 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 399 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 400 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 401 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 402 #define CONFIG_SYS_UEC3_PHY_ADDR 2 403 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 404 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 405 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 406 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 407 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 408 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 409 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 410 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 411 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 412 #endif /* CONFIG_UEC_ETH3 */ 413 414 #define CONFIG_UEC_ETH4 /* GETH4 */ 415 #define CONFIG_HAS_ETH3 416 417 #ifdef CONFIG_UEC_ETH4 418 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 419 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 420 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 421 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 422 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 423 #define CONFIG_SYS_UEC4_PHY_ADDR 3 424 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 425 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 426 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 427 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 428 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 429 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 430 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 431 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 432 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 433 #endif /* CONFIG_UEC_ETH4 */ 434 435 #undef CONFIG_UEC_ETH6 /* GETH6 */ 436 #define CONFIG_HAS_ETH5 437 438 #ifdef CONFIG_UEC_ETH6 439 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 440 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 441 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 442 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 443 #define CONFIG_SYS_UEC6_PHY_ADDR 4 444 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 445 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 446 #endif /* CONFIG_UEC_ETH6 */ 447 448 #undef CONFIG_UEC_ETH8 /* GETH8 */ 449 #define CONFIG_HAS_ETH7 450 451 #ifdef CONFIG_UEC_ETH8 452 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 453 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 454 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 455 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 456 #define CONFIG_SYS_UEC8_PHY_ADDR 6 457 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 458 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 459 #endif /* CONFIG_UEC_ETH8 */ 460 461 #endif /* CONFIG_QE */ 462 463 #if defined(CONFIG_PCI) 464 465 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 466 467 #undef CONFIG_EEPRO100 468 #undef CONFIG_TULIP 469 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 470 471 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 472 473 #endif /* CONFIG_PCI */ 474 475 /* 476 * Environment 477 */ 478 #if defined(CONFIG_SYS_RAMBOOT) 479 #if defined(CONFIG_RAMBOOT_NAND) 480 #define CONFIG_ENV_IS_IN_NAND 1 481 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 482 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 483 #endif 484 #else 485 #define CONFIG_ENV_IS_IN_FLASH 1 486 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 487 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 488 #define CONFIG_ENV_SIZE 0x2000 489 #endif 490 491 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 492 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 493 494 /* QE microcode/firmware address */ 495 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 496 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000 497 498 /* 499 * BOOTP options 500 */ 501 #define CONFIG_BOOTP_BOOTFILESIZE 502 #define CONFIG_BOOTP_BOOTPATH 503 #define CONFIG_BOOTP_GATEWAY 504 #define CONFIG_BOOTP_HOSTNAME 505 506 507 /* 508 * Command line configuration. 509 */ 510 #include <config_cmd_default.h> 511 512 #define CONFIG_CMD_PING 513 #define CONFIG_CMD_I2C 514 #define CONFIG_CMD_MII 515 #define CONFIG_CMD_ELF 516 #define CONFIG_CMD_IRQ 517 #define CONFIG_CMD_SETEXPR 518 #define CONFIG_CMD_REGINFO 519 520 #if defined(CONFIG_PCI) 521 #define CONFIG_CMD_PCI 522 #endif 523 524 525 #undef CONFIG_WATCHDOG /* watchdog disabled */ 526 527 #define CONFIG_MMC 1 528 529 #ifdef CONFIG_MMC 530 #define CONFIG_FSL_ESDHC 531 #define CONFIG_FSL_ESDHC_PIN_MUX 532 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 533 #define CONFIG_CMD_MMC 534 #define CONFIG_GENERIC_MMC 535 #define CONFIG_CMD_EXT2 536 #define CONFIG_CMD_FAT 537 #define CONFIG_DOS_PARTITION 538 #endif 539 540 /* 541 * Miscellaneous configurable options 542 */ 543 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 544 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 545 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 546 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 547 #if defined(CONFIG_CMD_KGDB) 548 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 549 #else 550 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 551 #endif 552 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 553 /* Print Buffer Size */ 554 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 555 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 556 /* Boot Argument Buffer Size */ 557 558 /* 559 * For booting Linux, the board info and command line data 560 * have to be in the first 64 MB of memory, since this is 561 * the maximum mapped by the Linux kernel during initialization. 562 */ 563 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 564 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 565 566 #if defined(CONFIG_CMD_KGDB) 567 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 568 #endif 569 570 /* 571 * Environment Configuration 572 */ 573 #define CONFIG_HOSTNAME mpc8569mds 574 #define CONFIG_ROOTPATH "/nfsroot" 575 #define CONFIG_BOOTFILE "your.uImage" 576 577 #define CONFIG_SERVERIP 192.168.1.1 578 #define CONFIG_GATEWAYIP 192.168.1.1 579 #define CONFIG_NETMASK 255.255.255.0 580 581 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 582 583 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 584 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 585 586 #define CONFIG_BAUDRATE 115200 587 588 #define CONFIG_EXTRA_ENV_SETTINGS \ 589 "netdev=eth0\0" \ 590 "consoledev=ttyS0\0" \ 591 "ramdiskaddr=600000\0" \ 592 "ramdiskfile=your.ramdisk.u-boot\0" \ 593 "fdtaddr=400000\0" \ 594 "fdtfile=your.fdt.dtb\0" \ 595 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 596 "nfsroot=$serverip:$rootpath " \ 597 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 598 "console=$consoledev,$baudrate $othbootargs\0" \ 599 "ramargs=setenv bootargs root=/dev/ram rw " \ 600 "console=$consoledev,$baudrate $othbootargs\0" \ 601 602 #define CONFIG_NFSBOOTCOMMAND \ 603 "run nfsargs;" \ 604 "tftp $loadaddr $bootfile;" \ 605 "tftp $fdtaddr $fdtfile;" \ 606 "bootm $loadaddr - $fdtaddr" 607 608 #define CONFIG_RAMBOOTCOMMAND \ 609 "run ramargs;" \ 610 "tftp $ramdiskaddr $ramdiskfile;" \ 611 "tftp $loadaddr $bootfile;" \ 612 "bootm $loadaddr $ramdiskaddr" 613 614 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 615 616 #endif /* __CONFIG_H */ 617