1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8569mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_BOOKE 1 /* BOOKE */ 15 #define CONFIG_E500 1 /* BOOKE e500 family */ 16 17 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ 18 19 #define CONFIG_SYS_SRIO 20 #define CONFIG_SRIO1 /* SRIO port 1 */ 21 22 #define CONFIG_PCIE1 1 /* PCIE controller */ 23 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 24 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 25 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 26 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 27 #define CONFIG_QE /* Enable QE */ 28 #define CONFIG_ENV_OVERWRITE 29 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 30 31 #ifndef __ASSEMBLY__ 32 extern unsigned long get_clock_freq(void); 33 #endif 34 /* Replace a call to get_clock_freq (after it is implemented)*/ 35 #define CONFIG_SYS_CLK_FREQ 66666666 36 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 37 38 #ifdef CONFIG_ATM 39 #define CONFIG_PQ_MDS_PIB 40 #define CONFIG_PQ_MDS_PIB_ATM 41 #endif 42 43 /* 44 * These can be toggled for performance analysis, otherwise use default. 45 */ 46 #define CONFIG_L2_CACHE /* toggle L2 cache */ 47 #define CONFIG_BTB /* toggle branch predition */ 48 49 #ifndef CONFIG_SYS_TEXT_BASE 50 #define CONFIG_SYS_TEXT_BASE 0xfff80000 51 #endif 52 53 #ifndef CONFIG_SYS_MONITOR_BASE 54 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 55 #endif 56 57 /* 58 * Only possible on E500 Version 2 or newer cores. 59 */ 60 #define CONFIG_ENABLE_36BIT_PHYS 1 61 62 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 63 #define CONFIG_BOARD_EARLY_INIT_R 1 64 #define CONFIG_HWCONFIG 65 66 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 67 #define CONFIG_SYS_MEMTEST_END 0x00400000 68 69 /* 70 * Config the L2 Cache as L2 SRAM 71 */ 72 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 73 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 74 #define CONFIG_SYS_L2_SIZE (512 << 10) 75 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 76 77 #define CONFIG_SYS_CCSRBAR 0xe0000000 78 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 79 80 #if defined(CONFIG_NAND_SPL) 81 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 82 #endif 83 84 /* DDR Setup */ 85 #define CONFIG_SYS_FSL_DDR3 86 #undef CONFIG_FSL_DDR_INTERACTIVE 87 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 88 #define CONFIG_DDR_SPD 89 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 90 91 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 92 93 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 94 /* DDR is system memory*/ 95 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 96 97 #define CONFIG_NUM_DDR_CONTROLLERS 1 98 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 99 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 100 101 /* I2C addresses of SPD EEPROMs */ 102 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 103 104 /* These are used when DDR doesn't use SPD. */ 105 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 106 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 107 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 108 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 109 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 110 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 111 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 112 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 113 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 114 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 115 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 116 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 117 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 118 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 119 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 120 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 121 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 122 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 123 #define CONFIG_SYS_DDR_CDR_1 0x80040000 124 #define CONFIG_SYS_DDR_CDR_2 0x00000000 125 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 126 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 127 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 128 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 129 130 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 131 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 132 #define CONFIG_SYS_DDR_SBE 0x00010000 133 134 #undef CONFIG_CLOCKS_IN_MHZ 135 136 /* 137 * Local Bus Definitions 138 */ 139 140 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 141 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 142 143 #define CONFIG_SYS_BCSR_BASE 0xf8000000 144 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 145 146 /*Chip select 0 - Flash*/ 147 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 148 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 149 150 /*Chip select 1 - BCSR*/ 151 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 152 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 153 154 /*Chip select 4 - PIB*/ 155 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 156 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 157 158 /*Chip select 5 - PIB*/ 159 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 160 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 161 162 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 163 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 164 #undef CONFIG_SYS_FLASH_CHECKSUM 165 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 166 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 167 168 #undef CONFIG_SYS_RAMBOOT 169 170 #define CONFIG_FLASH_CFI_DRIVER 171 #define CONFIG_SYS_FLASH_CFI 172 #define CONFIG_SYS_FLASH_EMPTY_INFO 173 174 /* Chip select 3 - NAND */ 175 #ifndef CONFIG_NAND_SPL 176 #define CONFIG_SYS_NAND_BASE 0xFC000000 177 #else 178 #define CONFIG_SYS_NAND_BASE 0xFFF00000 179 #endif 180 181 /* NAND boot: 4K NAND loader config */ 182 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 183 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 184 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 185 #define CONFIG_SYS_NAND_U_BOOT_START \ 186 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 187 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 188 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 189 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 190 191 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 192 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 193 #define CONFIG_SYS_MAX_NAND_DEVICE 1 194 #define CONFIG_CMD_NAND 1 195 #define CONFIG_NAND_FSL_ELBC 1 196 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 197 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 198 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 199 | BR_PS_8 /* Port Size = 8 bit */ \ 200 | BR_MS_FCM /* MSEL = FCM */ \ 201 | BR_V) /* valid */ 202 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 203 | OR_FCM_CSCT \ 204 | OR_FCM_CST \ 205 | OR_FCM_CHT \ 206 | OR_FCM_SCY_1 \ 207 | OR_FCM_TRLX \ 208 | OR_FCM_EHTR) 209 210 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 211 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 212 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 213 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 214 215 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 216 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 217 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 218 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 219 220 #define CONFIG_SYS_INIT_RAM_LOCK 1 221 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 222 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 223 224 #define CONFIG_SYS_GBL_DATA_OFFSET \ 225 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 226 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 227 228 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 229 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 230 231 /* Serial Port */ 232 #define CONFIG_CONS_INDEX 1 233 #define CONFIG_SYS_NS16550_SERIAL 234 #define CONFIG_SYS_NS16550_REG_SIZE 1 235 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 236 #ifdef CONFIG_NAND_SPL 237 #define CONFIG_NS16550_MIN_FUNCTIONS 238 #endif 239 240 #define CONFIG_SYS_BAUDRATE_TABLE \ 241 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 242 243 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 244 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 245 246 /* 247 * I2C 248 */ 249 #define CONFIG_SYS_I2C 250 #define CONFIG_SYS_I2C_FSL 251 #define CONFIG_SYS_FSL_I2C_SPEED 400000 252 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 253 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 254 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 255 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 256 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 257 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 258 259 /* 260 * I2C2 EEPROM 261 */ 262 #define CONFIG_ID_EEPROM 263 #ifdef CONFIG_ID_EEPROM 264 #define CONFIG_SYS_I2C_EEPROM_NXID 265 #endif 266 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 267 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 268 #define CONFIG_SYS_EEPROM_BUS_NUM 1 269 270 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 271 #define PLPPAR1_I2C2_VAL 0x00000000 272 #define PLPPAR1_ESDHC_VAL 0x0000000A 273 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 274 #define PLPDIR1_I2C2_VAL 0x0000000F 275 #define PLPDIR1_ESDHC_VAL 0x00000006 276 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 277 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 278 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 279 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 280 281 /* 282 * General PCI 283 * Memory Addresses are mapped 1-1. I/O is mapped from 0 284 */ 285 #define CONFIG_SYS_PCIE1_NAME "Slot" 286 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 287 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 288 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 289 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 290 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 291 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 292 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 293 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 294 295 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 296 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 297 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 298 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 299 300 #ifdef CONFIG_QE 301 /* 302 * QE UEC ethernet configuration 303 */ 304 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 305 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 306 307 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 308 #define CONFIG_UEC_ETH 309 #define CONFIG_ETHPRIME "UEC0" 310 #define CONFIG_PHY_MODE_NEED_CHANGE 311 312 #define CONFIG_UEC_ETH1 /* GETH1 */ 313 #define CONFIG_HAS_ETH0 314 315 #ifdef CONFIG_UEC_ETH1 316 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 317 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 318 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 319 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 320 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 321 #define CONFIG_SYS_UEC1_PHY_ADDR 7 322 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 323 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 324 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 325 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 326 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 327 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 328 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 329 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 330 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 331 #endif /* CONFIG_UEC_ETH1 */ 332 333 #define CONFIG_UEC_ETH2 /* GETH2 */ 334 #define CONFIG_HAS_ETH1 335 336 #ifdef CONFIG_UEC_ETH2 337 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 338 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 339 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 340 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 341 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 342 #define CONFIG_SYS_UEC2_PHY_ADDR 1 343 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 344 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 345 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 346 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 347 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 348 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 349 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 350 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 351 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 352 #endif /* CONFIG_UEC_ETH2 */ 353 354 #define CONFIG_UEC_ETH3 /* GETH3 */ 355 #define CONFIG_HAS_ETH2 356 357 #ifdef CONFIG_UEC_ETH3 358 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 359 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 360 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 361 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 362 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 363 #define CONFIG_SYS_UEC3_PHY_ADDR 2 364 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 365 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 366 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 367 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 368 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 369 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 370 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 371 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 372 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 373 #endif /* CONFIG_UEC_ETH3 */ 374 375 #define CONFIG_UEC_ETH4 /* GETH4 */ 376 #define CONFIG_HAS_ETH3 377 378 #ifdef CONFIG_UEC_ETH4 379 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 380 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 381 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 382 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 383 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 384 #define CONFIG_SYS_UEC4_PHY_ADDR 3 385 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 386 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 387 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 388 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 389 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 390 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 391 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 392 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 393 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 394 #endif /* CONFIG_UEC_ETH4 */ 395 396 #undef CONFIG_UEC_ETH6 /* GETH6 */ 397 #define CONFIG_HAS_ETH5 398 399 #ifdef CONFIG_UEC_ETH6 400 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 401 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 402 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 403 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 404 #define CONFIG_SYS_UEC6_PHY_ADDR 4 405 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 406 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 407 #endif /* CONFIG_UEC_ETH6 */ 408 409 #undef CONFIG_UEC_ETH8 /* GETH8 */ 410 #define CONFIG_HAS_ETH7 411 412 #ifdef CONFIG_UEC_ETH8 413 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 414 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 415 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 416 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 417 #define CONFIG_SYS_UEC8_PHY_ADDR 6 418 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 419 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 420 #endif /* CONFIG_UEC_ETH8 */ 421 422 #endif /* CONFIG_QE */ 423 424 #if defined(CONFIG_PCI) 425 #undef CONFIG_EEPRO100 426 #undef CONFIG_TULIP 427 428 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 429 430 #endif /* CONFIG_PCI */ 431 432 /* 433 * Environment 434 */ 435 #if defined(CONFIG_SYS_RAMBOOT) 436 #else 437 #define CONFIG_ENV_IS_IN_FLASH 1 438 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 439 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 440 #define CONFIG_ENV_SIZE 0x2000 441 #endif 442 443 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 444 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 445 446 /* QE microcode/firmware address */ 447 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 448 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 449 450 /* 451 * BOOTP options 452 */ 453 #define CONFIG_BOOTP_BOOTFILESIZE 454 #define CONFIG_BOOTP_BOOTPATH 455 #define CONFIG_BOOTP_GATEWAY 456 #define CONFIG_BOOTP_HOSTNAME 457 458 /* 459 * Command line configuration. 460 */ 461 #define CONFIG_CMD_IRQ 462 #define CONFIG_CMD_REGINFO 463 464 #if defined(CONFIG_PCI) 465 #define CONFIG_CMD_PCI 466 #endif 467 468 #undef CONFIG_WATCHDOG /* watchdog disabled */ 469 470 #define CONFIG_MMC 1 471 472 #ifdef CONFIG_MMC 473 #define CONFIG_FSL_ESDHC 474 #define CONFIG_FSL_ESDHC_PIN_MUX 475 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 476 #define CONFIG_GENERIC_MMC 477 #define CONFIG_DOS_PARTITION 478 #endif 479 480 /* 481 * Miscellaneous configurable options 482 */ 483 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 484 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 485 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 486 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 487 #if defined(CONFIG_CMD_KGDB) 488 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 489 #else 490 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 491 #endif 492 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 493 /* Print Buffer Size */ 494 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 495 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 496 /* Boot Argument Buffer Size */ 497 498 /* 499 * For booting Linux, the board info and command line data 500 * have to be in the first 64 MB of memory, since this is 501 * the maximum mapped by the Linux kernel during initialization. 502 */ 503 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 504 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 505 506 #if defined(CONFIG_CMD_KGDB) 507 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 508 #endif 509 510 /* 511 * Environment Configuration 512 */ 513 #define CONFIG_HOSTNAME mpc8569mds 514 #define CONFIG_ROOTPATH "/nfsroot" 515 #define CONFIG_BOOTFILE "your.uImage" 516 517 #define CONFIG_SERVERIP 192.168.1.1 518 #define CONFIG_GATEWAYIP 192.168.1.1 519 #define CONFIG_NETMASK 255.255.255.0 520 521 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 522 523 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 524 525 #define CONFIG_BAUDRATE 115200 526 527 #define CONFIG_EXTRA_ENV_SETTINGS \ 528 "netdev=eth0\0" \ 529 "consoledev=ttyS0\0" \ 530 "ramdiskaddr=600000\0" \ 531 "ramdiskfile=your.ramdisk.u-boot\0" \ 532 "fdtaddr=400000\0" \ 533 "fdtfile=your.fdt.dtb\0" \ 534 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 535 "nfsroot=$serverip:$rootpath " \ 536 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 537 "console=$consoledev,$baudrate $othbootargs\0" \ 538 "ramargs=setenv bootargs root=/dev/ram rw " \ 539 "console=$consoledev,$baudrate $othbootargs\0" \ 540 541 #define CONFIG_NFSBOOTCOMMAND \ 542 "run nfsargs;" \ 543 "tftp $loadaddr $bootfile;" \ 544 "tftp $fdtaddr $fdtfile;" \ 545 "bootm $loadaddr - $fdtaddr" 546 547 #define CONFIG_RAMBOOTCOMMAND \ 548 "run ramargs;" \ 549 "tftp $ramdiskaddr $ramdiskfile;" \ 550 "tftp $loadaddr $bootfile;" \ 551 "bootm $loadaddr $ramdiskaddr" 552 553 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 554 555 #endif /* __CONFIG_H */ 556