1 /* 2 * Copyright (C) 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8569mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8569 1 /* MPC8569 specific */ 34 #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ 35 36 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ 37 38 #define CONFIG_PCI 1 /* Disable PCI/PCIE */ 39 #define CONFIG_PCIE1 1 /* PCIE controller */ 40 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 41 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 42 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 43 #define CONFIG_QE /* Enable QE */ 44 #define CONFIG_ENV_OVERWRITE 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #ifndef __ASSEMBLY__ 48 extern unsigned long get_clock_freq(void); 49 #endif 50 /* Replace a call to get_clock_freq (after it is implemented)*/ 51 #define CONFIG_SYS_CLK_FREQ 66666666 52 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 53 54 #ifdef CONFIG_MK_ATM 55 #define CONFIG_PQ_MDS_PIB 56 #define CONFIG_PQ_MDS_PIB_ATM 57 #endif 58 59 /* 60 * These can be toggled for performance analysis, otherwise use default. 61 */ 62 #define CONFIG_L2_CACHE /* toggle L2 cache */ 63 #define CONFIG_BTB /* toggle branch predition */ 64 65 #ifdef CONFIG_MK_NAND 66 #define CONFIG_NAND_U_BOOT 1 67 #define CONFIG_RAMBOOT_NAND 1 68 #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 69 #endif 70 71 /* 72 * Only possible on E500 Version 2 or newer cores. 73 */ 74 #define CONFIG_ENABLE_36BIT_PHYS 1 75 76 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 77 #define CONFIG_HWCONFIG 78 79 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 80 #define CONFIG_SYS_MEMTEST_END 0x00400000 81 82 /* 83 * Config the L2 Cache as L2 SRAM 84 */ 85 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 86 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 87 #define CONFIG_SYS_L2_SIZE (512 << 10) 88 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 89 90 /* 91 * Base addresses -- Note these are effective addresses where the 92 * actual resources get mapped (not physical addresses) 93 */ 94 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 95 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 96 /* physical addr of CCSRBAR */ 97 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 98 /* PQII uses CONFIG_SYS_IMMR */ 99 100 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) 101 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR 102 #else 103 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 104 #endif 105 106 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 107 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 108 109 /* DDR Setup */ 110 #define CONFIG_FSL_DDR3 111 #undef CONFIG_FSL_DDR_INTERACTIVE 112 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 113 #define CONFIG_DDR_SPD 114 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 115 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 116 117 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 118 119 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 120 /* DDR is system memory*/ 121 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 122 123 #define CONFIG_NUM_DDR_CONTROLLERS 1 124 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 125 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 126 127 /* I2C addresses of SPD EEPROMs */ 128 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 129 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 130 131 /* These are used when DDR doesn't use SPD. */ 132 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 133 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 134 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 135 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 136 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 137 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 138 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 139 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 140 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 141 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 142 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 143 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 144 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 145 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 146 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 147 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 148 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 149 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 150 #define CONFIG_SYS_DDR_CDR_1 0x80040000 151 #define CONFIG_SYS_DDR_CDR_2 0x00000000 152 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 153 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 154 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 155 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 156 157 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 158 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 159 #define CONFIG_SYS_DDR_SBE 0x00010000 160 161 #undef CONFIG_CLOCKS_IN_MHZ 162 163 /* 164 * Local Bus Definitions 165 */ 166 167 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 168 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 169 170 #define CONFIG_SYS_BCSR_BASE 0xf8000000 171 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 172 173 /*Chip select 0 - Flash*/ 174 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 175 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 176 177 /*Chip select 1 - BCSR*/ 178 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 179 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 180 181 /*Chip select 4 - PIB*/ 182 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 183 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 184 185 /*Chip select 5 - PIB*/ 186 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 187 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 188 189 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 190 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 191 #undef CONFIG_SYS_FLASH_CHECKSUM 192 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 193 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 194 195 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 196 197 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) 198 #define CONFIG_SYS_RAMBOOT 199 #else 200 #undef CONFIG_SYS_RAMBOOT 201 #endif 202 203 #define CONFIG_FLASH_CFI_DRIVER 204 #define CONFIG_SYS_FLASH_CFI 205 #define CONFIG_SYS_FLASH_EMPTY_INFO 206 207 /* Chip select 3 - NAND */ 208 #ifndef CONFIG_NAND_SPL 209 #define CONFIG_SYS_NAND_BASE 0xFC000000 210 #else 211 #define CONFIG_SYS_NAND_BASE 0xFFF00000 212 #endif 213 214 /* NAND boot: 4K NAND loader config */ 215 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 216 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 217 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 218 #define CONFIG_SYS_NAND_U_BOOT_START \ 219 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 220 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 221 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 222 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 223 224 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 225 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 226 #define CONFIG_SYS_MAX_NAND_DEVICE 1 227 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 228 #define CONFIG_CMD_NAND 1 229 #define CONFIG_NAND_FSL_ELBC 1 230 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 231 #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 232 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 233 | BR_PS_8 /* Port Size = 8 bit */ \ 234 | BR_MS_FCM /* MSEL = FCM */ \ 235 | BR_V) /* valid */ 236 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 237 | OR_FCM_CSCT \ 238 | OR_FCM_CST \ 239 | OR_FCM_CHT \ 240 | OR_FCM_SCY_1 \ 241 | OR_FCM_TRLX \ 242 | OR_FCM_EHTR) 243 244 #ifdef CONFIG_RAMBOOT_NAND 245 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 246 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 247 #define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 248 #define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 249 #else 250 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 251 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 252 #define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 253 #define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 254 #endif 255 256 /* 257 * SDRAM on the LocalBus 258 */ 259 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 260 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 261 262 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 263 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 264 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 265 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 266 267 #define CONFIG_SYS_INIT_RAM_LOCK 1 268 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 269 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 270 271 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 272 #define CONFIG_SYS_GBL_DATA_OFFSET \ 273 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 274 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 275 276 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 277 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 278 279 /* Serial Port */ 280 #define CONFIG_CONS_INDEX 1 281 #define CONFIG_SERIAL_MULTI 1 282 #undef CONFIG_SERIAL_SOFTWARE_FIFO 283 #define CONFIG_SYS_NS16550 284 #define CONFIG_SYS_NS16550_SERIAL 285 #define CONFIG_SYS_NS16550_REG_SIZE 1 286 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 287 288 #define CONFIG_SYS_BAUDRATE_TABLE \ 289 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 290 291 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 292 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 293 294 /* Use the HUSH parser*/ 295 #define CONFIG_SYS_HUSH_PARSER 296 #ifdef CONFIG_SYS_HUSH_PARSER 297 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 298 #endif 299 300 /* pass open firmware flat tree */ 301 #define CONFIG_OF_LIBFDT 1 302 #define CONFIG_OF_BOARD_SETUP 1 303 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 304 305 /* 306 * I2C 307 */ 308 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 309 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 310 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 311 #define CONFIG_I2C_MULTI_BUS 312 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 313 #define CONFIG_SYS_I2C_SLAVE 0x7F 314 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 315 #define CONFIG_SYS_I2C_OFFSET 0x3000 316 #define CONFIG_SYS_I2C2_OFFSET 0x3100 317 318 /* 319 * I2C2 EEPROM 320 */ 321 #define CONFIG_ID_EEPROM 322 #ifdef CONFIG_ID_EEPROM 323 #define CONFIG_SYS_I2C_EEPROM_NXID 324 #endif 325 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 326 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 327 #define CONFIG_SYS_EEPROM_BUS_NUM 1 328 329 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 330 #define PLPPAR1_I2C2_VAL 0x00000000 331 #define PLPPAR1_ESDHC_VAL 0x0000000A 332 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 333 #define PLPDIR1_I2C2_VAL 0x0000000F 334 #define PLPDIR1_ESDHC_VAL 0x00000006 335 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 336 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 337 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 338 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 339 340 /* 341 * General PCI 342 * Memory Addresses are mapped 1-1. I/O is mapped from 0 343 */ 344 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 345 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 346 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 347 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 348 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 349 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 350 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 351 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 352 353 #define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 354 #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 355 #define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 356 357 #ifdef CONFIG_QE 358 /* 359 * QE UEC ethernet configuration 360 */ 361 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 362 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 363 364 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 365 #define CONFIG_UEC_ETH 366 #define CONFIG_ETHPRIME "FSL UEC0" 367 #define CONFIG_PHY_MODE_NEED_CHANGE 368 369 #define CONFIG_UEC_ETH1 /* GETH1 */ 370 #define CONFIG_HAS_ETH0 371 372 #ifdef CONFIG_UEC_ETH1 373 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 374 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 375 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 376 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 377 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 378 #define CONFIG_SYS_UEC1_PHY_ADDR 7 379 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID 380 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 381 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 382 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 383 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 384 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 385 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII 386 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 387 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 388 #endif /* CONFIG_UEC_ETH1 */ 389 390 #define CONFIG_UEC_ETH2 /* GETH2 */ 391 #define CONFIG_HAS_ETH1 392 393 #ifdef CONFIG_UEC_ETH2 394 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 395 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 396 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 397 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 398 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 399 #define CONFIG_SYS_UEC2_PHY_ADDR 1 400 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID 401 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 402 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 403 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 404 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 405 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 406 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII 407 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 408 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 409 #endif /* CONFIG_UEC_ETH2 */ 410 411 #define CONFIG_UEC_ETH3 /* GETH3 */ 412 #define CONFIG_HAS_ETH2 413 414 #ifdef CONFIG_UEC_ETH3 415 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 416 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 417 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 418 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 419 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 420 #define CONFIG_SYS_UEC3_PHY_ADDR 2 421 #define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID 422 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 423 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 424 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 425 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 426 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 427 #define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII 428 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 429 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 430 #endif /* CONFIG_UEC_ETH3 */ 431 432 #define CONFIG_UEC_ETH4 /* GETH4 */ 433 #define CONFIG_HAS_ETH3 434 435 #ifdef CONFIG_UEC_ETH4 436 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 437 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 438 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 439 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 440 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 441 #define CONFIG_SYS_UEC4_PHY_ADDR 3 442 #define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID 443 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 444 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 445 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 446 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 447 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 448 #define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII 449 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 450 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 451 #endif /* CONFIG_UEC_ETH4 */ 452 453 #undef CONFIG_UEC_ETH6 /* GETH6 */ 454 #define CONFIG_HAS_ETH5 455 456 #ifdef CONFIG_UEC_ETH6 457 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 458 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 459 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 460 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 461 #define CONFIG_SYS_UEC6_PHY_ADDR 4 462 #define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII 463 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 464 #endif /* CONFIG_UEC_ETH6 */ 465 466 #undef CONFIG_UEC_ETH8 /* GETH8 */ 467 #define CONFIG_HAS_ETH7 468 469 #ifdef CONFIG_UEC_ETH8 470 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 471 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 472 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 473 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 474 #define CONFIG_SYS_UEC8_PHY_ADDR 6 475 #define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII 476 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 477 #endif /* CONFIG_UEC_ETH8 */ 478 479 #endif /* CONFIG_QE */ 480 481 #if defined(CONFIG_PCI) 482 483 #define CONFIG_NET_MULTI 484 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 485 486 #undef CONFIG_EEPRO100 487 #undef CONFIG_TULIP 488 489 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 490 491 #endif /* CONFIG_PCI */ 492 493 #ifndef CONFIG_NET_MULTI 494 #define CONFIG_NET_MULTI 1 495 #endif 496 497 /* 498 * Environment 499 */ 500 #if defined(CONFIG_SYS_RAMBOOT) 501 #if defined(CONFIG_RAMBOOT_NAND) 502 #define CONFIG_ENV_IS_IN_NAND 1 503 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 504 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 505 #endif 506 #else 507 #define CONFIG_ENV_IS_IN_FLASH 1 508 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 509 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ 510 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 511 #endif 512 513 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 514 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 515 516 /* QE microcode/firmware address */ 517 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 518 519 /* 520 * BOOTP options 521 */ 522 #define CONFIG_BOOTP_BOOTFILESIZE 523 #define CONFIG_BOOTP_BOOTPATH 524 #define CONFIG_BOOTP_GATEWAY 525 #define CONFIG_BOOTP_HOSTNAME 526 527 528 /* 529 * Command line configuration. 530 */ 531 #include <config_cmd_default.h> 532 533 #define CONFIG_CMD_PING 534 #define CONFIG_CMD_I2C 535 #define CONFIG_CMD_MII 536 #define CONFIG_CMD_ELF 537 #define CONFIG_CMD_IRQ 538 #define CONFIG_CMD_SETEXPR 539 540 #if defined(CONFIG_PCI) 541 #define CONFIG_CMD_PCI 542 #endif 543 544 545 #undef CONFIG_WATCHDOG /* watchdog disabled */ 546 547 #define CONFIG_MMC 1 548 549 #ifdef CONFIG_MMC 550 #define CONFIG_FSL_ESDHC 551 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 552 #define CONFIG_CMD_MMC 553 #define CONFIG_GENERIC_MMC 554 #define CONFIG_CMD_EXT2 555 #define CONFIG_CMD_FAT 556 #define CONFIG_DOS_PARTITION 557 #endif 558 559 /* 560 * Miscellaneous configurable options 561 */ 562 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 563 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 564 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 565 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 566 #if defined(CONFIG_CMD_KGDB) 567 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 568 #else 569 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 570 #endif 571 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 572 /* Print Buffer Size */ 573 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 574 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 575 /* Boot Argument Buffer Size */ 576 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 577 578 /* 579 * For booting Linux, the board info and command line data 580 * have to be in the first 16 MB of memory, since this is 581 * the maximum mapped by the Linux kernel during initialization. 582 */ 583 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) 584 /* Initial Memory map for Linux*/ 585 586 /* 587 * Internal Definitions 588 * 589 * Boot Flags 590 */ 591 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 592 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 593 594 #if defined(CONFIG_CMD_KGDB) 595 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 596 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 597 #endif 598 599 /* 600 * Environment Configuration 601 */ 602 #define CONFIG_HOSTNAME mpc8569mds 603 #define CONFIG_ROOTPATH /nfsroot 604 #define CONFIG_BOOTFILE your.uImage 605 606 #define CONFIG_SERVERIP 192.168.1.1 607 #define CONFIG_GATEWAYIP 192.168.1.1 608 #define CONFIG_NETMASK 255.255.255.0 609 610 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 611 612 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 613 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 614 615 #define CONFIG_BAUDRATE 115200 616 617 #define CONFIG_EXTRA_ENV_SETTINGS \ 618 "netdev=eth0\0" \ 619 "consoledev=ttyS0\0" \ 620 "ramdiskaddr=600000\0" \ 621 "ramdiskfile=your.ramdisk.u-boot\0" \ 622 "fdtaddr=400000\0" \ 623 "fdtfile=your.fdt.dtb\0" \ 624 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 625 "nfsroot=$serverip:$rootpath " \ 626 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 627 "console=$consoledev,$baudrate $othbootargs\0" \ 628 "ramargs=setenv bootargs root=/dev/ram rw " \ 629 "console=$consoledev,$baudrate $othbootargs\0" \ 630 631 #define CONFIG_NFSBOOTCOMMAND \ 632 "run nfsargs;" \ 633 "tftp $loadaddr $bootfile;" \ 634 "tftp $fdtaddr $fdtfile;" \ 635 "bootm $loadaddr - $fdtaddr" 636 637 #define CONFIG_RAMBOOTCOMMAND \ 638 "run ramargs;" \ 639 "tftp $ramdiskaddr $ramdiskfile;" \ 640 "tftp $loadaddr $bootfile;" \ 641 "bootm $loadaddr $ramdiskaddr" 642 643 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 644 645 #endif /* __CONFIG_H */ 646