1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8569mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_SYS_GENERIC_BOARD 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 /* High Level Configuration Options */ 17 #define CONFIG_BOOKE 1 /* BOOKE */ 18 #define CONFIG_E500 1 /* BOOKE e500 family */ 19 #define CONFIG_MPC8569 1 /* MPC8569 specific */ 20 #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ 21 22 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ 23 24 #define CONFIG_SYS_SRIO 25 #define CONFIG_SRIO1 /* SRIO port 1 */ 26 27 #define CONFIG_PCI 1 /* Disable PCI/PCIE */ 28 #define CONFIG_PCIE1 1 /* PCIE controller */ 29 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 30 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 31 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 32 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 33 #define CONFIG_QE /* Enable QE */ 34 #define CONFIG_ENV_OVERWRITE 35 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 36 37 #ifndef __ASSEMBLY__ 38 extern unsigned long get_clock_freq(void); 39 #endif 40 /* Replace a call to get_clock_freq (after it is implemented)*/ 41 #define CONFIG_SYS_CLK_FREQ 66666666 42 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 43 44 #ifdef CONFIG_ATM 45 #define CONFIG_PQ_MDS_PIB 46 #define CONFIG_PQ_MDS_PIB_ATM 47 #endif 48 49 /* 50 * These can be toggled for performance analysis, otherwise use default. 51 */ 52 #define CONFIG_L2_CACHE /* toggle L2 cache */ 53 #define CONFIG_BTB /* toggle branch predition */ 54 55 #ifndef CONFIG_SYS_TEXT_BASE 56 #define CONFIG_SYS_TEXT_BASE 0xfff80000 57 #endif 58 59 #ifndef CONFIG_SYS_MONITOR_BASE 60 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 61 #endif 62 63 /* 64 * Only possible on E500 Version 2 or newer cores. 65 */ 66 #define CONFIG_ENABLE_36BIT_PHYS 1 67 68 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 69 #define CONFIG_BOARD_EARLY_INIT_R 1 70 #define CONFIG_HWCONFIG 71 72 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 73 #define CONFIG_SYS_MEMTEST_END 0x00400000 74 75 /* 76 * Config the L2 Cache as L2 SRAM 77 */ 78 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 79 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 80 #define CONFIG_SYS_L2_SIZE (512 << 10) 81 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 82 83 #define CONFIG_SYS_CCSRBAR 0xe0000000 84 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 85 86 #if defined(CONFIG_NAND_SPL) 87 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 88 #endif 89 90 /* DDR Setup */ 91 #define CONFIG_SYS_FSL_DDR3 92 #undef CONFIG_FSL_DDR_INTERACTIVE 93 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 94 #define CONFIG_DDR_SPD 95 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 96 97 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 98 99 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 100 /* DDR is system memory*/ 101 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 102 103 #define CONFIG_NUM_DDR_CONTROLLERS 1 104 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 105 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 106 107 /* I2C addresses of SPD EEPROMs */ 108 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 109 110 /* These are used when DDR doesn't use SPD. */ 111 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 112 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 113 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 114 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 115 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 116 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 117 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 118 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 119 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 120 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 121 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 122 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 123 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 124 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 125 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 126 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 127 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 128 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 129 #define CONFIG_SYS_DDR_CDR_1 0x80040000 130 #define CONFIG_SYS_DDR_CDR_2 0x00000000 131 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 132 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 133 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 134 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 135 136 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 137 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 138 #define CONFIG_SYS_DDR_SBE 0x00010000 139 140 #undef CONFIG_CLOCKS_IN_MHZ 141 142 /* 143 * Local Bus Definitions 144 */ 145 146 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 147 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 148 149 #define CONFIG_SYS_BCSR_BASE 0xf8000000 150 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 151 152 /*Chip select 0 - Flash*/ 153 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 154 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 155 156 /*Chip select 1 - BCSR*/ 157 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 158 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 159 160 /*Chip select 4 - PIB*/ 161 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 162 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 163 164 /*Chip select 5 - PIB*/ 165 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 166 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 167 168 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 169 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 170 #undef CONFIG_SYS_FLASH_CHECKSUM 171 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 172 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 173 174 #undef CONFIG_SYS_RAMBOOT 175 176 #define CONFIG_FLASH_CFI_DRIVER 177 #define CONFIG_SYS_FLASH_CFI 178 #define CONFIG_SYS_FLASH_EMPTY_INFO 179 180 /* Chip select 3 - NAND */ 181 #ifndef CONFIG_NAND_SPL 182 #define CONFIG_SYS_NAND_BASE 0xFC000000 183 #else 184 #define CONFIG_SYS_NAND_BASE 0xFFF00000 185 #endif 186 187 /* NAND boot: 4K NAND loader config */ 188 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 189 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 190 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 191 #define CONFIG_SYS_NAND_U_BOOT_START \ 192 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 193 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 194 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 195 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 196 197 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 198 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 199 #define CONFIG_SYS_MAX_NAND_DEVICE 1 200 #define CONFIG_CMD_NAND 1 201 #define CONFIG_NAND_FSL_ELBC 1 202 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 203 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 204 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 205 | BR_PS_8 /* Port Size = 8 bit */ \ 206 | BR_MS_FCM /* MSEL = FCM */ \ 207 | BR_V) /* valid */ 208 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 209 | OR_FCM_CSCT \ 210 | OR_FCM_CST \ 211 | OR_FCM_CHT \ 212 | OR_FCM_SCY_1 \ 213 | OR_FCM_TRLX \ 214 | OR_FCM_EHTR) 215 216 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 217 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 218 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 219 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 220 221 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 222 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 223 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 224 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 225 226 #define CONFIG_SYS_INIT_RAM_LOCK 1 227 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 228 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 229 230 #define CONFIG_SYS_GBL_DATA_OFFSET \ 231 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 232 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 233 234 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 235 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 236 237 /* Serial Port */ 238 #define CONFIG_CONS_INDEX 1 239 #define CONFIG_SYS_NS16550 240 #define CONFIG_SYS_NS16550_SERIAL 241 #define CONFIG_SYS_NS16550_REG_SIZE 1 242 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 243 #ifdef CONFIG_NAND_SPL 244 #define CONFIG_NS16550_MIN_FUNCTIONS 245 #endif 246 247 #define CONFIG_SYS_BAUDRATE_TABLE \ 248 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 249 250 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 251 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 252 253 /* Use the HUSH parser*/ 254 #define CONFIG_SYS_HUSH_PARSER 255 #ifdef CONFIG_SYS_HUSH_PARSER 256 #endif 257 258 /* pass open firmware flat tree */ 259 #define CONFIG_OF_LIBFDT 1 260 #define CONFIG_OF_BOARD_SETUP 1 261 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 262 263 /* 264 * I2C 265 */ 266 #define CONFIG_SYS_I2C 267 #define CONFIG_SYS_I2C_FSL 268 #define CONFIG_SYS_FSL_I2C_SPEED 400000 269 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 270 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 271 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 272 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 273 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 274 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 275 276 /* 277 * I2C2 EEPROM 278 */ 279 #define CONFIG_ID_EEPROM 280 #ifdef CONFIG_ID_EEPROM 281 #define CONFIG_SYS_I2C_EEPROM_NXID 282 #endif 283 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 284 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 285 #define CONFIG_SYS_EEPROM_BUS_NUM 1 286 287 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 288 #define PLPPAR1_I2C2_VAL 0x00000000 289 #define PLPPAR1_ESDHC_VAL 0x0000000A 290 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 291 #define PLPDIR1_I2C2_VAL 0x0000000F 292 #define PLPDIR1_ESDHC_VAL 0x00000006 293 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 294 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 295 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 296 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 297 298 /* 299 * General PCI 300 * Memory Addresses are mapped 1-1. I/O is mapped from 0 301 */ 302 #define CONFIG_SYS_PCIE1_NAME "Slot" 303 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 304 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 305 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 306 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 307 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 308 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 309 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 310 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 311 312 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 313 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 314 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 315 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 316 317 #ifdef CONFIG_QE 318 /* 319 * QE UEC ethernet configuration 320 */ 321 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 322 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 323 324 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 325 #define CONFIG_UEC_ETH 326 #define CONFIG_ETHPRIME "UEC0" 327 #define CONFIG_PHY_MODE_NEED_CHANGE 328 329 #define CONFIG_UEC_ETH1 /* GETH1 */ 330 #define CONFIG_HAS_ETH0 331 332 #ifdef CONFIG_UEC_ETH1 333 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 334 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 335 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 336 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 337 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 338 #define CONFIG_SYS_UEC1_PHY_ADDR 7 339 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 340 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 341 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 342 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 343 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 344 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 345 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 346 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 347 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 348 #endif /* CONFIG_UEC_ETH1 */ 349 350 #define CONFIG_UEC_ETH2 /* GETH2 */ 351 #define CONFIG_HAS_ETH1 352 353 #ifdef CONFIG_UEC_ETH2 354 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 355 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 356 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 357 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 358 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 359 #define CONFIG_SYS_UEC2_PHY_ADDR 1 360 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 361 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 362 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 363 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 364 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 365 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 366 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 367 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 368 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 369 #endif /* CONFIG_UEC_ETH2 */ 370 371 #define CONFIG_UEC_ETH3 /* GETH3 */ 372 #define CONFIG_HAS_ETH2 373 374 #ifdef CONFIG_UEC_ETH3 375 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 376 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 377 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 378 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 379 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 380 #define CONFIG_SYS_UEC3_PHY_ADDR 2 381 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 382 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 383 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 384 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 385 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 386 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 387 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 388 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 389 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 390 #endif /* CONFIG_UEC_ETH3 */ 391 392 #define CONFIG_UEC_ETH4 /* GETH4 */ 393 #define CONFIG_HAS_ETH3 394 395 #ifdef CONFIG_UEC_ETH4 396 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 397 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 398 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 399 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 400 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 401 #define CONFIG_SYS_UEC4_PHY_ADDR 3 402 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 403 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 404 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 405 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 406 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 407 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 408 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 409 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 410 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 411 #endif /* CONFIG_UEC_ETH4 */ 412 413 #undef CONFIG_UEC_ETH6 /* GETH6 */ 414 #define CONFIG_HAS_ETH5 415 416 #ifdef CONFIG_UEC_ETH6 417 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 418 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 419 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 420 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 421 #define CONFIG_SYS_UEC6_PHY_ADDR 4 422 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 423 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 424 #endif /* CONFIG_UEC_ETH6 */ 425 426 #undef CONFIG_UEC_ETH8 /* GETH8 */ 427 #define CONFIG_HAS_ETH7 428 429 #ifdef CONFIG_UEC_ETH8 430 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 431 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 432 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 433 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 434 #define CONFIG_SYS_UEC8_PHY_ADDR 6 435 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 436 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 437 #endif /* CONFIG_UEC_ETH8 */ 438 439 #endif /* CONFIG_QE */ 440 441 #if defined(CONFIG_PCI) 442 443 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 444 445 #undef CONFIG_EEPRO100 446 #undef CONFIG_TULIP 447 448 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 449 450 #endif /* CONFIG_PCI */ 451 452 /* 453 * Environment 454 */ 455 #if defined(CONFIG_SYS_RAMBOOT) 456 #else 457 #define CONFIG_ENV_IS_IN_FLASH 1 458 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 459 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 460 #define CONFIG_ENV_SIZE 0x2000 461 #endif 462 463 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 464 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 465 466 /* QE microcode/firmware address */ 467 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 468 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 469 470 /* 471 * BOOTP options 472 */ 473 #define CONFIG_BOOTP_BOOTFILESIZE 474 #define CONFIG_BOOTP_BOOTPATH 475 #define CONFIG_BOOTP_GATEWAY 476 #define CONFIG_BOOTP_HOSTNAME 477 478 479 /* 480 * Command line configuration. 481 */ 482 #define CONFIG_CMD_PING 483 #define CONFIG_CMD_I2C 484 #define CONFIG_CMD_MII 485 #define CONFIG_CMD_ELF 486 #define CONFIG_CMD_IRQ 487 #define CONFIG_CMD_REGINFO 488 489 #if defined(CONFIG_PCI) 490 #define CONFIG_CMD_PCI 491 #endif 492 493 494 #undef CONFIG_WATCHDOG /* watchdog disabled */ 495 496 #define CONFIG_MMC 1 497 498 #ifdef CONFIG_MMC 499 #define CONFIG_FSL_ESDHC 500 #define CONFIG_FSL_ESDHC_PIN_MUX 501 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 502 #define CONFIG_CMD_MMC 503 #define CONFIG_GENERIC_MMC 504 #define CONFIG_CMD_EXT2 505 #define CONFIG_CMD_FAT 506 #define CONFIG_DOS_PARTITION 507 #endif 508 509 /* 510 * Miscellaneous configurable options 511 */ 512 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 513 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 514 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 515 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 516 #if defined(CONFIG_CMD_KGDB) 517 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 518 #else 519 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 520 #endif 521 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 522 /* Print Buffer Size */ 523 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 524 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 525 /* Boot Argument Buffer Size */ 526 527 /* 528 * For booting Linux, the board info and command line data 529 * have to be in the first 64 MB of memory, since this is 530 * the maximum mapped by the Linux kernel during initialization. 531 */ 532 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 533 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 534 535 #if defined(CONFIG_CMD_KGDB) 536 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 537 #endif 538 539 /* 540 * Environment Configuration 541 */ 542 #define CONFIG_HOSTNAME mpc8569mds 543 #define CONFIG_ROOTPATH "/nfsroot" 544 #define CONFIG_BOOTFILE "your.uImage" 545 546 #define CONFIG_SERVERIP 192.168.1.1 547 #define CONFIG_GATEWAYIP 192.168.1.1 548 #define CONFIG_NETMASK 255.255.255.0 549 550 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 551 552 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 553 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 554 555 #define CONFIG_BAUDRATE 115200 556 557 #define CONFIG_EXTRA_ENV_SETTINGS \ 558 "netdev=eth0\0" \ 559 "consoledev=ttyS0\0" \ 560 "ramdiskaddr=600000\0" \ 561 "ramdiskfile=your.ramdisk.u-boot\0" \ 562 "fdtaddr=400000\0" \ 563 "fdtfile=your.fdt.dtb\0" \ 564 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 565 "nfsroot=$serverip:$rootpath " \ 566 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 567 "console=$consoledev,$baudrate $othbootargs\0" \ 568 "ramargs=setenv bootargs root=/dev/ram rw " \ 569 "console=$consoledev,$baudrate $othbootargs\0" \ 570 571 #define CONFIG_NFSBOOTCOMMAND \ 572 "run nfsargs;" \ 573 "tftp $loadaddr $bootfile;" \ 574 "tftp $fdtaddr $fdtfile;" \ 575 "bootm $loadaddr - $fdtaddr" 576 577 #define CONFIG_RAMBOOTCOMMAND \ 578 "run ramargs;" \ 579 "tftp $ramdiskaddr $ramdiskfile;" \ 580 "tftp $loadaddr $bootfile;" \ 581 "bootm $loadaddr $ramdiskaddr" 582 583 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 584 585 #endif /* __CONFIG_H */ 586