xref: /openbmc/u-boot/include/configs/MPC8569MDS.h (revision 9b107e6138e719ea5a0b924862a9b109c020c7ac)
1 /*
2  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20  * MA 02111-1307 USA
21  */
22 
23 /*
24  * mpc8569mds board configuration file
25  */
26 #ifndef __CONFIG_H
27 #define __CONFIG_H
28 
29 /* High Level Configuration Options */
30 #define CONFIG_BOOKE		1	/* BOOKE */
31 #define CONFIG_E500		1	/* BOOKE e500 family */
32 #define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48/68 */
33 #define CONFIG_MPC8569		1	/* MPC8569 specific */
34 #define CONFIG_MPC8569MDS	1	/* MPC8569MDS board specific */
35 
36 #define CONFIG_FSL_ELBC		1	/* Has Enhance localbus controller */
37 
38 #define CONFIG_PCI		1	/* Disable PCI/PCIE */
39 #define CONFIG_PCIE1		1	/* PCIE controller */
40 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
41 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
42 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
43 #define CONFIG_QE			/* Enable QE */
44 #define CONFIG_ENV_OVERWRITE
45 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
46 
47 #ifndef __ASSEMBLY__
48 extern unsigned long get_clock_freq(void);
49 #endif
50 /* Replace a call to get_clock_freq (after it is implemented)*/
51 #define CONFIG_SYS_CLK_FREQ	66666666
52 #define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
53 
54 #ifdef CONFIG_ATM
55 #define CONFIG_PQ_MDS_PIB
56 #define CONFIG_PQ_MDS_PIB_ATM
57 #endif
58 
59 /*
60  * These can be toggled for performance analysis, otherwise use default.
61  */
62 #define CONFIG_L2_CACHE				/* toggle L2 cache	*/
63 #define CONFIG_BTB				/* toggle branch predition */
64 
65 #ifdef CONFIG_NAND
66 #define CONFIG_NAND_U_BOOT		1
67 #define CONFIG_RAMBOOT_NAND		1
68 #ifdef CONFIG_NAND_SPL
69 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
70 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
71 #else
72 #define CONFIG_SYS_TEXT_BASE	0xf8f82000
73 #endif
74 #endif
75 
76 #ifndef CONFIG_SYS_TEXT_BASE
77 #define CONFIG_SYS_TEXT_BASE	0xfff80000
78 #endif
79 
80 #ifndef CONFIG_SYS_MONITOR_BASE
81 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
82 #endif
83 
84 /*
85  * Only possible on E500 Version 2 or newer cores.
86  */
87 #define CONFIG_ENABLE_36BIT_PHYS	1
88 
89 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
90 #define CONFIG_BOARD_EARLY_INIT_R	1
91 #define CONFIG_HWCONFIG
92 
93 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
94 #define CONFIG_SYS_MEMTEST_END		0x00400000
95 
96 /*
97  * Config the L2 Cache as L2 SRAM
98  */
99 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
100 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
101 #define CONFIG_SYS_L2_SIZE		(512 << 10)
102 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
103 
104 /*
105  * Base addresses -- Note these are effective addresses where the
106  * actual resources get mapped (not physical addresses)
107  */
108 #define CONFIG_SYS_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
109 #define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR
110 						/* physical addr of CCSRBAR */
111 #define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR
112 						/* PQII uses CONFIG_SYS_IMMR */
113 
114 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
115 #define CONFIG_SYS_CCSRBAR_DEFAULT	CONFIG_SYS_CCSRBAR
116 #else
117 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
118 #endif
119 
120 /* DDR Setup */
121 #define CONFIG_FSL_DDR3
122 #undef CONFIG_FSL_DDR_INTERACTIVE
123 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
124 #define CONFIG_DDR_SPD
125 #define CONFIG_DDR_DLL			/* possible DLL fix needed */
126 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
127 
128 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
129 
130 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
131 					/* DDR is system memory*/
132 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
133 
134 #define CONFIG_NUM_DDR_CONTROLLERS	1
135 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
136 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
137 
138 /* I2C addresses of SPD EEPROMs */
139 #define SPD_EEPROM_ADDRESS1    0x51    /* CTLR 0 DIMM 0 */
140 #define SPD_EEPROM_ADDRESS2    0x52    /* CTLR 1 DIMM 0 */
141 
142 /* These are used when DDR doesn't use SPD.  */
143 #define CONFIG_SYS_SDRAM_SIZE           1024		/* DDR is 1024MB */
144 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
145 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
146 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
147 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
148 #define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
149 #define CONFIG_SYS_DDR_TIMING_2         0x002888D0
150 #define CONFIG_SYS_DDR_SDRAM_CFG	0x47000000
151 #define CONFIG_SYS_DDR_SDRAM_CFG_2	0x04401040
152 #define CONFIG_SYS_DDR_SDRAM_MODE	0x40401521
153 #define CONFIG_SYS_DDR_SDRAM_MODE_2	0x8000C000
154 #define CONFIG_SYS_DDR_SDRAM_INTERVAL	0x03E00000
155 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
156 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x01000000
157 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
158 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
159 #define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
160 #define CONFIG_SYS_DDR_WRLVL_CNTL	0x0655A604
161 #define CONFIG_SYS_DDR_CDR_1		0x80040000
162 #define CONFIG_SYS_DDR_CDR_2		0x00000000
163 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
164 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
165 #define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
166 #define CONFIG_SYS_DDR_CONTROL2         0x24400000
167 
168 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
169 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
170 #define CONFIG_SYS_DDR_SBE              0x00010000
171 
172 #undef CONFIG_CLOCKS_IN_MHZ
173 
174 /*
175  * Local Bus Definitions
176  */
177 
178 #define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
179 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
180 
181 #define CONFIG_SYS_BCSR_BASE		0xf8000000
182 #define CONFIG_SYS_BCSR_BASE_PHYS	CONFIG_SYS_BCSR_BASE
183 
184 /*Chip select 0 - Flash*/
185 #define CONFIG_FLASH_BR_PRELIM		0xfe000801
186 #define	CONFIG_FLASH_OR_PRELIM		0xfe000ff7
187 
188 /*Chip select 1 - BCSR*/
189 #define CONFIG_SYS_BR1_PRELIM		0xf8000801
190 #define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
191 
192 /*Chip select 4 - PIB*/
193 #define CONFIG_SYS_BR4_PRELIM		0xf8008801
194 #define CONFIG_SYS_OR4_PRELIM		0xffffe9f7
195 
196 /*Chip select 5 - PIB*/
197 #define CONFIG_SYS_BR5_PRELIM		0xf8010801
198 #define CONFIG_SYS_OR5_PRELIM		0xffffe9f7
199 
200 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
201 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
202 #undef	CONFIG_SYS_FLASH_CHECKSUM
203 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
204 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
205 
206 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
207 #define CONFIG_SYS_RAMBOOT
208 #else
209 #undef CONFIG_SYS_RAMBOOT
210 #endif
211 
212 #define CONFIG_FLASH_CFI_DRIVER
213 #define CONFIG_SYS_FLASH_CFI
214 #define CONFIG_SYS_FLASH_EMPTY_INFO
215 
216 /* Chip select 3 - NAND */
217 #ifndef CONFIG_NAND_SPL
218 #define CONFIG_SYS_NAND_BASE		0xFC000000
219 #else
220 #define CONFIG_SYS_NAND_BASE		0xFFF00000
221 #endif
222 
223 /* NAND boot: 4K NAND loader config */
224 #define CONFIG_SYS_NAND_SPL_SIZE	0x1000
225 #define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
226 #define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
227 #define CONFIG_SYS_NAND_U_BOOT_START \
228 	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
229 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
230 #define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
231 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
232 
233 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
234 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, }
235 #define CONFIG_SYS_MAX_NAND_DEVICE	1
236 #define CONFIG_MTD_NAND_VERIFY_WRITE	1
237 #define CONFIG_CMD_NAND			1
238 #define CONFIG_NAND_FSL_ELBC		1
239 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
240 #define CONFIG_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE_PHYS \
241 				| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
242 				| BR_PS_8	     /* Port Size = 8 bit */ \
243 				| BR_MS_FCM	     /* MSEL = FCM */ \
244 				| BR_V)		     /* valid */
245 #define CONFIG_NAND_OR_PRELIM	(0xFFFC0000	     /* length 256K */ \
246 				| OR_FCM_CSCT \
247 				| OR_FCM_CST \
248 				| OR_FCM_CHT \
249 				| OR_FCM_SCY_1 \
250 				| OR_FCM_TRLX \
251 				| OR_FCM_EHTR)
252 
253 #ifdef CONFIG_RAMBOOT_NAND
254 #define CONFIG_SYS_BR0_PRELIM	CONFIG_NAND_BR_PRELIM	/* NAND Base Address */
255 #define CONFIG_SYS_OR0_PRELIM	CONFIG_NAND_OR_PRELIM	/* NAND Options */
256 #define CONFIG_SYS_BR3_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
257 #define CONFIG_SYS_OR3_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
258 #else
259 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
260 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
261 #define CONFIG_SYS_BR3_PRELIM	CONFIG_NAND_BR_PRELIM /* NAND Base Address */
262 #define CONFIG_SYS_OR3_PRELIM	CONFIG_NAND_OR_PRELIM /* NAND Options */
263 #endif
264 
265 /*
266  * SDRAM on the LocalBus
267  */
268 #define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM	 */
269 #define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
270 
271 #define CONFIG_SYS_LBC_LCRR	0x00000004	/* LB clock ratio reg */
272 #define CONFIG_SYS_LBC_LBCR	0x00040000	/* LB config reg */
273 #define CONFIG_SYS_LBC_LSRT	0x20000000	/* LB sdram refresh timer */
274 #define CONFIG_SYS_LBC_MRTPR	0x00000000	/* LB refresh timer prescal*/
275 
276 #define CONFIG_SYS_INIT_RAM_LOCK	1
277 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000  /* Initial RAM address */
278 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
279 
280 #define CONFIG_SYS_GBL_DATA_OFFSET	\
281 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
282 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
283 
284 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
285 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
286 
287 /* Serial Port */
288 #define CONFIG_CONS_INDEX		1
289 #define CONFIG_SERIAL_MULTI		1
290 #define CONFIG_SYS_NS16550
291 #define CONFIG_SYS_NS16550_SERIAL
292 #define CONFIG_SYS_NS16550_REG_SIZE    1
293 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
294 #ifdef CONFIG_NAND_SPL
295 #define CONFIG_NS16550_MIN_FUNCTIONS
296 #endif
297 
298 #define CONFIG_SYS_BAUDRATE_TABLE  \
299 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
300 
301 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
302 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
303 
304 /* Use the HUSH parser*/
305 #define CONFIG_SYS_HUSH_PARSER
306 #ifdef  CONFIG_SYS_HUSH_PARSER
307 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
308 #endif
309 
310 /* pass open firmware flat tree */
311 #define CONFIG_OF_LIBFDT		1
312 #define CONFIG_OF_BOARD_SETUP		1
313 #define CONFIG_OF_STDOUT_VIA_ALIAS	1
314 
315 /*
316  * I2C
317  */
318 #define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
319 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
320 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
321 #define CONFIG_I2C_MULTI_BUS
322 #define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
323 #define CONFIG_SYS_I2C_SLAVE	0x7F
324 #define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
325 #define CONFIG_SYS_I2C_OFFSET	0x3000
326 #define CONFIG_SYS_I2C2_OFFSET	0x3100
327 
328 /*
329  * I2C2 EEPROM
330  */
331 #define CONFIG_ID_EEPROM
332 #ifdef CONFIG_ID_EEPROM
333 #define CONFIG_SYS_I2C_EEPROM_NXID
334 #endif
335 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
336 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
337 #define CONFIG_SYS_EEPROM_BUS_NUM       1
338 
339 #define PLPPAR1_I2C_BIT_MASK		0x0000000F
340 #define PLPPAR1_I2C2_VAL		0x00000000
341 #define PLPPAR1_ESDHC_VAL		0x0000000A
342 #define PLPDIR1_I2C_BIT_MASK		0x0000000F
343 #define PLPDIR1_I2C2_VAL		0x0000000F
344 #define PLPDIR1_ESDHC_VAL		0x00000006
345 #define PLPPAR1_UART0_BIT_MASK		0x00000fc0
346 #define PLPPAR1_ESDHC_4BITS_VAL		0x00000a80
347 #define PLPDIR1_UART0_BIT_MASK		0x00000fc0
348 #define PLPDIR1_ESDHC_4BITS_VAL		0x00000a80
349 
350 /*
351  * General PCI
352  * Memory Addresses are mapped 1-1. I/O is mapped from 0
353  */
354 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
355 #define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
356 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
357 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
358 #define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
359 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
360 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
361 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
362 
363 #define CONFIG_SYS_SRIO_MEM_VIRT	0xc0000000
364 #define CONFIG_SYS_SRIO_MEM_BUS		0xc0000000
365 #define CONFIG_SYS_SRIO_MEM_PHYS	0xc0000000
366 
367 #ifdef CONFIG_QE
368 /*
369  * QE UEC ethernet configuration
370  */
371 #define CONFIG_SYS_UCC_RGMII_MODE	/* Set UCC work at RGMII by default */
372 #undef CONFIG_SYS_UCC_RMII_MODE		/* Set UCC work at RMII mode */
373 
374 #define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
375 #define CONFIG_UEC_ETH
376 #define CONFIG_ETHPRIME         "UEC0"
377 #define CONFIG_PHY_MODE_NEED_CHANGE
378 
379 #define CONFIG_UEC_ETH1         /* GETH1 */
380 #define CONFIG_HAS_ETH0
381 
382 #ifdef CONFIG_UEC_ETH1
383 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
384 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
385 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
386 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
387 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
388 #define CONFIG_SYS_UEC1_PHY_ADDR       7
389 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
390 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
391 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
392 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16	/* CLK16 for RMII */
393 #define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
394 #define CONFIG_SYS_UEC1_PHY_ADDR       8	/* 0x8 for RMII */
395 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
396 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
397 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
398 #endif /* CONFIG_UEC_ETH1 */
399 
400 #define CONFIG_UEC_ETH2         /* GETH2 */
401 #define CONFIG_HAS_ETH1
402 
403 #ifdef CONFIG_UEC_ETH2
404 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
405 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
406 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
407 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
408 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
409 #define CONFIG_SYS_UEC2_PHY_ADDR       1
410 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
411 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
412 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
413 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16	/* CLK 16 for RMII */
414 #define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
415 #define CONFIG_SYS_UEC2_PHY_ADDR       0x9	/* 0x9 for RMII */
416 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII
417 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
418 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
419 #endif /* CONFIG_UEC_ETH2 */
420 
421 #define CONFIG_UEC_ETH3         /* GETH3 */
422 #define CONFIG_HAS_ETH2
423 
424 #ifdef CONFIG_UEC_ETH3
425 #define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
426 #define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
427 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
428 #define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
429 #define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
430 #define CONFIG_SYS_UEC3_PHY_ADDR       2
431 #define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID
432 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
433 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
434 #define CONFIG_SYS_UEC3_TX_CLK		QE_CLK16 /* CLK_16 for RMII */
435 #define CONFIG_SYS_UEC3_ETH_TYPE	FAST_ETH
436 #define CONFIG_SYS_UEC3_PHY_ADDR	0xA     /* 0xA for RMII */
437 #define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII
438 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
439 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
440 #endif /* CONFIG_UEC_ETH3 */
441 
442 #define CONFIG_UEC_ETH4         /* GETH4 */
443 #define CONFIG_HAS_ETH3
444 
445 #ifdef CONFIG_UEC_ETH4
446 #define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
447 #define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
448 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
449 #define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
450 #define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
451 #define CONFIG_SYS_UEC4_PHY_ADDR       3
452 #define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID
453 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
454 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
455 #define CONFIG_SYS_UEC4_TX_CLK		QE_CLK16 /* CLK16 for RMII */
456 #define CONFIG_SYS_UEC4_ETH_TYPE	FAST_ETH
457 #define CONFIG_SYS_UEC4_PHY_ADDR	0xB     /* 0xB for RMII */
458 #define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII
459 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
460 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
461 #endif /* CONFIG_UEC_ETH4 */
462 
463 #undef CONFIG_UEC_ETH6         /* GETH6 */
464 #define CONFIG_HAS_ETH5
465 
466 #ifdef CONFIG_UEC_ETH6
467 #define CONFIG_SYS_UEC6_UCC_NUM        5       /* UCC6 */
468 #define CONFIG_SYS_UEC6_RX_CLK         QE_CLK_NONE
469 #define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
470 #define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
471 #define CONFIG_SYS_UEC6_PHY_ADDR       4
472 #define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII
473 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
474 #endif /* CONFIG_UEC_ETH6 */
475 
476 #undef CONFIG_UEC_ETH8         /* GETH8 */
477 #define CONFIG_HAS_ETH7
478 
479 #ifdef CONFIG_UEC_ETH8
480 #define CONFIG_SYS_UEC8_UCC_NUM        7       /* UCC8 */
481 #define CONFIG_SYS_UEC8_RX_CLK         QE_CLK_NONE
482 #define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
483 #define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
484 #define CONFIG_SYS_UEC8_PHY_ADDR       6
485 #define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII
486 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
487 #endif /* CONFIG_UEC_ETH8 */
488 
489 #endif /* CONFIG_QE */
490 
491 #if defined(CONFIG_PCI)
492 
493 #define CONFIG_NET_MULTI
494 #define CONFIG_PCI_PNP			/* do pci plug-and-play */
495 
496 #undef CONFIG_EEPRO100
497 #undef CONFIG_TULIP
498 #define CONFIG_E1000			/* Define e1000 pci Ethernet card */
499 
500 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
501 
502 #endif	/* CONFIG_PCI */
503 
504 #ifndef CONFIG_NET_MULTI
505 #define CONFIG_NET_MULTI	1
506 #endif
507 
508 /*
509  * Environment
510  */
511 #if defined(CONFIG_SYS_RAMBOOT)
512 #if defined(CONFIG_RAMBOOT_NAND)
513 #define CONFIG_ENV_IS_IN_NAND	1
514 #define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
515 #define CONFIG_ENV_OFFSET	((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
516 #endif
517 #else
518 #define CONFIG_ENV_IS_IN_FLASH	1
519 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
520 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
521 #define CONFIG_ENV_SIZE		0x2000
522 #endif
523 
524 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
525 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
526 
527 /* QE microcode/firmware address */
528 #define CONFIG_SYS_QE_FW_ADDR	0xfff00000
529 
530 /*
531  * BOOTP options
532  */
533 #define CONFIG_BOOTP_BOOTFILESIZE
534 #define CONFIG_BOOTP_BOOTPATH
535 #define CONFIG_BOOTP_GATEWAY
536 #define CONFIG_BOOTP_HOSTNAME
537 
538 
539 /*
540  * Command line configuration.
541  */
542 #include <config_cmd_default.h>
543 
544 #define CONFIG_CMD_PING
545 #define CONFIG_CMD_I2C
546 #define CONFIG_CMD_MII
547 #define CONFIG_CMD_ELF
548 #define CONFIG_CMD_IRQ
549 #define CONFIG_CMD_SETEXPR
550 #define CONFIG_CMD_REGINFO
551 
552 #if defined(CONFIG_PCI)
553     #define CONFIG_CMD_PCI
554 #endif
555 
556 
557 #undef CONFIG_WATCHDOG			/* watchdog disabled */
558 
559 #define CONFIG_MMC     1
560 
561 #ifdef CONFIG_MMC
562 #define CONFIG_FSL_ESDHC
563 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
564 #define CONFIG_CMD_MMC
565 #define CONFIG_GENERIC_MMC
566 #define CONFIG_CMD_EXT2
567 #define CONFIG_CMD_FAT
568 #define CONFIG_DOS_PARTITION
569 #endif
570 
571 /*
572  * Miscellaneous configurable options
573  */
574 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
575 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
576 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
577 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
578 #define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
579 #if defined(CONFIG_CMD_KGDB)
580 #define CONFIG_SYS_CBSIZE	2048		/* Console I/O Buffer Size */
581 #else
582 #define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
583 #endif
584 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
585 						/* Print Buffer Size */
586 #define CONFIG_SYS_MAXARGS	32		/* max number of command args */
587 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
588 						/* Boot Argument Buffer Size */
589 #define CONFIG_SYS_HZ	1000		/* decrementer freq: 1ms ticks */
590 
591 /*
592  * For booting Linux, the board info and command line data
593  * have to be in the first 16 MB of memory, since this is
594  * the maximum mapped by the Linux kernel during initialization.
595  */
596 #define CONFIG_SYS_BOOTMAPSZ	(16 << 20)
597 					/* Initial Memory map for Linux*/
598 
599 #if defined(CONFIG_CMD_KGDB)
600 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
601 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
602 #endif
603 
604 /*
605  * Environment Configuration
606  */
607 #define CONFIG_HOSTNAME mpc8569mds
608 #define CONFIG_ROOTPATH  /nfsroot
609 #define CONFIG_BOOTFILE  your.uImage
610 
611 #define CONFIG_SERVERIP  192.168.1.1
612 #define CONFIG_GATEWAYIP 192.168.1.1
613 #define CONFIG_NETMASK   255.255.255.0
614 
615 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
616 
617 #define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
618 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
619 
620 #define CONFIG_BAUDRATE	115200
621 
622 #define	CONFIG_EXTRA_ENV_SETTINGS					\
623 	"netdev=eth0\0"							\
624 	"consoledev=ttyS0\0"						\
625 	"ramdiskaddr=600000\0"						\
626 	"ramdiskfile=your.ramdisk.u-boot\0"				\
627 	"fdtaddr=400000\0"						\
628 	"fdtfile=your.fdt.dtb\0"					\
629 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
630 	"nfsroot=$serverip:$rootpath "					\
631 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
632 	"console=$consoledev,$baudrate $othbootargs\0"			\
633 	"ramargs=setenv bootargs root=/dev/ram rw "			\
634 	"console=$consoledev,$baudrate $othbootargs\0"			\
635 
636 #define CONFIG_NFSBOOTCOMMAND						\
637 	"run nfsargs;"							\
638 	"tftp $loadaddr $bootfile;"					\
639 	"tftp $fdtaddr $fdtfile;"					\
640 	"bootm $loadaddr - $fdtaddr"
641 
642 #define CONFIG_RAMBOOTCOMMAND						\
643 	"run ramargs;"							\
644 	"tftp $ramdiskaddr $ramdiskfile;"				\
645 	"tftp $loadaddr $bootfile;"					\
646 	"bootm $loadaddr $ramdiskaddr"
647 
648 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
649 
650 #endif	/* __CONFIG_H */
651