xref: /openbmc/u-boot/include/configs/MPC8569MDS.h (revision 730d2544)
1 /*
2  * Copyright 2009-2011 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 /*
8  * mpc8569mds board configuration file
9  */
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 /* High Level Configuration Options */
14 #define CONFIG_BOOKE		1	/* BOOKE */
15 #define CONFIG_E500		1	/* BOOKE e500 family */
16 #define CONFIG_MPC8569		1	/* MPC8569 specific */
17 #define CONFIG_MPC8569MDS	1	/* MPC8569MDS board specific */
18 
19 #define CONFIG_FSL_ELBC		1	/* Has Enhance localbus controller */
20 
21 #define CONFIG_SYS_SRIO
22 #define CONFIG_SRIO1			/* SRIO port 1 */
23 
24 #define CONFIG_PCIE1		1	/* PCIE controller */
25 #define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
26 #define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
27 #define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
28 #define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
29 #define CONFIG_QE			/* Enable QE */
30 #define CONFIG_ENV_OVERWRITE
31 #define CONFIG_FSL_LAW		1	/* Use common FSL init code */
32 
33 #ifndef __ASSEMBLY__
34 extern unsigned long get_clock_freq(void);
35 #endif
36 /* Replace a call to get_clock_freq (after it is implemented)*/
37 #define CONFIG_SYS_CLK_FREQ	66666666
38 #define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
39 
40 #ifdef CONFIG_ATM
41 #define CONFIG_PQ_MDS_PIB
42 #define CONFIG_PQ_MDS_PIB_ATM
43 #endif
44 
45 /*
46  * These can be toggled for performance analysis, otherwise use default.
47  */
48 #define CONFIG_L2_CACHE				/* toggle L2 cache	*/
49 #define CONFIG_BTB				/* toggle branch predition */
50 
51 #ifndef CONFIG_SYS_TEXT_BASE
52 #define CONFIG_SYS_TEXT_BASE	0xfff80000
53 #endif
54 
55 #ifndef CONFIG_SYS_MONITOR_BASE
56 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
57 #endif
58 
59 /*
60  * Only possible on E500 Version 2 or newer cores.
61  */
62 #define CONFIG_ENABLE_36BIT_PHYS	1
63 
64 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */
65 #define CONFIG_BOARD_EARLY_INIT_R	1
66 #define CONFIG_HWCONFIG
67 
68 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
69 #define CONFIG_SYS_MEMTEST_END		0x00400000
70 
71 /*
72  * Config the L2 Cache as L2 SRAM
73  */
74 #define CONFIG_SYS_INIT_L2_ADDR		0xf8f80000
75 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
76 #define CONFIG_SYS_L2_SIZE		(512 << 10)
77 #define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
78 
79 #define CONFIG_SYS_CCSRBAR		0xe0000000
80 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
81 
82 #if defined(CONFIG_NAND_SPL)
83 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
84 #endif
85 
86 /* DDR Setup */
87 #define CONFIG_SYS_FSL_DDR3
88 #undef CONFIG_FSL_DDR_INTERACTIVE
89 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
90 #define CONFIG_DDR_SPD
91 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
92 
93 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
94 
95 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
96 					/* DDR is system memory*/
97 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
98 
99 #define CONFIG_NUM_DDR_CONTROLLERS	1
100 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
101 #define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
102 
103 /* I2C addresses of SPD EEPROMs */
104 #define SPD_EEPROM_ADDRESS    0x51    /* CTLR 0 DIMM 0 */
105 
106 /* These are used when DDR doesn't use SPD.  */
107 #define CONFIG_SYS_SDRAM_SIZE           1024		/* DDR is 1024MB */
108 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
109 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
110 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
111 #define CONFIG_SYS_DDR_TIMING_0         0x00330004
112 #define CONFIG_SYS_DDR_TIMING_1         0x6F6B4644
113 #define CONFIG_SYS_DDR_TIMING_2         0x002888D0
114 #define CONFIG_SYS_DDR_SDRAM_CFG	0x47000000
115 #define CONFIG_SYS_DDR_SDRAM_CFG_2	0x04401040
116 #define CONFIG_SYS_DDR_SDRAM_MODE	0x40401521
117 #define CONFIG_SYS_DDR_SDRAM_MODE_2	0x8000C000
118 #define CONFIG_SYS_DDR_SDRAM_INTERVAL	0x03E00000
119 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
120 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x01000000
121 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
122 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
123 #define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
124 #define CONFIG_SYS_DDR_WRLVL_CNTL	0x0655A604
125 #define CONFIG_SYS_DDR_CDR_1		0x80040000
126 #define CONFIG_SYS_DDR_CDR_2		0x00000000
127 #define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
128 #define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
129 #define CONFIG_SYS_DDR_CONTROL          0xc7000000      /* Type = DDR3 */
130 #define CONFIG_SYS_DDR_CONTROL2         0x24400000
131 
132 #define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
133 #define CONFIG_SYS_DDR_ERR_DIS          0x00000000
134 #define CONFIG_SYS_DDR_SBE              0x00010000
135 
136 #undef CONFIG_CLOCKS_IN_MHZ
137 
138 /*
139  * Local Bus Definitions
140  */
141 
142 #define CONFIG_SYS_FLASH_BASE		0xfe000000	/* start of FLASH 32M */
143 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
144 
145 #define CONFIG_SYS_BCSR_BASE		0xf8000000
146 #define CONFIG_SYS_BCSR_BASE_PHYS	CONFIG_SYS_BCSR_BASE
147 
148 /*Chip select 0 - Flash*/
149 #define CONFIG_FLASH_BR_PRELIM		0xfe000801
150 #define	CONFIG_FLASH_OR_PRELIM		0xfe000ff7
151 
152 /*Chip select 1 - BCSR*/
153 #define CONFIG_SYS_BR1_PRELIM		0xf8000801
154 #define	CONFIG_SYS_OR1_PRELIM		0xffffe9f7
155 
156 /*Chip select 4 - PIB*/
157 #define CONFIG_SYS_BR4_PRELIM		0xf8008801
158 #define CONFIG_SYS_OR4_PRELIM		0xffffe9f7
159 
160 /*Chip select 5 - PIB*/
161 #define CONFIG_SYS_BR5_PRELIM		0xf8010801
162 #define CONFIG_SYS_OR5_PRELIM		0xffffe9f7
163 
164 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
165 #define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device */
166 #undef	CONFIG_SYS_FLASH_CHECKSUM
167 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
168 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
169 
170 #undef CONFIG_SYS_RAMBOOT
171 
172 #define CONFIG_FLASH_CFI_DRIVER
173 #define CONFIG_SYS_FLASH_CFI
174 #define CONFIG_SYS_FLASH_EMPTY_INFO
175 
176 /* Chip select 3 - NAND */
177 #ifndef CONFIG_NAND_SPL
178 #define CONFIG_SYS_NAND_BASE		0xFC000000
179 #else
180 #define CONFIG_SYS_NAND_BASE		0xFFF00000
181 #endif
182 
183 /* NAND boot: 4K NAND loader config */
184 #define CONFIG_SYS_NAND_SPL_SIZE	0x1000
185 #define CONFIG_SYS_NAND_U_BOOT_SIZE	((512 << 10) - 0x2000)
186 #define CONFIG_SYS_NAND_U_BOOT_DST	(CONFIG_SYS_INIT_L2_ADDR)
187 #define CONFIG_SYS_NAND_U_BOOT_START \
188 	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
189 #define CONFIG_SYS_NAND_U_BOOT_OFFS	(0)
190 #define CONFIG_SYS_NAND_U_BOOT_RELOC	(CONFIG_SYS_INIT_L2_END - 0x2000)
191 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP	((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
192 
193 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
194 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, }
195 #define CONFIG_SYS_MAX_NAND_DEVICE	1
196 #define CONFIG_CMD_NAND			1
197 #define CONFIG_NAND_FSL_ELBC		1
198 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
199 #define CONFIG_SYS_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE_PHYS \
200 				| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
201 				| BR_PS_8	     /* Port Size = 8 bit */ \
202 				| BR_MS_FCM	     /* MSEL = FCM */ \
203 				| BR_V)		     /* valid */
204 #define CONFIG_SYS_NAND_OR_PRELIM	(0xFFFC0000	     /* length 256K */ \
205 				| OR_FCM_CSCT \
206 				| OR_FCM_CST \
207 				| OR_FCM_CHT \
208 				| OR_FCM_SCY_1 \
209 				| OR_FCM_TRLX \
210 				| OR_FCM_EHTR)
211 
212 #define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM	/* NOR Base Address */
213 #define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM	/* NOR Options */
214 #define CONFIG_SYS_BR3_PRELIM	CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
215 #define CONFIG_SYS_OR3_PRELIM	CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
216 
217 #define CONFIG_SYS_LBC_LCRR	0x00000004	/* LB clock ratio reg */
218 #define CONFIG_SYS_LBC_LBCR	0x00040000	/* LB config reg */
219 #define CONFIG_SYS_LBC_LSRT	0x20000000	/* LB sdram refresh timer */
220 #define CONFIG_SYS_LBC_MRTPR	0x00000000	/* LB refresh timer prescal*/
221 
222 #define CONFIG_SYS_INIT_RAM_LOCK	1
223 #define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000  /* Initial RAM address */
224 #define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */
225 
226 #define CONFIG_SYS_GBL_DATA_OFFSET	\
227 			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
228 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
229 
230 #define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Mon */
231 #define CONFIG_SYS_MALLOC_LEN	(512 * 1024)	/* Reserved for malloc */
232 
233 /* Serial Port */
234 #define CONFIG_CONS_INDEX		1
235 #define CONFIG_SYS_NS16550_SERIAL
236 #define CONFIG_SYS_NS16550_REG_SIZE    1
237 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
238 #ifdef CONFIG_NAND_SPL
239 #define CONFIG_NS16550_MIN_FUNCTIONS
240 #endif
241 
242 #define CONFIG_SYS_BAUDRATE_TABLE  \
243 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
244 
245 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
246 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
247 
248 /*
249  * I2C
250  */
251 #define CONFIG_SYS_I2C
252 #define CONFIG_SYS_I2C_FSL
253 #define CONFIG_SYS_FSL_I2C_SPEED	400000
254 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
255 #define CONFIG_SYS_FSL_I2C2_SPEED	400000
256 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
257 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
258 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
259 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
260 
261 /*
262  * I2C2 EEPROM
263  */
264 #define CONFIG_ID_EEPROM
265 #ifdef CONFIG_ID_EEPROM
266 #define CONFIG_SYS_I2C_EEPROM_NXID
267 #endif
268 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
269 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
270 #define CONFIG_SYS_EEPROM_BUS_NUM       1
271 
272 #define PLPPAR1_I2C_BIT_MASK		0x0000000F
273 #define PLPPAR1_I2C2_VAL		0x00000000
274 #define PLPPAR1_ESDHC_VAL		0x0000000A
275 #define PLPDIR1_I2C_BIT_MASK		0x0000000F
276 #define PLPDIR1_I2C2_VAL		0x0000000F
277 #define PLPDIR1_ESDHC_VAL		0x00000006
278 #define PLPPAR1_UART0_BIT_MASK		0x00000fc0
279 #define PLPPAR1_ESDHC_4BITS_VAL		0x00000a80
280 #define PLPDIR1_UART0_BIT_MASK		0x00000fc0
281 #define PLPDIR1_ESDHC_4BITS_VAL		0x00000a80
282 
283 /*
284  * General PCI
285  * Memory Addresses are mapped 1-1. I/O is mapped from 0
286  */
287 #define CONFIG_SYS_PCIE1_NAME		"Slot"
288 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
289 #define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
290 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
291 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
292 #define CONFIG_SYS_PCIE1_IO_VIRT	0xe2800000
293 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
294 #define CONFIG_SYS_PCIE1_IO_PHYS	0xe2800000
295 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000	/* 8M */
296 
297 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xC0000000
298 #define CONFIG_SYS_SRIO1_MEM_BUS	0xC0000000
299 #define CONFIG_SYS_SRIO1_MEM_PHYS	CONFIG_SYS_SRIO1_MEM_BUS
300 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
301 
302 #ifdef CONFIG_QE
303 /*
304  * QE UEC ethernet configuration
305  */
306 #define CONFIG_SYS_UCC_RGMII_MODE	/* Set UCC work at RGMII by default */
307 #undef CONFIG_SYS_UCC_RMII_MODE		/* Set UCC work at RMII mode */
308 
309 #define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
310 #define CONFIG_UEC_ETH
311 #define CONFIG_ETHPRIME         "UEC0"
312 #define CONFIG_PHY_MODE_NEED_CHANGE
313 
314 #define CONFIG_UEC_ETH1         /* GETH1 */
315 #define CONFIG_HAS_ETH0
316 
317 #ifdef CONFIG_UEC_ETH1
318 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
319 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
320 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
321 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
322 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
323 #define CONFIG_SYS_UEC1_PHY_ADDR       7
324 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
325 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
326 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
327 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16	/* CLK16 for RMII */
328 #define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
329 #define CONFIG_SYS_UEC1_PHY_ADDR       8	/* 0x8 for RMII */
330 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
331 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
332 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
333 #endif /* CONFIG_UEC_ETH1 */
334 
335 #define CONFIG_UEC_ETH2         /* GETH2 */
336 #define CONFIG_HAS_ETH1
337 
338 #ifdef CONFIG_UEC_ETH2
339 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
340 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
341 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
342 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
343 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
344 #define CONFIG_SYS_UEC2_PHY_ADDR       1
345 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
346 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
347 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
348 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16	/* CLK 16 for RMII */
349 #define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
350 #define CONFIG_SYS_UEC2_PHY_ADDR       0x9	/* 0x9 for RMII */
351 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
352 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
353 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
354 #endif /* CONFIG_UEC_ETH2 */
355 
356 #define CONFIG_UEC_ETH3         /* GETH3 */
357 #define CONFIG_HAS_ETH2
358 
359 #ifdef CONFIG_UEC_ETH3
360 #define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
361 #define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
362 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
363 #define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
364 #define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
365 #define CONFIG_SYS_UEC3_PHY_ADDR       2
366 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
367 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
368 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
369 #define CONFIG_SYS_UEC3_TX_CLK		QE_CLK16 /* CLK_16 for RMII */
370 #define CONFIG_SYS_UEC3_ETH_TYPE	FAST_ETH
371 #define CONFIG_SYS_UEC3_PHY_ADDR	0xA     /* 0xA for RMII */
372 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
373 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
374 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
375 #endif /* CONFIG_UEC_ETH3 */
376 
377 #define CONFIG_UEC_ETH4         /* GETH4 */
378 #define CONFIG_HAS_ETH3
379 
380 #ifdef CONFIG_UEC_ETH4
381 #define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
382 #define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
383 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
384 #define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
385 #define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
386 #define CONFIG_SYS_UEC4_PHY_ADDR       3
387 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID
388 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
389 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
390 #define CONFIG_SYS_UEC4_TX_CLK		QE_CLK16 /* CLK16 for RMII */
391 #define CONFIG_SYS_UEC4_ETH_TYPE	FAST_ETH
392 #define CONFIG_SYS_UEC4_PHY_ADDR	0xB     /* 0xB for RMII */
393 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
394 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
395 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
396 #endif /* CONFIG_UEC_ETH4 */
397 
398 #undef CONFIG_UEC_ETH6         /* GETH6 */
399 #define CONFIG_HAS_ETH5
400 
401 #ifdef CONFIG_UEC_ETH6
402 #define CONFIG_SYS_UEC6_UCC_NUM        5       /* UCC6 */
403 #define CONFIG_SYS_UEC6_RX_CLK         QE_CLK_NONE
404 #define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
405 #define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
406 #define CONFIG_SYS_UEC6_PHY_ADDR       4
407 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
408 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
409 #endif /* CONFIG_UEC_ETH6 */
410 
411 #undef CONFIG_UEC_ETH8         /* GETH8 */
412 #define CONFIG_HAS_ETH7
413 
414 #ifdef CONFIG_UEC_ETH8
415 #define CONFIG_SYS_UEC8_UCC_NUM        7       /* UCC8 */
416 #define CONFIG_SYS_UEC8_RX_CLK         QE_CLK_NONE
417 #define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
418 #define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
419 #define CONFIG_SYS_UEC8_PHY_ADDR       6
420 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
421 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
422 #endif /* CONFIG_UEC_ETH8 */
423 
424 #endif /* CONFIG_QE */
425 
426 #if defined(CONFIG_PCI)
427 #undef CONFIG_EEPRO100
428 #undef CONFIG_TULIP
429 
430 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
431 
432 #endif	/* CONFIG_PCI */
433 
434 /*
435  * Environment
436  */
437 #if defined(CONFIG_SYS_RAMBOOT)
438 #else
439 #define CONFIG_ENV_IS_IN_FLASH	1
440 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
441 #define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
442 #define CONFIG_ENV_SIZE		0x2000
443 #endif
444 
445 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
446 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
447 
448 /* QE microcode/firmware address */
449 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
450 #define CONFIG_SYS_QE_FW_ADDR	0xfff00000
451 
452 /*
453  * BOOTP options
454  */
455 #define CONFIG_BOOTP_BOOTFILESIZE
456 #define CONFIG_BOOTP_BOOTPATH
457 #define CONFIG_BOOTP_GATEWAY
458 #define CONFIG_BOOTP_HOSTNAME
459 
460 /*
461  * Command line configuration.
462  */
463 #define CONFIG_CMD_IRQ
464 #define CONFIG_CMD_REGINFO
465 
466 #if defined(CONFIG_PCI)
467     #define CONFIG_CMD_PCI
468 #endif
469 
470 #undef CONFIG_WATCHDOG			/* watchdog disabled */
471 
472 #define CONFIG_MMC     1
473 
474 #ifdef CONFIG_MMC
475 #define CONFIG_FSL_ESDHC
476 #define CONFIG_FSL_ESDHC_PIN_MUX
477 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
478 #define CONFIG_GENERIC_MMC
479 #define CONFIG_DOS_PARTITION
480 #endif
481 
482 /*
483  * Miscellaneous configurable options
484  */
485 #define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
486 #define CONFIG_CMDLINE_EDITING			/* Command-line editing */
487 #define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
488 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
489 #if defined(CONFIG_CMD_KGDB)
490 #define CONFIG_SYS_CBSIZE	2048		/* Console I/O Buffer Size */
491 #else
492 #define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
493 #endif
494 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
495 						/* Print Buffer Size */
496 #define CONFIG_SYS_MAXARGS	32		/* max number of command args */
497 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
498 						/* Boot Argument Buffer Size */
499 
500 /*
501  * For booting Linux, the board info and command line data
502  * have to be in the first 64 MB of memory, since this is
503  * the maximum mapped by the Linux kernel during initialization.
504  */
505 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20) /* Initial Memory map for Linux*/
506 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
507 
508 #if defined(CONFIG_CMD_KGDB)
509 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
510 #endif
511 
512 /*
513  * Environment Configuration
514  */
515 #define CONFIG_HOSTNAME mpc8569mds
516 #define CONFIG_ROOTPATH  "/nfsroot"
517 #define CONFIG_BOOTFILE  "your.uImage"
518 
519 #define CONFIG_SERVERIP  192.168.1.1
520 #define CONFIG_GATEWAYIP 192.168.1.1
521 #define CONFIG_NETMASK   255.255.255.0
522 
523 #define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/
524 
525 #undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
526 
527 #define CONFIG_BAUDRATE	115200
528 
529 #define	CONFIG_EXTRA_ENV_SETTINGS					\
530 	"netdev=eth0\0"							\
531 	"consoledev=ttyS0\0"						\
532 	"ramdiskaddr=600000\0"						\
533 	"ramdiskfile=your.ramdisk.u-boot\0"				\
534 	"fdtaddr=400000\0"						\
535 	"fdtfile=your.fdt.dtb\0"					\
536 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
537 	"nfsroot=$serverip:$rootpath "					\
538 	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
539 	"console=$consoledev,$baudrate $othbootargs\0"			\
540 	"ramargs=setenv bootargs root=/dev/ram rw "			\
541 	"console=$consoledev,$baudrate $othbootargs\0"			\
542 
543 #define CONFIG_NFSBOOTCOMMAND						\
544 	"run nfsargs;"							\
545 	"tftp $loadaddr $bootfile;"					\
546 	"tftp $fdtaddr $fdtfile;"					\
547 	"bootm $loadaddr - $fdtaddr"
548 
549 #define CONFIG_RAMBOOTCOMMAND						\
550 	"run ramargs;"							\
551 	"tftp $ramdiskaddr $ramdiskfile;"				\
552 	"tftp $loadaddr $bootfile;"					\
553 	"bootm $loadaddr $ramdiskaddr"
554 
555 #define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
556 
557 #endif	/* __CONFIG_H */
558