1 /* 2 * Copyright (C) 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8569mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8569 1 /* MPC8569 specific */ 34 #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ 35 36 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ 37 38 #define CONFIG_PCI 1 /* Disable PCI/PCIE */ 39 #define CONFIG_PCIE1 1 /* PCIE controller */ 40 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 41 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 42 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 43 #define CONFIG_QE /* Enable QE */ 44 #define CONFIG_ENV_OVERWRITE 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 #ifndef __ASSEMBLY__ 48 extern unsigned long get_clock_freq(void); 49 #endif 50 /* Replace a call to get_clock_freq (after it is implemented)*/ 51 #define CONFIG_SYS_CLK_FREQ 66666666 52 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 53 54 #ifdef CONFIG_MK_ATM 55 #define CONFIG_PQ_MDS_PIB 56 #define CONFIG_PQ_MDS_PIB_ATM 57 #endif 58 59 /* 60 * These can be toggled for performance analysis, otherwise use default. 61 */ 62 #define CONFIG_L2_CACHE /* toggle L2 cache */ 63 #define CONFIG_BTB /* toggle branch predition */ 64 65 #ifdef CONFIG_MK_NAND 66 #define CONFIG_NAND_U_BOOT 1 67 #define CONFIG_RAMBOOT_NAND 1 68 #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 69 #endif 70 71 /* 72 * Only possible on E500 Version 2 or newer cores. 73 */ 74 #define CONFIG_ENABLE_36BIT_PHYS 1 75 76 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 77 #define CONFIG_HWCONFIG 78 79 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 80 #define CONFIG_SYS_MEMTEST_END 0x00400000 81 82 /* 83 * Config the L2 Cache as L2 SRAM 84 */ 85 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 86 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 87 #define CONFIG_SYS_L2_SIZE (512 << 10) 88 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 89 90 /* 91 * Base addresses -- Note these are effective addresses where the 92 * actual resources get mapped (not physical addresses) 93 */ 94 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 95 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 96 /* physical addr of CCSRBAR */ 97 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 98 /* PQII uses CONFIG_SYS_IMMR */ 99 100 #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) 101 #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR 102 #else 103 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 104 #endif 105 106 /* DDR Setup */ 107 #define CONFIG_FSL_DDR3 108 #undef CONFIG_FSL_DDR_INTERACTIVE 109 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 110 #define CONFIG_DDR_SPD 111 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 112 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 113 114 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 115 116 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 117 /* DDR is system memory*/ 118 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 119 120 #define CONFIG_NUM_DDR_CONTROLLERS 1 121 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 122 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 123 124 /* I2C addresses of SPD EEPROMs */ 125 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 126 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 127 128 /* These are used when DDR doesn't use SPD. */ 129 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 130 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 131 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 132 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 133 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 134 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 135 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 136 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 137 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 138 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 139 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 140 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 141 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 142 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 143 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 144 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 145 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 146 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 147 #define CONFIG_SYS_DDR_CDR_1 0x80040000 148 #define CONFIG_SYS_DDR_CDR_2 0x00000000 149 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 150 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 151 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 152 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 153 154 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 155 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 156 #define CONFIG_SYS_DDR_SBE 0x00010000 157 158 #undef CONFIG_CLOCKS_IN_MHZ 159 160 /* 161 * Local Bus Definitions 162 */ 163 164 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 165 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 166 167 #define CONFIG_SYS_BCSR_BASE 0xf8000000 168 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 169 170 /*Chip select 0 - Flash*/ 171 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 172 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 173 174 /*Chip select 1 - BCSR*/ 175 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 176 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 177 178 /*Chip select 4 - PIB*/ 179 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 180 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 181 182 /*Chip select 5 - PIB*/ 183 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 184 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 185 186 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 187 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 188 #undef CONFIG_SYS_FLASH_CHECKSUM 189 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 190 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 191 192 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 193 194 #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) 195 #define CONFIG_SYS_RAMBOOT 196 #else 197 #undef CONFIG_SYS_RAMBOOT 198 #endif 199 200 #define CONFIG_FLASH_CFI_DRIVER 201 #define CONFIG_SYS_FLASH_CFI 202 #define CONFIG_SYS_FLASH_EMPTY_INFO 203 204 /* Chip select 3 - NAND */ 205 #ifndef CONFIG_NAND_SPL 206 #define CONFIG_SYS_NAND_BASE 0xFC000000 207 #else 208 #define CONFIG_SYS_NAND_BASE 0xFFF00000 209 #endif 210 211 /* NAND boot: 4K NAND loader config */ 212 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 213 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 214 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 215 #define CONFIG_SYS_NAND_U_BOOT_START \ 216 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 217 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 218 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 219 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 220 221 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 222 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 223 #define CONFIG_SYS_MAX_NAND_DEVICE 1 224 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 225 #define CONFIG_CMD_NAND 1 226 #define CONFIG_NAND_FSL_ELBC 1 227 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 228 #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 229 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 230 | BR_PS_8 /* Port Size = 8 bit */ \ 231 | BR_MS_FCM /* MSEL = FCM */ \ 232 | BR_V) /* valid */ 233 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 234 | OR_FCM_CSCT \ 235 | OR_FCM_CST \ 236 | OR_FCM_CHT \ 237 | OR_FCM_SCY_1 \ 238 | OR_FCM_TRLX \ 239 | OR_FCM_EHTR) 240 241 #ifdef CONFIG_RAMBOOT_NAND 242 #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 243 #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 244 #define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 245 #define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 246 #else 247 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 248 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 249 #define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 250 #define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 251 #endif 252 253 /* 254 * SDRAM on the LocalBus 255 */ 256 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 257 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 258 259 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 260 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 261 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 262 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 263 264 #define CONFIG_SYS_INIT_RAM_LOCK 1 265 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 266 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 267 268 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 269 #define CONFIG_SYS_GBL_DATA_OFFSET \ 270 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 271 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 272 273 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 274 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 275 276 /* Serial Port */ 277 #define CONFIG_CONS_INDEX 1 278 #define CONFIG_SERIAL_MULTI 1 279 #define CONFIG_SYS_NS16550 280 #define CONFIG_SYS_NS16550_SERIAL 281 #define CONFIG_SYS_NS16550_REG_SIZE 1 282 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 283 #ifdef CONFIG_NAND_SPL 284 #define CONFIG_NS16550_MIN_FUNCTIONS 285 #endif 286 287 #define CONFIG_SYS_BAUDRATE_TABLE \ 288 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 289 290 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 291 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 292 293 /* Use the HUSH parser*/ 294 #define CONFIG_SYS_HUSH_PARSER 295 #ifdef CONFIG_SYS_HUSH_PARSER 296 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 297 #endif 298 299 /* pass open firmware flat tree */ 300 #define CONFIG_OF_LIBFDT 1 301 #define CONFIG_OF_BOARD_SETUP 1 302 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 303 304 /* 305 * I2C 306 */ 307 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 308 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 309 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 310 #define CONFIG_I2C_MULTI_BUS 311 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 312 #define CONFIG_SYS_I2C_SLAVE 0x7F 313 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 314 #define CONFIG_SYS_I2C_OFFSET 0x3000 315 #define CONFIG_SYS_I2C2_OFFSET 0x3100 316 317 /* 318 * I2C2 EEPROM 319 */ 320 #define CONFIG_ID_EEPROM 321 #ifdef CONFIG_ID_EEPROM 322 #define CONFIG_SYS_I2C_EEPROM_NXID 323 #endif 324 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 325 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 326 #define CONFIG_SYS_EEPROM_BUS_NUM 1 327 328 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 329 #define PLPPAR1_I2C2_VAL 0x00000000 330 #define PLPPAR1_ESDHC_VAL 0x0000000A 331 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 332 #define PLPDIR1_I2C2_VAL 0x0000000F 333 #define PLPDIR1_ESDHC_VAL 0x00000006 334 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 335 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 336 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 337 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 338 339 /* 340 * General PCI 341 * Memory Addresses are mapped 1-1. I/O is mapped from 0 342 */ 343 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 344 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 345 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 346 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 347 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 348 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 349 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 350 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 351 352 #define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 353 #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 354 #define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 355 356 #ifdef CONFIG_QE 357 /* 358 * QE UEC ethernet configuration 359 */ 360 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 361 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 362 363 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 364 #define CONFIG_UEC_ETH 365 #define CONFIG_ETHPRIME "UEC0" 366 #define CONFIG_PHY_MODE_NEED_CHANGE 367 368 #define CONFIG_UEC_ETH1 /* GETH1 */ 369 #define CONFIG_HAS_ETH0 370 371 #ifdef CONFIG_UEC_ETH1 372 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 373 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 374 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 375 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 376 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 377 #define CONFIG_SYS_UEC1_PHY_ADDR 7 378 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID 379 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 380 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 381 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 382 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 383 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 384 #define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII 385 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 386 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 387 #endif /* CONFIG_UEC_ETH1 */ 388 389 #define CONFIG_UEC_ETH2 /* GETH2 */ 390 #define CONFIG_HAS_ETH1 391 392 #ifdef CONFIG_UEC_ETH2 393 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 394 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 395 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 396 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 397 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 398 #define CONFIG_SYS_UEC2_PHY_ADDR 1 399 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID 400 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 401 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 402 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 403 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 404 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 405 #define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII 406 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 407 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 408 #endif /* CONFIG_UEC_ETH2 */ 409 410 #define CONFIG_UEC_ETH3 /* GETH3 */ 411 #define CONFIG_HAS_ETH2 412 413 #ifdef CONFIG_UEC_ETH3 414 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 415 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 416 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 417 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 418 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 419 #define CONFIG_SYS_UEC3_PHY_ADDR 2 420 #define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID 421 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 422 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 423 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 424 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 425 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 426 #define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII 427 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 428 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 429 #endif /* CONFIG_UEC_ETH3 */ 430 431 #define CONFIG_UEC_ETH4 /* GETH4 */ 432 #define CONFIG_HAS_ETH3 433 434 #ifdef CONFIG_UEC_ETH4 435 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 436 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 437 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 438 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 439 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 440 #define CONFIG_SYS_UEC4_PHY_ADDR 3 441 #define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID 442 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 443 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 444 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 445 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 446 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 447 #define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII 448 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 449 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 450 #endif /* CONFIG_UEC_ETH4 */ 451 452 #undef CONFIG_UEC_ETH6 /* GETH6 */ 453 #define CONFIG_HAS_ETH5 454 455 #ifdef CONFIG_UEC_ETH6 456 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 457 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 458 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 459 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 460 #define CONFIG_SYS_UEC6_PHY_ADDR 4 461 #define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII 462 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 463 #endif /* CONFIG_UEC_ETH6 */ 464 465 #undef CONFIG_UEC_ETH8 /* GETH8 */ 466 #define CONFIG_HAS_ETH7 467 468 #ifdef CONFIG_UEC_ETH8 469 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 470 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 471 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 472 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 473 #define CONFIG_SYS_UEC8_PHY_ADDR 6 474 #define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII 475 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 476 #endif /* CONFIG_UEC_ETH8 */ 477 478 #endif /* CONFIG_QE */ 479 480 #if defined(CONFIG_PCI) 481 482 #define CONFIG_NET_MULTI 483 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 484 485 #undef CONFIG_EEPRO100 486 #undef CONFIG_TULIP 487 488 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 489 490 #endif /* CONFIG_PCI */ 491 492 #ifndef CONFIG_NET_MULTI 493 #define CONFIG_NET_MULTI 1 494 #endif 495 496 /* 497 * Environment 498 */ 499 #if defined(CONFIG_SYS_RAMBOOT) 500 #if defined(CONFIG_RAMBOOT_NAND) 501 #define CONFIG_ENV_IS_IN_NAND 1 502 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 503 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 504 #endif 505 #else 506 #define CONFIG_ENV_IS_IN_FLASH 1 507 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 508 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ 509 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 510 #endif 511 512 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 513 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 514 515 /* QE microcode/firmware address */ 516 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 517 518 /* 519 * BOOTP options 520 */ 521 #define CONFIG_BOOTP_BOOTFILESIZE 522 #define CONFIG_BOOTP_BOOTPATH 523 #define CONFIG_BOOTP_GATEWAY 524 #define CONFIG_BOOTP_HOSTNAME 525 526 527 /* 528 * Command line configuration. 529 */ 530 #include <config_cmd_default.h> 531 532 #define CONFIG_CMD_PING 533 #define CONFIG_CMD_I2C 534 #define CONFIG_CMD_MII 535 #define CONFIG_CMD_ELF 536 #define CONFIG_CMD_IRQ 537 #define CONFIG_CMD_SETEXPR 538 #define CONFIG_CMD_REGINFO 539 540 #if defined(CONFIG_PCI) 541 #define CONFIG_CMD_PCI 542 #endif 543 544 545 #undef CONFIG_WATCHDOG /* watchdog disabled */ 546 547 #define CONFIG_MMC 1 548 549 #ifdef CONFIG_MMC 550 #define CONFIG_FSL_ESDHC 551 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 552 #define CONFIG_CMD_MMC 553 #define CONFIG_GENERIC_MMC 554 #define CONFIG_CMD_EXT2 555 #define CONFIG_CMD_FAT 556 #define CONFIG_DOS_PARTITION 557 #endif 558 559 /* 560 * Miscellaneous configurable options 561 */ 562 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 563 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 564 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 565 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 566 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 567 #if defined(CONFIG_CMD_KGDB) 568 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 569 #else 570 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 571 #endif 572 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 573 /* Print Buffer Size */ 574 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 575 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 576 /* Boot Argument Buffer Size */ 577 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 578 579 /* 580 * For booting Linux, the board info and command line data 581 * have to be in the first 16 MB of memory, since this is 582 * the maximum mapped by the Linux kernel during initialization. 583 */ 584 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) 585 /* Initial Memory map for Linux*/ 586 587 /* 588 * Internal Definitions 589 * 590 * Boot Flags 591 */ 592 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 593 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 594 595 #if defined(CONFIG_CMD_KGDB) 596 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 597 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 598 #endif 599 600 /* 601 * Environment Configuration 602 */ 603 #define CONFIG_HOSTNAME mpc8569mds 604 #define CONFIG_ROOTPATH /nfsroot 605 #define CONFIG_BOOTFILE your.uImage 606 607 #define CONFIG_SERVERIP 192.168.1.1 608 #define CONFIG_GATEWAYIP 192.168.1.1 609 #define CONFIG_NETMASK 255.255.255.0 610 611 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 612 613 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 614 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 615 616 #define CONFIG_BAUDRATE 115200 617 618 #define CONFIG_EXTRA_ENV_SETTINGS \ 619 "netdev=eth0\0" \ 620 "consoledev=ttyS0\0" \ 621 "ramdiskaddr=600000\0" \ 622 "ramdiskfile=your.ramdisk.u-boot\0" \ 623 "fdtaddr=400000\0" \ 624 "fdtfile=your.fdt.dtb\0" \ 625 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 626 "nfsroot=$serverip:$rootpath " \ 627 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 628 "console=$consoledev,$baudrate $othbootargs\0" \ 629 "ramargs=setenv bootargs root=/dev/ram rw " \ 630 "console=$consoledev,$baudrate $othbootargs\0" \ 631 632 #define CONFIG_NFSBOOTCOMMAND \ 633 "run nfsargs;" \ 634 "tftp $loadaddr $bootfile;" \ 635 "tftp $fdtaddr $fdtfile;" \ 636 "bootm $loadaddr - $fdtaddr" 637 638 #define CONFIG_RAMBOOTCOMMAND \ 639 "run ramargs;" \ 640 "tftp $ramdiskaddr $ramdiskfile;" \ 641 "tftp $loadaddr $bootfile;" \ 642 "bootm $loadaddr $ramdiskaddr" 643 644 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 645 646 #endif /* __CONFIG_H */ 647