1 /* 2 * Copyright (C) 2009 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8569mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8569 1 /* MPC8569 specific */ 34 #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ 35 36 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ 37 38 #define CONFIG_PCI 1 /* Disable PCI/PCIE */ 39 #define CONFIG_PCIE1 1 /* PCIE controller */ 40 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 41 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 42 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 43 #define CONFIG_QE /* Enable QE */ 44 #define CONFIG_ENV_OVERWRITE 45 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 46 47 /* 48 * When initializing flash, if we cannot find the manufacturer ID, 49 * assume this is the AMD flash associated with the MDS board. 50 * This allows booting from a promjet. 51 */ 52 #define CONFIG_ASSUME_AMD_FLASH 53 54 #ifndef __ASSEMBLY__ 55 extern unsigned long get_clock_freq(void); 56 #endif 57 /* Replace a call to get_clock_freq (after it is implemented)*/ 58 #define CONFIG_SYS_CLK_FREQ 66666666 59 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 60 61 /* 62 * These can be toggled for performance analysis, otherwise use default. 63 */ 64 #define CONFIG_L2_CACHE /* toggle L2 cache */ 65 #define CONFIG_BTB /* toggle branch predition */ 66 67 /* 68 * Only possible on E500 Version 2 or newer cores. 69 */ 70 #define CONFIG_ENABLE_36BIT_PHYS 1 71 72 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 73 #define CONFIG_HWCONFIG 74 75 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 76 #define CONFIG_SYS_MEMTEST_END 0x00400000 77 78 /* 79 * Base addresses -- Note these are effective addresses where the 80 * actual resources get mapped (not physical addresses) 81 */ 82 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 83 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ 84 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR 85 /* physical addr of CCSRBAR */ 86 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 87 /* PQII uses CONFIG_SYS_IMMR */ 88 89 #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) 90 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) 91 92 /* DDR Setup */ 93 #define CONFIG_FSL_DDR3 94 #undef CONFIG_FSL_DDR_INTERACTIVE 95 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 96 #define CONFIG_DDR_SPD 97 #define CONFIG_DDR_DLL /* possible DLL fix needed */ 98 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 99 100 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 101 102 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 103 /* DDR is system memory*/ 104 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 105 106 #define CONFIG_NUM_DDR_CONTROLLERS 1 107 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 108 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 109 110 /* I2C addresses of SPD EEPROMs */ 111 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 112 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 113 114 /* These are used when DDR doesn't use SPD. */ 115 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 116 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 117 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 118 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 119 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 120 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 121 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 122 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 123 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 124 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 125 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 126 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 127 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 128 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 129 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 130 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 131 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 132 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 133 #define CONFIG_SYS_DDR_CDR_1 0x80040000 134 #define CONFIG_SYS_DDR_CDR_2 0x00000000 135 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 136 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 137 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 138 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 139 140 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 141 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 142 #define CONFIG_SYS_DDR_SBE 0x00010000 143 144 #undef CONFIG_CLOCKS_IN_MHZ 145 146 /* 147 * Local Bus Definitions 148 */ 149 150 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 151 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 152 153 #define CONFIG_SYS_BCSR_BASE 0xf8000000 154 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 155 156 /*Chip select 0 - Flash*/ 157 #define CONFIG_SYS_BR0_PRELIM 0xfe000801 158 #define CONFIG_SYS_OR0_PRELIM 0xfe000ff7 159 160 /*Chip select 1 - BCSR*/ 161 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 162 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 163 164 /*Chip select 4 - PIB*/ 165 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 166 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 167 168 /*Chip select 5 - PIB*/ 169 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 170 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 171 172 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 173 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 174 #undef CONFIG_SYS_FLASH_CHECKSUM 175 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 176 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 177 178 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 179 180 #define CONFIG_FLASH_CFI_DRIVER 181 #define CONFIG_SYS_FLASH_CFI 182 #define CONFIG_SYS_FLASH_EMPTY_INFO 183 184 /* Chip select 3 - NAND */ 185 #define CONFIG_SYS_NAND_BASE 0xFC000000 186 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 187 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 188 #define CONFIG_SYS_MAX_NAND_DEVICE 1 189 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 190 #define CONFIG_CMD_NAND 1 191 #define CONFIG_NAND_FSL_ELBC 1 192 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 193 #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 194 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 195 | BR_PS_8 /* Port Size = 8 bit */ \ 196 | BR_MS_FCM /* MSEL = FCM */ \ 197 | BR_V) /* valid */ 198 #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 199 | OR_FCM_CSCT \ 200 | OR_FCM_CST \ 201 | OR_FCM_CHT \ 202 | OR_FCM_SCY_1 \ 203 | OR_FCM_TRLX \ 204 | OR_FCM_EHTR) 205 #define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ 206 #define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ 207 208 /* 209 * SDRAM on the LocalBus 210 */ 211 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 212 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 213 214 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 215 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 216 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 217 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 218 219 #define CONFIG_SYS_INIT_RAM_LOCK 1 220 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 221 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 222 223 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 224 #define CONFIG_SYS_GBL_DATA_OFFSET \ 225 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 226 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 227 228 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 229 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 230 231 /* Serial Port */ 232 #define CONFIG_CONS_INDEX 1 233 #define CONFIG_SERIAL_MULTI 1 234 #undef CONFIG_SERIAL_SOFTWARE_FIFO 235 #define CONFIG_SYS_NS16550 236 #define CONFIG_SYS_NS16550_SERIAL 237 #define CONFIG_SYS_NS16550_REG_SIZE 1 238 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 239 240 #define CONFIG_SYS_BAUDRATE_TABLE \ 241 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 242 243 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 244 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 245 246 /* Use the HUSH parser*/ 247 #define CONFIG_SYS_HUSH_PARSER 248 #ifdef CONFIG_SYS_HUSH_PARSER 249 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 250 #endif 251 252 /* pass open firmware flat tree */ 253 #define CONFIG_OF_LIBFDT 1 254 #define CONFIG_OF_BOARD_SETUP 1 255 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 256 257 #define CONFIG_SYS_64BIT_VSPRINTF 1 258 #define CONFIG_SYS_64BIT_STRTOUL 1 259 260 /* 261 * I2C 262 */ 263 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 264 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 265 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 266 #define CONFIG_I2C_MULTI_BUS 267 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 268 #define CONFIG_SYS_I2C_SLAVE 0x7F 269 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 270 #define CONFIG_SYS_I2C_OFFSET 0x3000 271 #define CONFIG_SYS_I2C2_OFFSET 0x3100 272 273 /* 274 * I2C2 EEPROM 275 */ 276 #define CONFIG_ID_EEPROM 277 #ifdef CONFIG_ID_EEPROM 278 #define CONFIG_SYS_I2C_EEPROM_NXID 279 #endif 280 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 281 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 282 #define CONFIG_SYS_EEPROM_BUS_NUM 1 283 284 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 285 #define PLPPAR1_I2C2_VAL 0x00000000 286 #define PLPPAR1_ESDHC_VAL 0x0000000A 287 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 288 #define PLPDIR1_I2C2_VAL 0x0000000F 289 #define PLPDIR1_ESDHC_VAL 0x00000006 290 291 /* 292 * General PCI 293 * Memory Addresses are mapped 1-1. I/O is mapped from 0 294 */ 295 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 296 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 297 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 298 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 299 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 300 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 301 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 302 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 303 304 #define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 305 #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 306 #define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 307 308 #ifdef CONFIG_QE 309 /* 310 * QE UEC ethernet configuration 311 */ 312 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 313 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 314 315 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 316 #define CONFIG_UEC_ETH 317 #define CONFIG_ETHPRIME "FSL UEC0" 318 #define CONFIG_PHY_MODE_NEED_CHANGE 319 320 #define CONFIG_UEC_ETH1 /* GETH1 */ 321 #define CONFIG_HAS_ETH0 322 323 #ifdef CONFIG_UEC_ETH1 324 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 325 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 326 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 327 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 328 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 329 #define CONFIG_SYS_UEC1_PHY_ADDR 7 330 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID 331 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 332 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 333 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 334 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 335 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII 336 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 337 #endif /* CONFIG_UEC_ETH1 */ 338 339 #define CONFIG_UEC_ETH2 /* GETH2 */ 340 #define CONFIG_HAS_ETH1 341 342 #ifdef CONFIG_UEC_ETH2 343 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 344 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 345 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 346 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 347 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 348 #define CONFIG_SYS_UEC2_PHY_ADDR 1 349 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID 350 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 351 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 352 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 353 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 354 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII 355 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 356 #endif /* CONFIG_UEC_ETH2 */ 357 358 #define CONFIG_UEC_ETH3 /* GETH3 */ 359 #define CONFIG_HAS_ETH2 360 361 #ifdef CONFIG_UEC_ETH3 362 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 363 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 364 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 365 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 366 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 367 #define CONFIG_SYS_UEC3_PHY_ADDR 2 368 #define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID 369 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 370 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 371 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 372 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 373 #define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII 374 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 375 #endif /* CONFIG_UEC_ETH3 */ 376 377 #define CONFIG_UEC_ETH4 /* GETH4 */ 378 #define CONFIG_HAS_ETH3 379 380 #ifdef CONFIG_UEC_ETH4 381 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 382 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 383 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 384 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 385 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 386 #define CONFIG_SYS_UEC4_PHY_ADDR 3 387 #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID 388 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 389 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 390 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 391 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 392 #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII 393 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 394 #endif /* CONFIG_UEC_ETH4 */ 395 396 #undef CONFIG_UEC_ETH6 /* GETH6 */ 397 #define CONFIG_HAS_ETH5 398 399 #ifdef CONFIG_UEC_ETH6 400 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 401 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 402 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 403 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 404 #define CONFIG_SYS_UEC6_PHY_ADDR 4 405 #define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII 406 #endif /* CONFIG_UEC_ETH6 */ 407 408 #undef CONFIG_UEC_ETH8 /* GETH8 */ 409 #define CONFIG_HAS_ETH7 410 411 #ifdef CONFIG_UEC_ETH8 412 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 413 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 414 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 415 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 416 #define CONFIG_SYS_UEC8_PHY_ADDR 6 417 #define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII 418 #endif /* CONFIG_UEC_ETH8 */ 419 420 #endif /* CONFIG_QE */ 421 422 #if defined(CONFIG_PCI) 423 424 #define CONFIG_NET_MULTI 425 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 426 427 #undef CONFIG_EEPRO100 428 #undef CONFIG_TULIP 429 430 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 431 432 #endif /* CONFIG_PCI */ 433 434 #ifndef CONFIG_NET_MULTI 435 #define CONFIG_NET_MULTI 1 436 #endif 437 438 /* 439 * Environment 440 */ 441 #define CONFIG_ENV_IS_IN_FLASH 1 442 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 443 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ 444 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 445 446 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 447 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 448 449 /* QE microcode/firmware address */ 450 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 451 452 /* 453 * BOOTP options 454 */ 455 #define CONFIG_BOOTP_BOOTFILESIZE 456 #define CONFIG_BOOTP_BOOTPATH 457 #define CONFIG_BOOTP_GATEWAY 458 #define CONFIG_BOOTP_HOSTNAME 459 460 461 /* 462 * Command line configuration. 463 */ 464 #include <config_cmd_default.h> 465 466 #define CONFIG_CMD_PING 467 #define CONFIG_CMD_I2C 468 #define CONFIG_CMD_MII 469 #define CONFIG_CMD_ELF 470 #define CONFIG_CMD_IRQ 471 #define CONFIG_CMD_SETEXPR 472 473 #if defined(CONFIG_PCI) 474 #define CONFIG_CMD_PCI 475 #endif 476 477 478 #undef CONFIG_WATCHDOG /* watchdog disabled */ 479 480 #define CONFIG_MMC 1 481 482 #ifdef CONFIG_MMC 483 #define CONFIG_FSL_ESDHC 484 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 485 #define CONFIG_CMD_MMC 486 #define CONFIG_GENERIC_MMC 487 #define CONFIG_CMD_EXT2 488 #define CONFIG_CMD_FAT 489 #define CONFIG_DOS_PARTITION 490 #endif 491 492 /* 493 * Miscellaneous configurable options 494 */ 495 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 496 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 497 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 498 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 499 #if defined(CONFIG_CMD_KGDB) 500 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 501 #else 502 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 503 #endif 504 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 505 /* Print Buffer Size */ 506 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 507 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 508 /* Boot Argument Buffer Size */ 509 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 510 511 /* 512 * For booting Linux, the board info and command line data 513 * have to be in the first 16 MB of memory, since this is 514 * the maximum mapped by the Linux kernel during initialization. 515 */ 516 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) 517 /* Initial Memory map for Linux*/ 518 519 /* 520 * Internal Definitions 521 * 522 * Boot Flags 523 */ 524 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 525 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 526 527 #if defined(CONFIG_CMD_KGDB) 528 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 529 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 530 #endif 531 532 /* 533 * Environment Configuration 534 */ 535 #define CONFIG_HOSTNAME mpc8569mds 536 #define CONFIG_ROOTPATH /nfsroot 537 #define CONFIG_BOOTFILE your.uImage 538 539 #define CONFIG_SERVERIP 192.168.1.1 540 #define CONFIG_GATEWAYIP 192.168.1.1 541 #define CONFIG_NETMASK 255.255.255.0 542 543 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 544 545 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 546 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 547 548 #define CONFIG_BAUDRATE 115200 549 550 #define CONFIG_EXTRA_ENV_SETTINGS \ 551 "netdev=eth0\0" \ 552 "consoledev=ttyS0\0" \ 553 "ramdiskaddr=600000\0" \ 554 "ramdiskfile=your.ramdisk.u-boot\0" \ 555 "fdtaddr=400000\0" \ 556 "fdtfile=your.fdt.dtb\0" \ 557 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 558 "nfsroot=$serverip:$rootpath " \ 559 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 560 "console=$consoledev,$baudrate $othbootargs\0" \ 561 "ramargs=setenv bootargs root=/dev/ram rw " \ 562 "console=$consoledev,$baudrate $othbootargs\0" \ 563 564 #define CONFIG_NFSBOOTCOMMAND \ 565 "run nfsargs;" \ 566 "tftp $loadaddr $bootfile;" \ 567 "tftp $fdtaddr $fdtfile;" \ 568 "bootm $loadaddr - $fdtaddr" 569 570 #define CONFIG_RAMBOOTCOMMAND \ 571 "run ramargs;" \ 572 "tftp $ramdiskaddr $ramdiskfile;" \ 573 "tftp $loadaddr $bootfile;" \ 574 "bootm $loadaddr $ramdiskaddr" 575 576 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 577 578 #endif /* __CONFIG_H */ 579