1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * mpc8569mds board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 /* High Level Configuration Options */ 30 #define CONFIG_BOOKE 1 /* BOOKE */ 31 #define CONFIG_E500 1 /* BOOKE e500 family */ 32 #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ 33 #define CONFIG_MPC8569 1 /* MPC8569 specific */ 34 #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ 35 36 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ 37 38 #define CONFIG_SYS_SRIO 39 #define CONFIG_SRIO1 /* SRIO port 1 */ 40 41 #define CONFIG_PCI 1 /* Disable PCI/PCIE */ 42 #define CONFIG_PCIE1 1 /* PCIE controller */ 43 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 44 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 45 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 46 #define CONFIG_QE /* Enable QE */ 47 #define CONFIG_ENV_OVERWRITE 48 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 49 50 #ifndef __ASSEMBLY__ 51 extern unsigned long get_clock_freq(void); 52 #endif 53 /* Replace a call to get_clock_freq (after it is implemented)*/ 54 #define CONFIG_SYS_CLK_FREQ 66666666 55 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 56 57 #ifdef CONFIG_ATM 58 #define CONFIG_PQ_MDS_PIB 59 #define CONFIG_PQ_MDS_PIB_ATM 60 #endif 61 62 /* 63 * These can be toggled for performance analysis, otherwise use default. 64 */ 65 #define CONFIG_L2_CACHE /* toggle L2 cache */ 66 #define CONFIG_BTB /* toggle branch predition */ 67 68 #ifdef CONFIG_NAND 69 #define CONFIG_NAND_U_BOOT 1 70 #define CONFIG_RAMBOOT_NAND 1 71 #ifdef CONFIG_NAND_SPL 72 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 73 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ 74 #else 75 #define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds 76 #define CONFIG_SYS_TEXT_BASE 0xf8f82000 77 #endif 78 #endif 79 80 #ifndef CONFIG_SYS_TEXT_BASE 81 #define CONFIG_SYS_TEXT_BASE 0xfff80000 82 #endif 83 84 #ifndef CONFIG_SYS_MONITOR_BASE 85 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 86 #endif 87 88 /* 89 * Only possible on E500 Version 2 or newer cores. 90 */ 91 #define CONFIG_ENABLE_36BIT_PHYS 1 92 93 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 94 #define CONFIG_BOARD_EARLY_INIT_R 1 95 #define CONFIG_HWCONFIG 96 97 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 98 #define CONFIG_SYS_MEMTEST_END 0x00400000 99 100 /* 101 * Config the L2 Cache as L2 SRAM 102 */ 103 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 104 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 105 #define CONFIG_SYS_L2_SIZE (512 << 10) 106 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 107 108 #define CONFIG_SYS_CCSRBAR 0xe0000000 109 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 110 111 #if defined(CONFIG_NAND_SPL) 112 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 113 #endif 114 115 /* DDR Setup */ 116 #define CONFIG_FSL_DDR3 117 #undef CONFIG_FSL_DDR_INTERACTIVE 118 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 119 #define CONFIG_DDR_SPD 120 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 121 122 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 123 124 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 125 /* DDR is system memory*/ 126 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 127 128 #define CONFIG_NUM_DDR_CONTROLLERS 1 129 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 130 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 131 132 /* I2C addresses of SPD EEPROMs */ 133 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 134 135 /* These are used when DDR doesn't use SPD. */ 136 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 137 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 138 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 139 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 140 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 141 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 142 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 143 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 144 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 145 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 146 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 147 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 148 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 149 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 150 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 151 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 152 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 153 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 154 #define CONFIG_SYS_DDR_CDR_1 0x80040000 155 #define CONFIG_SYS_DDR_CDR_2 0x00000000 156 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 157 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 158 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 159 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 160 161 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 162 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 163 #define CONFIG_SYS_DDR_SBE 0x00010000 164 165 #undef CONFIG_CLOCKS_IN_MHZ 166 167 /* 168 * Local Bus Definitions 169 */ 170 171 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 172 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 173 174 #define CONFIG_SYS_BCSR_BASE 0xf8000000 175 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 176 177 /*Chip select 0 - Flash*/ 178 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 179 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 180 181 /*Chip select 1 - BCSR*/ 182 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 183 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 184 185 /*Chip select 4 - PIB*/ 186 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 187 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 188 189 /*Chip select 5 - PIB*/ 190 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 191 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 192 193 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 194 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 195 #undef CONFIG_SYS_FLASH_CHECKSUM 196 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 197 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 198 199 #if defined(CONFIG_RAMBOOT_NAND) 200 #define CONFIG_SYS_RAMBOOT 201 #define CONFIG_SYS_EXTRA_ENV_RELOC 202 #else 203 #undef CONFIG_SYS_RAMBOOT 204 #endif 205 206 #define CONFIG_FLASH_CFI_DRIVER 207 #define CONFIG_SYS_FLASH_CFI 208 #define CONFIG_SYS_FLASH_EMPTY_INFO 209 210 /* Chip select 3 - NAND */ 211 #ifndef CONFIG_NAND_SPL 212 #define CONFIG_SYS_NAND_BASE 0xFC000000 213 #else 214 #define CONFIG_SYS_NAND_BASE 0xFFF00000 215 #endif 216 217 /* NAND boot: 4K NAND loader config */ 218 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 219 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 220 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 221 #define CONFIG_SYS_NAND_U_BOOT_START \ 222 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 223 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 224 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 225 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 226 227 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 228 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 229 #define CONFIG_SYS_MAX_NAND_DEVICE 1 230 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 231 #define CONFIG_CMD_NAND 1 232 #define CONFIG_NAND_FSL_ELBC 1 233 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 234 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 235 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 236 | BR_PS_8 /* Port Size = 8 bit */ \ 237 | BR_MS_FCM /* MSEL = FCM */ \ 238 | BR_V) /* valid */ 239 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 240 | OR_FCM_CSCT \ 241 | OR_FCM_CST \ 242 | OR_FCM_CHT \ 243 | OR_FCM_SCY_1 \ 244 | OR_FCM_TRLX \ 245 | OR_FCM_EHTR) 246 247 #ifdef CONFIG_RAMBOOT_NAND 248 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 249 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */ 250 #define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 251 #define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 252 #else 253 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 254 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 255 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 256 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 257 #endif 258 259 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 260 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 261 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 262 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 263 264 #define CONFIG_SYS_INIT_RAM_LOCK 1 265 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 266 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 267 268 #define CONFIG_SYS_GBL_DATA_OFFSET \ 269 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 270 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 271 272 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 273 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 274 275 /* Serial Port */ 276 #define CONFIG_CONS_INDEX 1 277 #define CONFIG_SYS_NS16550 278 #define CONFIG_SYS_NS16550_SERIAL 279 #define CONFIG_SYS_NS16550_REG_SIZE 1 280 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 281 #ifdef CONFIG_NAND_SPL 282 #define CONFIG_NS16550_MIN_FUNCTIONS 283 #endif 284 285 #define CONFIG_SYS_BAUDRATE_TABLE \ 286 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 287 288 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 289 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 290 291 /* Use the HUSH parser*/ 292 #define CONFIG_SYS_HUSH_PARSER 293 #ifdef CONFIG_SYS_HUSH_PARSER 294 #endif 295 296 /* pass open firmware flat tree */ 297 #define CONFIG_OF_LIBFDT 1 298 #define CONFIG_OF_BOARD_SETUP 1 299 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 300 301 /* 302 * I2C 303 */ 304 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 305 #define CONFIG_HARD_I2C /* I2C with hardware support*/ 306 #undef CONFIG_SOFT_I2C /* I2C bit-banged */ 307 #define CONFIG_I2C_MULTI_BUS 308 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 309 #define CONFIG_SYS_I2C_SLAVE 0x7F 310 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ 311 #define CONFIG_SYS_I2C_OFFSET 0x3000 312 #define CONFIG_SYS_I2C2_OFFSET 0x3100 313 314 /* 315 * I2C2 EEPROM 316 */ 317 #define CONFIG_ID_EEPROM 318 #ifdef CONFIG_ID_EEPROM 319 #define CONFIG_SYS_I2C_EEPROM_NXID 320 #endif 321 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 322 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 323 #define CONFIG_SYS_EEPROM_BUS_NUM 1 324 325 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 326 #define PLPPAR1_I2C2_VAL 0x00000000 327 #define PLPPAR1_ESDHC_VAL 0x0000000A 328 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 329 #define PLPDIR1_I2C2_VAL 0x0000000F 330 #define PLPDIR1_ESDHC_VAL 0x00000006 331 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 332 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 333 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 334 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 335 336 /* 337 * General PCI 338 * Memory Addresses are mapped 1-1. I/O is mapped from 0 339 */ 340 #define CONFIG_SYS_PCIE1_NAME "Slot" 341 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 342 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 343 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 344 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 345 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 346 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 347 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 348 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 349 350 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 351 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 352 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 353 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 354 355 #ifdef CONFIG_QE 356 /* 357 * QE UEC ethernet configuration 358 */ 359 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 360 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 361 362 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 363 #define CONFIG_UEC_ETH 364 #define CONFIG_ETHPRIME "UEC0" 365 #define CONFIG_PHY_MODE_NEED_CHANGE 366 367 #define CONFIG_UEC_ETH1 /* GETH1 */ 368 #define CONFIG_HAS_ETH0 369 370 #ifdef CONFIG_UEC_ETH1 371 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 372 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 373 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 374 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 375 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 376 #define CONFIG_SYS_UEC1_PHY_ADDR 7 377 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 378 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 379 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 380 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 381 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 382 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 383 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 384 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 385 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 386 #endif /* CONFIG_UEC_ETH1 */ 387 388 #define CONFIG_UEC_ETH2 /* GETH2 */ 389 #define CONFIG_HAS_ETH1 390 391 #ifdef CONFIG_UEC_ETH2 392 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 393 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 394 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 395 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 396 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 397 #define CONFIG_SYS_UEC2_PHY_ADDR 1 398 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 399 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 400 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 401 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 402 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 403 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 404 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 405 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 406 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 407 #endif /* CONFIG_UEC_ETH2 */ 408 409 #define CONFIG_UEC_ETH3 /* GETH3 */ 410 #define CONFIG_HAS_ETH2 411 412 #ifdef CONFIG_UEC_ETH3 413 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 414 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 415 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 416 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 417 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 418 #define CONFIG_SYS_UEC3_PHY_ADDR 2 419 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 420 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 421 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 422 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 423 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 424 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 425 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 426 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 427 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 428 #endif /* CONFIG_UEC_ETH3 */ 429 430 #define CONFIG_UEC_ETH4 /* GETH4 */ 431 #define CONFIG_HAS_ETH3 432 433 #ifdef CONFIG_UEC_ETH4 434 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 435 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 436 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 437 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 438 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 439 #define CONFIG_SYS_UEC4_PHY_ADDR 3 440 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 441 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 442 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 443 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 444 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 445 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 446 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 447 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 448 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 449 #endif /* CONFIG_UEC_ETH4 */ 450 451 #undef CONFIG_UEC_ETH6 /* GETH6 */ 452 #define CONFIG_HAS_ETH5 453 454 #ifdef CONFIG_UEC_ETH6 455 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 456 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 457 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 458 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 459 #define CONFIG_SYS_UEC6_PHY_ADDR 4 460 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 461 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 462 #endif /* CONFIG_UEC_ETH6 */ 463 464 #undef CONFIG_UEC_ETH8 /* GETH8 */ 465 #define CONFIG_HAS_ETH7 466 467 #ifdef CONFIG_UEC_ETH8 468 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 469 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 470 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 471 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 472 #define CONFIG_SYS_UEC8_PHY_ADDR 6 473 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 474 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 475 #endif /* CONFIG_UEC_ETH8 */ 476 477 #endif /* CONFIG_QE */ 478 479 #if defined(CONFIG_PCI) 480 481 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 482 483 #undef CONFIG_EEPRO100 484 #undef CONFIG_TULIP 485 #define CONFIG_E1000 /* Define e1000 pci Ethernet card */ 486 487 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 488 489 #endif /* CONFIG_PCI */ 490 491 /* 492 * Environment 493 */ 494 #if defined(CONFIG_SYS_RAMBOOT) 495 #if defined(CONFIG_RAMBOOT_NAND) 496 #define CONFIG_ENV_IS_IN_NAND 1 497 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 498 #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 499 #endif 500 #else 501 #define CONFIG_ENV_IS_IN_FLASH 1 502 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 503 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 504 #define CONFIG_ENV_SIZE 0x2000 505 #endif 506 507 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 508 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 509 510 /* QE microcode/firmware address */ 511 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 512 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000 513 514 /* 515 * BOOTP options 516 */ 517 #define CONFIG_BOOTP_BOOTFILESIZE 518 #define CONFIG_BOOTP_BOOTPATH 519 #define CONFIG_BOOTP_GATEWAY 520 #define CONFIG_BOOTP_HOSTNAME 521 522 523 /* 524 * Command line configuration. 525 */ 526 #include <config_cmd_default.h> 527 528 #define CONFIG_CMD_PING 529 #define CONFIG_CMD_I2C 530 #define CONFIG_CMD_MII 531 #define CONFIG_CMD_ELF 532 #define CONFIG_CMD_IRQ 533 #define CONFIG_CMD_SETEXPR 534 #define CONFIG_CMD_REGINFO 535 536 #if defined(CONFIG_PCI) 537 #define CONFIG_CMD_PCI 538 #endif 539 540 541 #undef CONFIG_WATCHDOG /* watchdog disabled */ 542 543 #define CONFIG_MMC 1 544 545 #ifdef CONFIG_MMC 546 #define CONFIG_FSL_ESDHC 547 #define CONFIG_FSL_ESDHC_PIN_MUX 548 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 549 #define CONFIG_CMD_MMC 550 #define CONFIG_GENERIC_MMC 551 #define CONFIG_CMD_EXT2 552 #define CONFIG_CMD_FAT 553 #define CONFIG_DOS_PARTITION 554 #endif 555 556 /* 557 * Miscellaneous configurable options 558 */ 559 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 560 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 561 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 562 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 563 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 564 #if defined(CONFIG_CMD_KGDB) 565 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 566 #else 567 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 568 #endif 569 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 570 /* Print Buffer Size */ 571 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 572 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 573 /* Boot Argument Buffer Size */ 574 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 575 576 /* 577 * For booting Linux, the board info and command line data 578 * have to be in the first 64 MB of memory, since this is 579 * the maximum mapped by the Linux kernel during initialization. 580 */ 581 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 582 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 583 584 #if defined(CONFIG_CMD_KGDB) 585 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 586 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 587 #endif 588 589 /* 590 * Environment Configuration 591 */ 592 #define CONFIG_HOSTNAME mpc8569mds 593 #define CONFIG_ROOTPATH "/nfsroot" 594 #define CONFIG_BOOTFILE "your.uImage" 595 596 #define CONFIG_SERVERIP 192.168.1.1 597 #define CONFIG_GATEWAYIP 192.168.1.1 598 #define CONFIG_NETMASK 255.255.255.0 599 600 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 601 602 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 603 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 604 605 #define CONFIG_BAUDRATE 115200 606 607 #define CONFIG_EXTRA_ENV_SETTINGS \ 608 "netdev=eth0\0" \ 609 "consoledev=ttyS0\0" \ 610 "ramdiskaddr=600000\0" \ 611 "ramdiskfile=your.ramdisk.u-boot\0" \ 612 "fdtaddr=400000\0" \ 613 "fdtfile=your.fdt.dtb\0" \ 614 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 615 "nfsroot=$serverip:$rootpath " \ 616 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 617 "console=$consoledev,$baudrate $othbootargs\0" \ 618 "ramargs=setenv bootargs root=/dev/ram rw " \ 619 "console=$consoledev,$baudrate $othbootargs\0" \ 620 621 #define CONFIG_NFSBOOTCOMMAND \ 622 "run nfsargs;" \ 623 "tftp $loadaddr $bootfile;" \ 624 "tftp $fdtaddr $fdtfile;" \ 625 "bootm $loadaddr - $fdtaddr" 626 627 #define CONFIG_RAMBOOTCOMMAND \ 628 "run ramargs;" \ 629 "tftp $ramdiskaddr $ramdiskfile;" \ 630 "tftp $loadaddr $bootfile;" \ 631 "bootm $loadaddr $ramdiskaddr" 632 633 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 634 635 #endif /* __CONFIG_H */ 636