1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8569mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_DISPLAY_BOARDINFO 14 15 /* High Level Configuration Options */ 16 #define CONFIG_BOOKE 1 /* BOOKE */ 17 #define CONFIG_E500 1 /* BOOKE e500 family */ 18 #define CONFIG_MPC8569 1 /* MPC8569 specific */ 19 #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ 20 21 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ 22 23 #define CONFIG_SYS_SRIO 24 #define CONFIG_SRIO1 /* SRIO port 1 */ 25 26 #define CONFIG_PCI 1 /* Disable PCI/PCIE */ 27 #define CONFIG_PCIE1 1 /* PCIE controller */ 28 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 29 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 30 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 32 #define CONFIG_QE /* Enable QE */ 33 #define CONFIG_ENV_OVERWRITE 34 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 35 36 #ifndef __ASSEMBLY__ 37 extern unsigned long get_clock_freq(void); 38 #endif 39 /* Replace a call to get_clock_freq (after it is implemented)*/ 40 #define CONFIG_SYS_CLK_FREQ 66666666 41 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 42 43 #ifdef CONFIG_ATM 44 #define CONFIG_PQ_MDS_PIB 45 #define CONFIG_PQ_MDS_PIB_ATM 46 #endif 47 48 /* 49 * These can be toggled for performance analysis, otherwise use default. 50 */ 51 #define CONFIG_L2_CACHE /* toggle L2 cache */ 52 #define CONFIG_BTB /* toggle branch predition */ 53 54 #ifndef CONFIG_SYS_TEXT_BASE 55 #define CONFIG_SYS_TEXT_BASE 0xfff80000 56 #endif 57 58 #ifndef CONFIG_SYS_MONITOR_BASE 59 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 60 #endif 61 62 /* 63 * Only possible on E500 Version 2 or newer cores. 64 */ 65 #define CONFIG_ENABLE_36BIT_PHYS 1 66 67 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 68 #define CONFIG_BOARD_EARLY_INIT_R 1 69 #define CONFIG_HWCONFIG 70 71 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 72 #define CONFIG_SYS_MEMTEST_END 0x00400000 73 74 /* 75 * Config the L2 Cache as L2 SRAM 76 */ 77 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 78 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 79 #define CONFIG_SYS_L2_SIZE (512 << 10) 80 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 81 82 #define CONFIG_SYS_CCSRBAR 0xe0000000 83 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 84 85 #if defined(CONFIG_NAND_SPL) 86 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 87 #endif 88 89 /* DDR Setup */ 90 #define CONFIG_SYS_FSL_DDR3 91 #undef CONFIG_FSL_DDR_INTERACTIVE 92 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 93 #define CONFIG_DDR_SPD 94 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 95 96 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 97 98 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 99 /* DDR is system memory*/ 100 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 101 102 #define CONFIG_NUM_DDR_CONTROLLERS 1 103 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 104 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 105 106 /* I2C addresses of SPD EEPROMs */ 107 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 108 109 /* These are used when DDR doesn't use SPD. */ 110 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 111 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 112 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 113 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 114 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 115 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 116 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 117 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 118 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 119 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 120 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 121 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 122 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 123 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 124 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 125 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 126 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 127 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 128 #define CONFIG_SYS_DDR_CDR_1 0x80040000 129 #define CONFIG_SYS_DDR_CDR_2 0x00000000 130 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 131 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 132 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 133 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 134 135 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 136 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 137 #define CONFIG_SYS_DDR_SBE 0x00010000 138 139 #undef CONFIG_CLOCKS_IN_MHZ 140 141 /* 142 * Local Bus Definitions 143 */ 144 145 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 146 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 147 148 #define CONFIG_SYS_BCSR_BASE 0xf8000000 149 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 150 151 /*Chip select 0 - Flash*/ 152 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 153 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 154 155 /*Chip select 1 - BCSR*/ 156 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 157 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 158 159 /*Chip select 4 - PIB*/ 160 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 161 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 162 163 /*Chip select 5 - PIB*/ 164 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 165 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 166 167 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 168 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 169 #undef CONFIG_SYS_FLASH_CHECKSUM 170 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 171 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 172 173 #undef CONFIG_SYS_RAMBOOT 174 175 #define CONFIG_FLASH_CFI_DRIVER 176 #define CONFIG_SYS_FLASH_CFI 177 #define CONFIG_SYS_FLASH_EMPTY_INFO 178 179 /* Chip select 3 - NAND */ 180 #ifndef CONFIG_NAND_SPL 181 #define CONFIG_SYS_NAND_BASE 0xFC000000 182 #else 183 #define CONFIG_SYS_NAND_BASE 0xFFF00000 184 #endif 185 186 /* NAND boot: 4K NAND loader config */ 187 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 188 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 189 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 190 #define CONFIG_SYS_NAND_U_BOOT_START \ 191 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 192 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 193 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 194 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 195 196 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 197 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 198 #define CONFIG_SYS_MAX_NAND_DEVICE 1 199 #define CONFIG_CMD_NAND 1 200 #define CONFIG_NAND_FSL_ELBC 1 201 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 202 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 203 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 204 | BR_PS_8 /* Port Size = 8 bit */ \ 205 | BR_MS_FCM /* MSEL = FCM */ \ 206 | BR_V) /* valid */ 207 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 208 | OR_FCM_CSCT \ 209 | OR_FCM_CST \ 210 | OR_FCM_CHT \ 211 | OR_FCM_SCY_1 \ 212 | OR_FCM_TRLX \ 213 | OR_FCM_EHTR) 214 215 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 216 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 217 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 218 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 219 220 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 221 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 222 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 223 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 224 225 #define CONFIG_SYS_INIT_RAM_LOCK 1 226 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 227 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 228 229 #define CONFIG_SYS_GBL_DATA_OFFSET \ 230 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 231 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 232 233 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 234 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 235 236 /* Serial Port */ 237 #define CONFIG_CONS_INDEX 1 238 #define CONFIG_SYS_NS16550_SERIAL 239 #define CONFIG_SYS_NS16550_REG_SIZE 1 240 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 241 #ifdef CONFIG_NAND_SPL 242 #define CONFIG_NS16550_MIN_FUNCTIONS 243 #endif 244 245 #define CONFIG_SYS_BAUDRATE_TABLE \ 246 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 247 248 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 249 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 250 251 /* Use the HUSH parser*/ 252 #define CONFIG_SYS_HUSH_PARSER 253 #ifdef CONFIG_SYS_HUSH_PARSER 254 #endif 255 256 /* 257 * I2C 258 */ 259 #define CONFIG_SYS_I2C 260 #define CONFIG_SYS_I2C_FSL 261 #define CONFIG_SYS_FSL_I2C_SPEED 400000 262 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 263 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 264 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 265 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 266 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 267 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 268 269 /* 270 * I2C2 EEPROM 271 */ 272 #define CONFIG_ID_EEPROM 273 #ifdef CONFIG_ID_EEPROM 274 #define CONFIG_SYS_I2C_EEPROM_NXID 275 #endif 276 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 277 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 278 #define CONFIG_SYS_EEPROM_BUS_NUM 1 279 280 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 281 #define PLPPAR1_I2C2_VAL 0x00000000 282 #define PLPPAR1_ESDHC_VAL 0x0000000A 283 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 284 #define PLPDIR1_I2C2_VAL 0x0000000F 285 #define PLPDIR1_ESDHC_VAL 0x00000006 286 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 287 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 288 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 289 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 290 291 /* 292 * General PCI 293 * Memory Addresses are mapped 1-1. I/O is mapped from 0 294 */ 295 #define CONFIG_SYS_PCIE1_NAME "Slot" 296 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 297 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 298 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 299 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 300 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 301 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 302 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 303 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 304 305 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 306 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 307 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 308 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 309 310 #ifdef CONFIG_QE 311 /* 312 * QE UEC ethernet configuration 313 */ 314 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 315 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 316 317 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 318 #define CONFIG_UEC_ETH 319 #define CONFIG_ETHPRIME "UEC0" 320 #define CONFIG_PHY_MODE_NEED_CHANGE 321 322 #define CONFIG_UEC_ETH1 /* GETH1 */ 323 #define CONFIG_HAS_ETH0 324 325 #ifdef CONFIG_UEC_ETH1 326 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 327 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 328 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 329 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 330 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 331 #define CONFIG_SYS_UEC1_PHY_ADDR 7 332 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 333 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 334 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 335 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 336 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 337 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 338 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 339 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 340 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 341 #endif /* CONFIG_UEC_ETH1 */ 342 343 #define CONFIG_UEC_ETH2 /* GETH2 */ 344 #define CONFIG_HAS_ETH1 345 346 #ifdef CONFIG_UEC_ETH2 347 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 348 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 349 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 350 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 351 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 352 #define CONFIG_SYS_UEC2_PHY_ADDR 1 353 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 354 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 355 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 356 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 357 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 358 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 359 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 360 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 361 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 362 #endif /* CONFIG_UEC_ETH2 */ 363 364 #define CONFIG_UEC_ETH3 /* GETH3 */ 365 #define CONFIG_HAS_ETH2 366 367 #ifdef CONFIG_UEC_ETH3 368 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 369 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 370 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 371 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 372 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 373 #define CONFIG_SYS_UEC3_PHY_ADDR 2 374 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 375 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 376 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 377 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 378 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 379 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 380 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 381 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 382 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 383 #endif /* CONFIG_UEC_ETH3 */ 384 385 #define CONFIG_UEC_ETH4 /* GETH4 */ 386 #define CONFIG_HAS_ETH3 387 388 #ifdef CONFIG_UEC_ETH4 389 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 390 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 391 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 392 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 393 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 394 #define CONFIG_SYS_UEC4_PHY_ADDR 3 395 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 396 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 397 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 398 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 399 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 400 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 401 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 402 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 403 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 404 #endif /* CONFIG_UEC_ETH4 */ 405 406 #undef CONFIG_UEC_ETH6 /* GETH6 */ 407 #define CONFIG_HAS_ETH5 408 409 #ifdef CONFIG_UEC_ETH6 410 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 411 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 412 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 413 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 414 #define CONFIG_SYS_UEC6_PHY_ADDR 4 415 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 416 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 417 #endif /* CONFIG_UEC_ETH6 */ 418 419 #undef CONFIG_UEC_ETH8 /* GETH8 */ 420 #define CONFIG_HAS_ETH7 421 422 #ifdef CONFIG_UEC_ETH8 423 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 424 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 425 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 426 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 427 #define CONFIG_SYS_UEC8_PHY_ADDR 6 428 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 429 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 430 #endif /* CONFIG_UEC_ETH8 */ 431 432 #endif /* CONFIG_QE */ 433 434 #if defined(CONFIG_PCI) 435 436 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 437 438 #undef CONFIG_EEPRO100 439 #undef CONFIG_TULIP 440 441 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 442 443 #endif /* CONFIG_PCI */ 444 445 /* 446 * Environment 447 */ 448 #if defined(CONFIG_SYS_RAMBOOT) 449 #else 450 #define CONFIG_ENV_IS_IN_FLASH 1 451 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 452 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 453 #define CONFIG_ENV_SIZE 0x2000 454 #endif 455 456 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 457 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 458 459 /* QE microcode/firmware address */ 460 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 461 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 462 463 /* 464 * BOOTP options 465 */ 466 #define CONFIG_BOOTP_BOOTFILESIZE 467 #define CONFIG_BOOTP_BOOTPATH 468 #define CONFIG_BOOTP_GATEWAY 469 #define CONFIG_BOOTP_HOSTNAME 470 471 472 /* 473 * Command line configuration. 474 */ 475 #define CONFIG_CMD_PING 476 #define CONFIG_CMD_I2C 477 #define CONFIG_CMD_MII 478 #define CONFIG_CMD_IRQ 479 #define CONFIG_CMD_REGINFO 480 481 #if defined(CONFIG_PCI) 482 #define CONFIG_CMD_PCI 483 #endif 484 485 486 #undef CONFIG_WATCHDOG /* watchdog disabled */ 487 488 #define CONFIG_MMC 1 489 490 #ifdef CONFIG_MMC 491 #define CONFIG_FSL_ESDHC 492 #define CONFIG_FSL_ESDHC_PIN_MUX 493 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 494 #define CONFIG_CMD_MMC 495 #define CONFIG_GENERIC_MMC 496 #define CONFIG_CMD_EXT2 497 #define CONFIG_CMD_FAT 498 #define CONFIG_DOS_PARTITION 499 #endif 500 501 /* 502 * Miscellaneous configurable options 503 */ 504 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 505 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 506 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 507 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 508 #if defined(CONFIG_CMD_KGDB) 509 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 510 #else 511 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 512 #endif 513 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 514 /* Print Buffer Size */ 515 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 516 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 517 /* Boot Argument Buffer Size */ 518 519 /* 520 * For booting Linux, the board info and command line data 521 * have to be in the first 64 MB of memory, since this is 522 * the maximum mapped by the Linux kernel during initialization. 523 */ 524 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 525 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 526 527 #if defined(CONFIG_CMD_KGDB) 528 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 529 #endif 530 531 /* 532 * Environment Configuration 533 */ 534 #define CONFIG_HOSTNAME mpc8569mds 535 #define CONFIG_ROOTPATH "/nfsroot" 536 #define CONFIG_BOOTFILE "your.uImage" 537 538 #define CONFIG_SERVERIP 192.168.1.1 539 #define CONFIG_GATEWAYIP 192.168.1.1 540 #define CONFIG_NETMASK 255.255.255.0 541 542 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 543 544 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 545 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 546 547 #define CONFIG_BAUDRATE 115200 548 549 #define CONFIG_EXTRA_ENV_SETTINGS \ 550 "netdev=eth0\0" \ 551 "consoledev=ttyS0\0" \ 552 "ramdiskaddr=600000\0" \ 553 "ramdiskfile=your.ramdisk.u-boot\0" \ 554 "fdtaddr=400000\0" \ 555 "fdtfile=your.fdt.dtb\0" \ 556 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 557 "nfsroot=$serverip:$rootpath " \ 558 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 559 "console=$consoledev,$baudrate $othbootargs\0" \ 560 "ramargs=setenv bootargs root=/dev/ram rw " \ 561 "console=$consoledev,$baudrate $othbootargs\0" \ 562 563 #define CONFIG_NFSBOOTCOMMAND \ 564 "run nfsargs;" \ 565 "tftp $loadaddr $bootfile;" \ 566 "tftp $fdtaddr $fdtfile;" \ 567 "bootm $loadaddr - $fdtaddr" 568 569 #define CONFIG_RAMBOOTCOMMAND \ 570 "run ramargs;" \ 571 "tftp $ramdiskaddr $ramdiskfile;" \ 572 "tftp $loadaddr $bootfile;" \ 573 "bootm $loadaddr $ramdiskaddr" 574 575 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 576 577 #endif /* __CONFIG_H */ 578