1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8569mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* High Level Configuration Options */ 14 #define CONFIG_BOOKE 1 /* BOOKE */ 15 #define CONFIG_E500 1 /* BOOKE e500 family */ 16 17 #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ 18 19 #define CONFIG_SYS_SRIO 20 #define CONFIG_SRIO1 /* SRIO port 1 */ 21 22 #define CONFIG_PCIE1 1 /* PCIE controller */ 23 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 24 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 25 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 26 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 27 #define CONFIG_QE /* Enable QE */ 28 #define CONFIG_ENV_OVERWRITE 29 30 #ifndef __ASSEMBLY__ 31 extern unsigned long get_clock_freq(void); 32 #endif 33 /* Replace a call to get_clock_freq (after it is implemented)*/ 34 #define CONFIG_SYS_CLK_FREQ 66666666 35 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 36 37 #ifdef CONFIG_ATM 38 #define CONFIG_PQ_MDS_PIB 39 #define CONFIG_PQ_MDS_PIB_ATM 40 #endif 41 42 /* 43 * These can be toggled for performance analysis, otherwise use default. 44 */ 45 #define CONFIG_L2_CACHE /* toggle L2 cache */ 46 #define CONFIG_BTB /* toggle branch predition */ 47 48 #ifndef CONFIG_SYS_TEXT_BASE 49 #define CONFIG_SYS_TEXT_BASE 0xfff80000 50 #endif 51 52 #ifndef CONFIG_SYS_MONITOR_BASE 53 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 54 #endif 55 56 /* 57 * Only possible on E500 Version 2 or newer cores. 58 */ 59 #define CONFIG_ENABLE_36BIT_PHYS 1 60 61 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 62 #define CONFIG_BOARD_EARLY_INIT_R 1 63 #define CONFIG_HWCONFIG 64 65 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 66 #define CONFIG_SYS_MEMTEST_END 0x00400000 67 68 /* 69 * Config the L2 Cache as L2 SRAM 70 */ 71 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 72 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 73 #define CONFIG_SYS_L2_SIZE (512 << 10) 74 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 75 76 #define CONFIG_SYS_CCSRBAR 0xe0000000 77 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 78 79 #if defined(CONFIG_NAND_SPL) 80 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 81 #endif 82 83 /* DDR Setup */ 84 #define CONFIG_SYS_FSL_DDR3 85 #undef CONFIG_FSL_DDR_INTERACTIVE 86 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 87 #define CONFIG_DDR_SPD 88 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 89 90 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 91 92 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 93 /* DDR is system memory*/ 94 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 95 96 #define CONFIG_NUM_DDR_CONTROLLERS 1 97 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 98 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 99 100 /* I2C addresses of SPD EEPROMs */ 101 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 102 103 /* These are used when DDR doesn't use SPD. */ 104 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 105 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 106 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 107 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 108 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 109 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 110 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 111 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 112 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 113 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 114 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 115 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 116 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 117 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 118 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 119 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 120 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 121 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 122 #define CONFIG_SYS_DDR_CDR_1 0x80040000 123 #define CONFIG_SYS_DDR_CDR_2 0x00000000 124 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 125 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 126 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 127 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 128 129 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 130 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 131 #define CONFIG_SYS_DDR_SBE 0x00010000 132 133 #undef CONFIG_CLOCKS_IN_MHZ 134 135 /* 136 * Local Bus Definitions 137 */ 138 139 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 140 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 141 142 #define CONFIG_SYS_BCSR_BASE 0xf8000000 143 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 144 145 /*Chip select 0 - Flash*/ 146 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 147 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 148 149 /*Chip select 1 - BCSR*/ 150 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 151 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 152 153 /*Chip select 4 - PIB*/ 154 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 155 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 156 157 /*Chip select 5 - PIB*/ 158 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 159 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 160 161 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 162 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 163 #undef CONFIG_SYS_FLASH_CHECKSUM 164 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 165 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 166 167 #undef CONFIG_SYS_RAMBOOT 168 169 #define CONFIG_FLASH_CFI_DRIVER 170 #define CONFIG_SYS_FLASH_CFI 171 #define CONFIG_SYS_FLASH_EMPTY_INFO 172 173 /* Chip select 3 - NAND */ 174 #ifndef CONFIG_NAND_SPL 175 #define CONFIG_SYS_NAND_BASE 0xFC000000 176 #else 177 #define CONFIG_SYS_NAND_BASE 0xFFF00000 178 #endif 179 180 /* NAND boot: 4K NAND loader config */ 181 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 182 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 183 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 184 #define CONFIG_SYS_NAND_U_BOOT_START \ 185 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 186 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 187 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 188 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 189 190 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 191 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 192 #define CONFIG_SYS_MAX_NAND_DEVICE 1 193 #define CONFIG_CMD_NAND 1 194 #define CONFIG_NAND_FSL_ELBC 1 195 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 196 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 197 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 198 | BR_PS_8 /* Port Size = 8 bit */ \ 199 | BR_MS_FCM /* MSEL = FCM */ \ 200 | BR_V) /* valid */ 201 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 202 | OR_FCM_CSCT \ 203 | OR_FCM_CST \ 204 | OR_FCM_CHT \ 205 | OR_FCM_SCY_1 \ 206 | OR_FCM_TRLX \ 207 | OR_FCM_EHTR) 208 209 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 210 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 211 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 212 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 213 214 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 215 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 216 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 217 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 218 219 #define CONFIG_SYS_INIT_RAM_LOCK 1 220 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 221 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 222 223 #define CONFIG_SYS_GBL_DATA_OFFSET \ 224 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 225 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 226 227 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 228 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 229 230 /* Serial Port */ 231 #define CONFIG_CONS_INDEX 1 232 #define CONFIG_SYS_NS16550_SERIAL 233 #define CONFIG_SYS_NS16550_REG_SIZE 1 234 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 235 #ifdef CONFIG_NAND_SPL 236 #define CONFIG_NS16550_MIN_FUNCTIONS 237 #endif 238 239 #define CONFIG_SYS_BAUDRATE_TABLE \ 240 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 241 242 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 243 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 244 245 /* 246 * I2C 247 */ 248 #define CONFIG_SYS_I2C 249 #define CONFIG_SYS_I2C_FSL 250 #define CONFIG_SYS_FSL_I2C_SPEED 400000 251 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 252 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 253 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 254 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 255 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 256 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 257 258 /* 259 * I2C2 EEPROM 260 */ 261 #define CONFIG_ID_EEPROM 262 #ifdef CONFIG_ID_EEPROM 263 #define CONFIG_SYS_I2C_EEPROM_NXID 264 #endif 265 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 266 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 267 #define CONFIG_SYS_EEPROM_BUS_NUM 1 268 269 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 270 #define PLPPAR1_I2C2_VAL 0x00000000 271 #define PLPPAR1_ESDHC_VAL 0x0000000A 272 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 273 #define PLPDIR1_I2C2_VAL 0x0000000F 274 #define PLPDIR1_ESDHC_VAL 0x00000006 275 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 276 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 277 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 278 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 279 280 /* 281 * General PCI 282 * Memory Addresses are mapped 1-1. I/O is mapped from 0 283 */ 284 #define CONFIG_SYS_PCIE1_NAME "Slot" 285 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 286 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 287 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 288 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 289 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 290 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 291 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 292 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 293 294 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 295 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 296 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 297 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 298 299 #ifdef CONFIG_QE 300 /* 301 * QE UEC ethernet configuration 302 */ 303 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 304 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 305 306 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 307 #define CONFIG_UEC_ETH 308 #define CONFIG_ETHPRIME "UEC0" 309 #define CONFIG_PHY_MODE_NEED_CHANGE 310 311 #define CONFIG_UEC_ETH1 /* GETH1 */ 312 #define CONFIG_HAS_ETH0 313 314 #ifdef CONFIG_UEC_ETH1 315 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 316 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 317 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 318 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 319 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 320 #define CONFIG_SYS_UEC1_PHY_ADDR 7 321 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 322 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 323 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 324 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 325 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 326 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 327 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 328 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 329 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 330 #endif /* CONFIG_UEC_ETH1 */ 331 332 #define CONFIG_UEC_ETH2 /* GETH2 */ 333 #define CONFIG_HAS_ETH1 334 335 #ifdef CONFIG_UEC_ETH2 336 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 337 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 338 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 339 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 340 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 341 #define CONFIG_SYS_UEC2_PHY_ADDR 1 342 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 343 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 344 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 345 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 346 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 347 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 348 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 349 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 350 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 351 #endif /* CONFIG_UEC_ETH2 */ 352 353 #define CONFIG_UEC_ETH3 /* GETH3 */ 354 #define CONFIG_HAS_ETH2 355 356 #ifdef CONFIG_UEC_ETH3 357 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 358 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 359 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 360 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 361 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 362 #define CONFIG_SYS_UEC3_PHY_ADDR 2 363 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 364 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 365 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 366 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 367 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 368 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 369 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 370 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 371 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 372 #endif /* CONFIG_UEC_ETH3 */ 373 374 #define CONFIG_UEC_ETH4 /* GETH4 */ 375 #define CONFIG_HAS_ETH3 376 377 #ifdef CONFIG_UEC_ETH4 378 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 379 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 380 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 381 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 382 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 383 #define CONFIG_SYS_UEC4_PHY_ADDR 3 384 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 385 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 386 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 387 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 388 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 389 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 390 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 391 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 392 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 393 #endif /* CONFIG_UEC_ETH4 */ 394 395 #undef CONFIG_UEC_ETH6 /* GETH6 */ 396 #define CONFIG_HAS_ETH5 397 398 #ifdef CONFIG_UEC_ETH6 399 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 400 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 401 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 402 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 403 #define CONFIG_SYS_UEC6_PHY_ADDR 4 404 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 405 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 406 #endif /* CONFIG_UEC_ETH6 */ 407 408 #undef CONFIG_UEC_ETH8 /* GETH8 */ 409 #define CONFIG_HAS_ETH7 410 411 #ifdef CONFIG_UEC_ETH8 412 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 413 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 414 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 415 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 416 #define CONFIG_SYS_UEC8_PHY_ADDR 6 417 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 418 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 419 #endif /* CONFIG_UEC_ETH8 */ 420 421 #endif /* CONFIG_QE */ 422 423 #if defined(CONFIG_PCI) 424 #undef CONFIG_EEPRO100 425 #undef CONFIG_TULIP 426 427 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 428 429 #endif /* CONFIG_PCI */ 430 431 /* 432 * Environment 433 */ 434 #if defined(CONFIG_SYS_RAMBOOT) 435 #else 436 #define CONFIG_ENV_IS_IN_FLASH 1 437 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 438 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 439 #define CONFIG_ENV_SIZE 0x2000 440 #endif 441 442 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 443 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 444 445 /* QE microcode/firmware address */ 446 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 447 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 448 449 /* 450 * BOOTP options 451 */ 452 #define CONFIG_BOOTP_BOOTFILESIZE 453 #define CONFIG_BOOTP_BOOTPATH 454 #define CONFIG_BOOTP_GATEWAY 455 #define CONFIG_BOOTP_HOSTNAME 456 457 /* 458 * Command line configuration. 459 */ 460 #define CONFIG_CMD_IRQ 461 #define CONFIG_CMD_REGINFO 462 463 #if defined(CONFIG_PCI) 464 #define CONFIG_CMD_PCI 465 #endif 466 467 #undef CONFIG_WATCHDOG /* watchdog disabled */ 468 469 #ifdef CONFIG_MMC 470 #define CONFIG_FSL_ESDHC 471 #define CONFIG_FSL_ESDHC_PIN_MUX 472 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 473 #define CONFIG_GENERIC_MMC 474 #define CONFIG_DOS_PARTITION 475 #endif 476 477 /* 478 * Miscellaneous configurable options 479 */ 480 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 481 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 482 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 483 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 484 #if defined(CONFIG_CMD_KGDB) 485 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 486 #else 487 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 488 #endif 489 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 490 /* Print Buffer Size */ 491 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 492 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 493 /* Boot Argument Buffer Size */ 494 495 /* 496 * For booting Linux, the board info and command line data 497 * have to be in the first 64 MB of memory, since this is 498 * the maximum mapped by the Linux kernel during initialization. 499 */ 500 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 501 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 502 503 #if defined(CONFIG_CMD_KGDB) 504 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 505 #endif 506 507 /* 508 * Environment Configuration 509 */ 510 #define CONFIG_HOSTNAME mpc8569mds 511 #define CONFIG_ROOTPATH "/nfsroot" 512 #define CONFIG_BOOTFILE "your.uImage" 513 514 #define CONFIG_SERVERIP 192.168.1.1 515 #define CONFIG_GATEWAYIP 192.168.1.1 516 #define CONFIG_NETMASK 255.255.255.0 517 518 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 519 520 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 521 522 #define CONFIG_BAUDRATE 115200 523 524 #define CONFIG_EXTRA_ENV_SETTINGS \ 525 "netdev=eth0\0" \ 526 "consoledev=ttyS0\0" \ 527 "ramdiskaddr=600000\0" \ 528 "ramdiskfile=your.ramdisk.u-boot\0" \ 529 "fdtaddr=400000\0" \ 530 "fdtfile=your.fdt.dtb\0" \ 531 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 532 "nfsroot=$serverip:$rootpath " \ 533 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 534 "console=$consoledev,$baudrate $othbootargs\0" \ 535 "ramargs=setenv bootargs root=/dev/ram rw " \ 536 "console=$consoledev,$baudrate $othbootargs\0" \ 537 538 #define CONFIG_NFSBOOTCOMMAND \ 539 "run nfsargs;" \ 540 "tftp $loadaddr $bootfile;" \ 541 "tftp $fdtaddr $fdtfile;" \ 542 "bootm $loadaddr - $fdtaddr" 543 544 #define CONFIG_RAMBOOTCOMMAND \ 545 "run ramargs;" \ 546 "tftp $ramdiskaddr $ramdiskfile;" \ 547 "tftp $loadaddr $bootfile;" \ 548 "bootm $loadaddr $ramdiskaddr" 549 550 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 551 552 #endif /* __CONFIG_H */ 553