1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * mpc8569mds board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_SYS_SRIO 14 #define CONFIG_SRIO1 /* SRIO port 1 */ 15 16 #define CONFIG_PCIE1 1 /* PCIE controller */ 17 #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ 18 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 19 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ 20 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 21 #define CONFIG_QE /* Enable QE */ 22 #define CONFIG_ENV_OVERWRITE 23 24 #ifndef __ASSEMBLY__ 25 extern unsigned long get_clock_freq(void); 26 #endif 27 /* Replace a call to get_clock_freq (after it is implemented)*/ 28 #define CONFIG_SYS_CLK_FREQ 66666666 29 #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ 30 31 #ifdef CONFIG_ATM 32 #define CONFIG_PQ_MDS_PIB 33 #define CONFIG_PQ_MDS_PIB_ATM 34 #endif 35 36 /* 37 * These can be toggled for performance analysis, otherwise use default. 38 */ 39 #define CONFIG_L2_CACHE /* toggle L2 cache */ 40 #define CONFIG_BTB /* toggle branch predition */ 41 42 #ifndef CONFIG_SYS_TEXT_BASE 43 #define CONFIG_SYS_TEXT_BASE 0xfff80000 44 #endif 45 46 #ifndef CONFIG_SYS_MONITOR_BASE 47 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 48 #endif 49 50 /* 51 * Only possible on E500 Version 2 or newer cores. 52 */ 53 #define CONFIG_ENABLE_36BIT_PHYS 1 54 55 #define CONFIG_BOARD_EARLY_INIT_R 1 56 #define CONFIG_HWCONFIG 57 58 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 59 #define CONFIG_SYS_MEMTEST_END 0x00400000 60 61 /* 62 * Config the L2 Cache as L2 SRAM 63 */ 64 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 65 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 66 #define CONFIG_SYS_L2_SIZE (512 << 10) 67 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 68 69 #define CONFIG_SYS_CCSRBAR 0xe0000000 70 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 71 72 #if defined(CONFIG_NAND_SPL) 73 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 74 #endif 75 76 /* DDR Setup */ 77 #undef CONFIG_FSL_DDR_INTERACTIVE 78 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 79 #define CONFIG_DDR_SPD 80 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 81 82 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 83 84 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 85 /* DDR is system memory*/ 86 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 87 88 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 89 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 90 91 /* I2C addresses of SPD EEPROMs */ 92 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 93 94 /* These are used when DDR doesn't use SPD. */ 95 #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ 96 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 97 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 98 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 99 #define CONFIG_SYS_DDR_TIMING_0 0x00330004 100 #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 101 #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 102 #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 103 #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 104 #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 105 #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 106 #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 107 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 108 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 109 #define CONFIG_SYS_DDR_TIMING_4 0x00220001 110 #define CONFIG_SYS_DDR_TIMING_5 0x03402400 111 #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 112 #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 113 #define CONFIG_SYS_DDR_CDR_1 0x80040000 114 #define CONFIG_SYS_DDR_CDR_2 0x00000000 115 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 116 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 117 #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ 118 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 119 120 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 121 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 122 #define CONFIG_SYS_DDR_SBE 0x00010000 123 124 #undef CONFIG_CLOCKS_IN_MHZ 125 126 /* 127 * Local Bus Definitions 128 */ 129 130 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ 131 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 132 133 #define CONFIG_SYS_BCSR_BASE 0xf8000000 134 #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE 135 136 /*Chip select 0 - Flash*/ 137 #define CONFIG_FLASH_BR_PRELIM 0xfe000801 138 #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 139 140 /*Chip select 1 - BCSR*/ 141 #define CONFIG_SYS_BR1_PRELIM 0xf8000801 142 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 143 144 /*Chip select 4 - PIB*/ 145 #define CONFIG_SYS_BR4_PRELIM 0xf8008801 146 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 147 148 /*Chip select 5 - PIB*/ 149 #define CONFIG_SYS_BR5_PRELIM 0xf8010801 150 #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 151 152 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 153 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ 154 #undef CONFIG_SYS_FLASH_CHECKSUM 155 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 156 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 157 158 #undef CONFIG_SYS_RAMBOOT 159 160 #define CONFIG_FLASH_CFI_DRIVER 161 #define CONFIG_SYS_FLASH_CFI 162 #define CONFIG_SYS_FLASH_EMPTY_INFO 163 164 /* Chip select 3 - NAND */ 165 #ifndef CONFIG_NAND_SPL 166 #define CONFIG_SYS_NAND_BASE 0xFC000000 167 #else 168 #define CONFIG_SYS_NAND_BASE 0xFFF00000 169 #endif 170 171 /* NAND boot: 4K NAND loader config */ 172 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 173 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 174 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 175 #define CONFIG_SYS_NAND_U_BOOT_START \ 176 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 177 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 178 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 179 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 180 181 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 182 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } 183 #define CONFIG_SYS_MAX_NAND_DEVICE 1 184 #define CONFIG_CMD_NAND 1 185 #define CONFIG_NAND_FSL_ELBC 1 186 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 187 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ 188 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 189 | BR_PS_8 /* Port Size = 8 bit */ \ 190 | BR_MS_FCM /* MSEL = FCM */ \ 191 | BR_V) /* valid */ 192 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 193 | OR_FCM_CSCT \ 194 | OR_FCM_CST \ 195 | OR_FCM_CHT \ 196 | OR_FCM_SCY_1 \ 197 | OR_FCM_TRLX \ 198 | OR_FCM_EHTR) 199 200 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 201 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 202 #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 203 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 204 205 #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ 206 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ 207 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 208 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ 209 210 #define CONFIG_SYS_INIT_RAM_LOCK 1 211 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 212 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 213 214 #define CONFIG_SYS_GBL_DATA_OFFSET \ 215 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 216 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 217 218 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 219 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 220 221 /* Serial Port */ 222 #define CONFIG_CONS_INDEX 1 223 #define CONFIG_SYS_NS16550_SERIAL 224 #define CONFIG_SYS_NS16550_REG_SIZE 1 225 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 226 #ifdef CONFIG_NAND_SPL 227 #define CONFIG_NS16550_MIN_FUNCTIONS 228 #endif 229 230 #define CONFIG_SYS_BAUDRATE_TABLE \ 231 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 232 233 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 234 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 235 236 /* 237 * I2C 238 */ 239 #define CONFIG_SYS_I2C 240 #define CONFIG_SYS_I2C_FSL 241 #define CONFIG_SYS_FSL_I2C_SPEED 400000 242 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 243 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 244 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 245 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 246 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 247 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 248 249 /* 250 * I2C2 EEPROM 251 */ 252 #define CONFIG_ID_EEPROM 253 #ifdef CONFIG_ID_EEPROM 254 #define CONFIG_SYS_I2C_EEPROM_NXID 255 #endif 256 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 257 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 258 #define CONFIG_SYS_EEPROM_BUS_NUM 1 259 260 #define PLPPAR1_I2C_BIT_MASK 0x0000000F 261 #define PLPPAR1_I2C2_VAL 0x00000000 262 #define PLPPAR1_ESDHC_VAL 0x0000000A 263 #define PLPDIR1_I2C_BIT_MASK 0x0000000F 264 #define PLPDIR1_I2C2_VAL 0x0000000F 265 #define PLPDIR1_ESDHC_VAL 0x00000006 266 #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 267 #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 268 #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 269 #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 270 271 /* 272 * General PCI 273 * Memory Addresses are mapped 1-1. I/O is mapped from 0 274 */ 275 #define CONFIG_SYS_PCIE1_NAME "Slot" 276 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 277 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 278 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 279 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 280 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 281 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 282 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 283 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ 284 285 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 286 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 287 #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS 288 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ 289 290 #ifdef CONFIG_QE 291 /* 292 * QE UEC ethernet configuration 293 */ 294 #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ 295 #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ 296 297 #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) 298 #define CONFIG_UEC_ETH 299 #define CONFIG_ETHPRIME "UEC0" 300 #define CONFIG_PHY_MODE_NEED_CHANGE 301 302 #define CONFIG_UEC_ETH1 /* GETH1 */ 303 #define CONFIG_HAS_ETH0 304 305 #ifdef CONFIG_UEC_ETH1 306 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ 307 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE 308 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 309 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 310 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH 311 #define CONFIG_SYS_UEC1_PHY_ADDR 7 312 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 313 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 314 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 315 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ 316 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH 317 #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ 318 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 319 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 320 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 321 #endif /* CONFIG_UEC_ETH1 */ 322 323 #define CONFIG_UEC_ETH2 /* GETH2 */ 324 #define CONFIG_HAS_ETH1 325 326 #ifdef CONFIG_UEC_ETH2 327 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ 328 #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE 329 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 330 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 331 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH 332 #define CONFIG_SYS_UEC2_PHY_ADDR 1 333 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 334 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 335 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 336 #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ 337 #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH 338 #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ 339 #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 340 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 341 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 342 #endif /* CONFIG_UEC_ETH2 */ 343 344 #define CONFIG_UEC_ETH3 /* GETH3 */ 345 #define CONFIG_HAS_ETH2 346 347 #ifdef CONFIG_UEC_ETH3 348 #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ 349 #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE 350 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 351 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 352 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH 353 #define CONFIG_SYS_UEC3_PHY_ADDR 2 354 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 355 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 356 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 357 #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ 358 #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH 359 #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ 360 #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 361 #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 362 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 363 #endif /* CONFIG_UEC_ETH3 */ 364 365 #define CONFIG_UEC_ETH4 /* GETH4 */ 366 #define CONFIG_HAS_ETH3 367 368 #ifdef CONFIG_UEC_ETH4 369 #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ 370 #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE 371 #if defined(CONFIG_SYS_UCC_RGMII_MODE) 372 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 373 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH 374 #define CONFIG_SYS_UEC4_PHY_ADDR 3 375 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID 376 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 377 #elif defined(CONFIG_SYS_UCC_RMII_MODE) 378 #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ 379 #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH 380 #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ 381 #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII 382 #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 383 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ 384 #endif /* CONFIG_UEC_ETH4 */ 385 386 #undef CONFIG_UEC_ETH6 /* GETH6 */ 387 #define CONFIG_HAS_ETH5 388 389 #ifdef CONFIG_UEC_ETH6 390 #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ 391 #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE 392 #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE 393 #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH 394 #define CONFIG_SYS_UEC6_PHY_ADDR 4 395 #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 396 #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 397 #endif /* CONFIG_UEC_ETH6 */ 398 399 #undef CONFIG_UEC_ETH8 /* GETH8 */ 400 #define CONFIG_HAS_ETH7 401 402 #ifdef CONFIG_UEC_ETH8 403 #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ 404 #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE 405 #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE 406 #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH 407 #define CONFIG_SYS_UEC8_PHY_ADDR 6 408 #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII 409 #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 410 #endif /* CONFIG_UEC_ETH8 */ 411 412 #endif /* CONFIG_QE */ 413 414 #if defined(CONFIG_PCI) 415 #undef CONFIG_EEPRO100 416 #undef CONFIG_TULIP 417 418 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 419 420 #endif /* CONFIG_PCI */ 421 422 /* 423 * Environment 424 */ 425 #if defined(CONFIG_SYS_RAMBOOT) 426 #else 427 #define CONFIG_ENV_IS_IN_FLASH 1 428 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 429 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 430 #define CONFIG_ENV_SIZE 0x2000 431 #endif 432 433 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 434 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 435 436 /* QE microcode/firmware address */ 437 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 438 #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 439 440 /* 441 * BOOTP options 442 */ 443 #define CONFIG_BOOTP_BOOTFILESIZE 444 #define CONFIG_BOOTP_BOOTPATH 445 #define CONFIG_BOOTP_GATEWAY 446 #define CONFIG_BOOTP_HOSTNAME 447 448 /* 449 * Command line configuration. 450 */ 451 #define CONFIG_CMD_IRQ 452 #define CONFIG_CMD_REGINFO 453 454 #if defined(CONFIG_PCI) 455 #define CONFIG_CMD_PCI 456 #endif 457 458 #undef CONFIG_WATCHDOG /* watchdog disabled */ 459 460 #ifdef CONFIG_MMC 461 #define CONFIG_FSL_ESDHC 462 #define CONFIG_FSL_ESDHC_PIN_MUX 463 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 464 #endif 465 466 /* 467 * Miscellaneous configurable options 468 */ 469 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 470 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 471 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 472 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 473 #if defined(CONFIG_CMD_KGDB) 474 #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ 475 #else 476 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 477 #endif 478 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 479 /* Print Buffer Size */ 480 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 481 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 482 /* Boot Argument Buffer Size */ 483 484 /* 485 * For booting Linux, the board info and command line data 486 * have to be in the first 64 MB of memory, since this is 487 * the maximum mapped by the Linux kernel during initialization. 488 */ 489 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 490 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 491 492 #if defined(CONFIG_CMD_KGDB) 493 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 494 #endif 495 496 /* 497 * Environment Configuration 498 */ 499 #define CONFIG_HOSTNAME mpc8569mds 500 #define CONFIG_ROOTPATH "/nfsroot" 501 #define CONFIG_BOOTFILE "your.uImage" 502 503 #define CONFIG_SERVERIP 192.168.1.1 504 #define CONFIG_GATEWAYIP 192.168.1.1 505 #define CONFIG_NETMASK 255.255.255.0 506 507 #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ 508 509 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ 510 511 #define CONFIG_EXTRA_ENV_SETTINGS \ 512 "netdev=eth0\0" \ 513 "consoledev=ttyS0\0" \ 514 "ramdiskaddr=600000\0" \ 515 "ramdiskfile=your.ramdisk.u-boot\0" \ 516 "fdtaddr=400000\0" \ 517 "fdtfile=your.fdt.dtb\0" \ 518 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 519 "nfsroot=$serverip:$rootpath " \ 520 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 521 "console=$consoledev,$baudrate $othbootargs\0" \ 522 "ramargs=setenv bootargs root=/dev/ram rw " \ 523 "console=$consoledev,$baudrate $othbootargs\0" \ 524 525 #define CONFIG_NFSBOOTCOMMAND \ 526 "run nfsargs;" \ 527 "tftp $loadaddr $bootfile;" \ 528 "tftp $fdtaddr $fdtfile;" \ 529 "bootm $loadaddr - $fdtaddr" 530 531 #define CONFIG_RAMBOOTCOMMAND \ 532 "run ramargs;" \ 533 "tftp $ramdiskaddr $ramdiskfile;" \ 534 "tftp $loadaddr $bootfile;" \ 535 "bootm $loadaddr $ramdiskaddr" 536 537 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 538 539 #endif /* __CONFIG_H */ 540